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Program appropriate value of DIV[ODIV], DIV[RDIV] and DIV[MFI] as per Integer mode. 2. Wait for 5 =CE=BCs. 3. Program the following field in CTRL register. Set CTRL[POWERUP] to 1'b1 to enable PLL block. 4. Poll PLL_STATUS[PLL_LOCK] register, and wait till PLL_STATUS[PLL_LOCK] is 1'b1 and pll_lock output signal is 1'b1. 5. Set CTRL[CLKMUX_EN] to 1'b1 to enable PLL output clock. So move the CLKMUX_EN operation after PLL locked. Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") Co-developed-by: Jacky Bai Signed-off-by: Jacky Bai Signed-off-by: Peng Fan --- drivers/clk/imx/clk-fracn-gppll.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-= gppll.c index 591e0364ee5c113859a7b6271c8c11e98a0e0ffc..4749c3e0b7051cf53876664808a= a28742f6861f7 100644 --- a/drivers/clk/imx/clk-fracn-gppll.c +++ b/drivers/clk/imx/clk-fracn-gppll.c @@ -303,13 +303,13 @@ static int clk_fracn_gppll_prepare(struct clk_hw *hw) val |=3D POWERUP_MASK; writel_relaxed(val, pll->base + PLL_CTRL); =20 - val |=3D CLKMUX_EN; - writel_relaxed(val, pll->base + PLL_CTRL); - ret =3D clk_fracn_gppll_wait_lock(pll); if (ret) return ret; =20 + val |=3D CLKMUX_EN; + writel_relaxed(val, pll->base + PLL_CTRL); + val &=3D ~CLKMUX_BYPASS; writel_relaxed(val, pll->base + PLL_CTRL); =20 --=20 2.37.1