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charset="utf-8" Add a panel-timing node to panel node to override any fixed display modes written in a panel driver. This way, 68.9MHz clock frequency specified in panel-timing node may accommodate 7-fold 482.3MHz "media_ldb" clock which is derived from 964.6MHz "video_pll1" clock. The above clock frequencies align to the clock rates assigned in the lvds_bridge node and media_blk_ctrl node in this DT file. This should be able to suppress this LDB driver warning: [ 17.206644] fsl-ldb 32ec0000.blk-ctrl:bridge@5c: Configured LDB clock (7= 0000000 Hz) does not match requested LVDS clock: 490000000 Hz This also makes the display mode used by the panel pass mode validation against pixel clock rate and "media_ldb" clock rate in a certain display driver. Fixes: 6d382d51d979 ("arm64: dts: freescale: Add SKOV IMX8MP CPU revB board= ") Signed-off-by: Liu Ying --- v2: * No change. .../freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.= dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts index 3c2efdc59bfa..4e9f76de7462 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts @@ -13,6 +13,21 @@ panel { backlight =3D <&backlight>; power-supply =3D <®_tft_vcom>; =20 + panel-timing { + clock-frequency =3D <68900000>; + hactive =3D <1280>; + vactive =3D <800>; + hfront-porch =3D <30>; + hback-porch =3D <30>; + hsync-len =3D <10>; + vfront-porch =3D <5>; + vback-porch =3D <5>; + vsync-len =3D <5>; + hsync-active =3D <0>; + vsync-active =3D <0>; + de-active =3D <1>; + }; + port { in_lvds0: endpoint { remote-endpoint =3D <&ldb_lvds_ch0>; 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charset="utf-8" Add a panel-timing node to panel-lvds node to override any fixed display modes written in a panel driver. This way, 74.25MHz clock frequency specified in panel-timing node may accommodate 7-fold 519.75MHz "media_ldb" clock which is derived from 1.0395GHz "video_pll1" clock. This should suppress this LDB driver warning: [ 17.923709] fsl-ldb 32ec0000.blk-ctrl:bridge@5c: Configured LDB clock (7= 2400000 Hz) does not match requested LVDS clock: 506800000 Hz This also makes the display mode used by the panel pass mode validation against pixel clock rate and "media_ldb" clock rate in a certain display driver. Fixes: 326d86e197fc ("arm64: dts: imx8mp-phyboard-pollux-rdk: add etml pane= l support") Signed-off-by: Liu Ying --- v2: * No change. .../dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b= /arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts index 50debe821c42..20cb5363cccb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts @@ -37,6 +37,21 @@ panel1_lvds: panel-lvds { backlight =3D <&backlight_lvds>; power-supply =3D <®_vcc_3v3_sw>; =20 + panel-timing { + clock-frequency =3D <74250000>; + hactive =3D <1280>; + vactive =3D <800>; + hfront-porch =3D <72>; + hback-porch =3D <86>; + hsync-len =3D <2>; + vfront-porch =3D <15>; + vback-porch =3D <21>; + vsync-len =3D <2>; + hsync-active =3D <0>; + vsync-active =3D <0>; + de-active =3D <1>; + }; + port { panel1_in: endpoint { remote-endpoint =3D <&ldb_lvds_ch1>; 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charset="utf-8" The next bridge in bridge chain could be a panel bridge or a non-panel bridge. Use devm_drm_of_get_bridge() to replace the combination function calls of of_drm_find_panel() and devm_drm_panel_bridge_add() to get either a panel bridge or a non-panel bridge, instead of getting a panel bridge only. Signed-off-by: Liu Ying Reviewed-by: Dmitry Baryshkov --- v2: * No change. drivers/gpu/drm/bridge/fsl-ldb.c | 31 +++++++++++-------------------- 1 file changed, 11 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-= ldb.c index 0e4bac7dd04f..b559f3e0bef6 100644 --- a/drivers/gpu/drm/bridge/fsl-ldb.c +++ b/drivers/gpu/drm/bridge/fsl-ldb.c @@ -15,7 +15,6 @@ #include #include #include -#include =20 #define LDB_CTRL_CH0_ENABLE BIT(0) #define LDB_CTRL_CH0_DI_SELECT BIT(1) @@ -86,7 +85,7 @@ static const struct fsl_ldb_devdata fsl_ldb_devdata[] =3D= { struct fsl_ldb { struct device *dev; struct drm_bridge bridge; - struct drm_bridge *panel_bridge; + struct drm_bridge *next_bridge; struct clk *clk; struct regmap *regmap; const struct fsl_ldb_devdata *devdata; @@ -117,7 +116,7 @@ static int fsl_ldb_attach(struct drm_bridge *bridge, { struct fsl_ldb *fsl_ldb =3D to_fsl_ldb(bridge); =20 - return drm_bridge_attach(bridge->encoder, fsl_ldb->panel_bridge, + return drm_bridge_attach(bridge->encoder, fsl_ldb->next_bridge, bridge, flags); } =20 @@ -292,9 +291,7 @@ static const struct drm_bridge_funcs funcs =3D { static int fsl_ldb_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; - struct device_node *panel_node; struct device_node *remote1, *remote2; - struct drm_panel *panel; struct fsl_ldb *fsl_ldb; int dual_link; =20 @@ -318,33 +315,27 @@ static int fsl_ldb_probe(struct platform_device *pdev) if (IS_ERR(fsl_ldb->regmap)) return PTR_ERR(fsl_ldb->regmap); =20 - /* Locate the remote ports and the panel node */ + /* Locate the remote ports. */ remote1 =3D of_graph_get_remote_node(dev->of_node, 1, 0); remote2 =3D of_graph_get_remote_node(dev->of_node, 2, 0); fsl_ldb->ch0_enabled =3D (remote1 !=3D NULL); fsl_ldb->ch1_enabled =3D (remote2 !=3D NULL); - panel_node =3D of_node_get(remote1 ? remote1 : remote2); of_node_put(remote1); of_node_put(remote2); =20 - if (!fsl_ldb->ch0_enabled && !fsl_ldb->ch1_enabled) { - of_node_put(panel_node); - return dev_err_probe(dev, -ENXIO, "No panel node found"); - } + if (!fsl_ldb->ch0_enabled && !fsl_ldb->ch1_enabled) + return dev_err_probe(dev, -ENXIO, "No next bridge node found"); =20 dev_dbg(dev, "Using %s\n", fsl_ldb_is_dual(fsl_ldb) ? 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Received: from AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) by DB8PR04MB6986.eurprd04.prod.outlook.com (2603:10a6:10:116::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.22; Sat, 12 Oct 2024 07:37:19 +0000 Received: from AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::d1ce:ea15:6648:6f90]) by AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::d1ce:ea15:6648:6f90%4]) with mapi id 15.20.8048.020; Sat, 12 Oct 2024 07:37:19 +0000 From: Liu Ying To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, geert+renesas@glider.be, dmitry.baryshkov@linaro.org, arnd@arndb.de, nfraprado@collabora.com, o.rempel@pengutronix.de, y.moog@phytec.de, marex@denx.de, isaac.scott@ideasonboard.com, biju.das.jz@bp.renesas.com Subject: [PATCH v2 4/9] drm/bridge: fsl-ldb: Use clk_round_rate() to validate "ldb" clock rate Date: Sat, 12 Oct 2024 15:35:38 +0800 Message-Id: <20241012073543.1388069-5-victor.liu@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241012073543.1388069-1-victor.liu@nxp.com> References: <20241012073543.1388069-1-victor.liu@nxp.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SI2PR01CA0051.apcprd01.prod.exchangelabs.com (2603:1096:4:193::6) To AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM7PR04MB7046:EE_|DB8PR04MB6986:EE_ X-MS-Office365-Filtering-Correlation-Id: 1f13943c-2a24-4651-97b6-08dcea90b3d7 X-LD-Processed: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|366016|52116014|38350700014; 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charset="utf-8" Multiple display modes could be read from a display device's EDID. Use clk_round_rate() to validate the "ldb" clock rate for each mode in drm_bridge_funcs::mode_valid() to filter unsupported modes out. Also, since this driver doesn't directly reference pixel clock, use clk_round_rate() to validate the pixel clock rate against the "ldb" clock if the "ldb" clock and the pixel clock are sibling in clock tree. This is not done in display controller driver because drm_crtc_helper_funcs::mode_valid() may not decide to do the validation or not if multiple encoders are connected to the CRTC, e.g., i.MX93 LCDIF may connect with MIPI DSI controller, LDB and parallel display output simultaneously. Signed-off-by: Liu Ying --- v2: * Add more comments in fsl-ldb.c and commit message about pixel clock rate validation. (Maxime) drivers/gpu/drm/bridge/fsl-ldb.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-= ldb.c index b559f3e0bef6..77afc169f0d3 100644 --- a/drivers/gpu/drm/bridge/fsl-ldb.c +++ b/drivers/gpu/drm/bridge/fsl-ldb.c @@ -11,6 +11,7 @@ #include #include #include +#include =20 #include #include @@ -64,6 +65,7 @@ struct fsl_ldb_devdata { u32 lvds_ctrl; bool lvds_en_bit; bool single_ctrl_reg; + bool ldb_clk_pixel_clk_sibling; }; =20 static const struct fsl_ldb_devdata fsl_ldb_devdata[] =3D { @@ -74,11 +76,13 @@ static const struct fsl_ldb_devdata fsl_ldb_devdata[] = =3D { [IMX8MP_LDB] =3D { .ldb_ctrl =3D 0x5c, .lvds_ctrl =3D 0x128, + .ldb_clk_pixel_clk_sibling =3D true, }, [IMX93_LDB] =3D { .ldb_ctrl =3D 0x20, .lvds_ctrl =3D 0x24, .lvds_en_bit =3D true, + .ldb_clk_pixel_clk_sibling =3D true, }, }; =20 @@ -269,11 +273,31 @@ fsl_ldb_mode_valid(struct drm_bridge *bridge, const struct drm_display_info *info, const struct drm_display_mode *mode) { + unsigned long link_freq, pclk_rate, rounded_pclk_rate; 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charset="utf-8" Document ITE IT6263 LVDS to HDMI converter. Product link: https://www.ite.com.tw/en/product/cate1/IT6263 Signed-off-by: Liu Ying --- v2: * Document number of LVDS link data lanes. (Biju) * Simplify ports property by dropping "oneOf". (Rob) .../bindings/display/bridge/ite,it6263.yaml | 276 ++++++++++++++++++ 1 file changed, 276 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/ite,it= 6263.yaml diff --git a/Documentation/devicetree/bindings/display/bridge/ite,it6263.ya= ml b/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml new file mode 100644 index 000000000000..bc2bbec07623 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml @@ -0,0 +1,276 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/ite,it6263.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ITE IT6263 LVDS to HDMI converter + +maintainers: + - Liu Ying + +description: | + The IT6263 is a high-performance single-chip De-SSC(De-Spread Spectrum) = LVDS + to HDMI converter. Combined with LVDS receiver and HDMI 1.4a transmitte= r, + the IT6263 supports LVDS input and HDMI 1.4 output by conversion functio= n. + The built-in LVDS receiver can support single-link and dual-link LVDS in= puts, + and the built-in HDMI transmitter is fully compliant with HDMI 1.4a/3D, = HDCP + 1.2 and backward compatible with DVI 1.0 specification. + + The IT6263 also encodes and transmits up to 8 channels of I2S digital au= dio, + with sampling rate up to 192KHz and sample size up to 24 bits. In additi= on, + an S/PDIF input port takes in compressed audio of up to 192KHz frame rat= e. + + The newly supported High-Bit Rate(HBR) audio by HDMI specifications v1.3= is + provided by the IT6263 in two interfaces: the four I2S input ports or the + S/PDIF input port. With both interfaces the highest possible HBR frame = rate + is supported at up to 768KHz. + +properties: + compatible: + const: ite,it6263 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + description: audio master clock + + clock-names: + const: mclk + + reset-gpios: + maxItems: 1 + + ivdd-supply: + description: 1.8V digital logic power + + ovdd-supply: + description: 3.3V I/O pin power + + txavcc18-supply: + description: 1.8V HDMI analog frontend power + + txavcc33-supply: + description: 3.3V HDMI analog frontend power + + pvcc1-supply: + description: 1.8V HDMI frontend core PLL power + + pvcc2-supply: + description: 1.8V HDMI frontend filter PLL power + + avcc-supply: + description: 3.3V LVDS frontend power + + anvdd-supply: + description: 1.8V LVDS frontend analog power + + apvdd-supply: + description: 1.8V LVDS frontend PLL power + + "#sound-dai-cells": + const: 0 + + ite,lvds-link-num-data-lanes: + $ref: /schemas/types.yaml#/definitions/uint8 + enum: [3, 4, 5] + description: number of data lanes per LVDS link + + ite,i2s-audio-fifo-sources: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 4 + items: + enum: [0, 1, 2, 3] + description: + Each array element indicates the pin number of an I2S serial data in= put + line which is connected to an audio FIFO, from audio FIFO0 to FIFO3. + + ite,rl-channel-swap-audio-sources: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 4 + uniqueItems: true + items: + enum: [0, 1, 2, 3] + description: + Each array element indicates an audio source whose right channel and= left + channel are swapped by this converter. For I2S, the element is the p= in + number of an I2S serial data input line. For S/PDIF, the element is = always + 0. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + The first LVDS input link. + In dual-link LVDS mode, this link works together with the second= LVDS + input link, and one link receives odd pixels while the other rec= eives + even pixels. Specify the pixels with one of the dual-lvds-odd-pi= xels + and dual-lvds-even-pixels properties when and only when dual-lin= k LVDS + mode is used. + + properties: + dual-lvds-odd-pixels: + type: boolean + description: the first sink port for odd pixels + + dual-lvds-even-pixels: + type: boolean + description: the first sink port for even pixels + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: the second LVDS input link + + properties: + dual-lvds-even-pixels: + type: boolean + description: the second sink port for even pixels + + dual-lvds-odd-pixels: + type: boolean + description: the second sink port for odd pixels + + oneOf: + - required: [dual-lvds-even-pixels] + - required: [dual-lvds-odd-pixels] + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: video port for the HDMI output + + port@3: + $ref: /schemas/graph.yaml#/properties/port + description: sound input port + + required: + - port@0 + - port@2 + +required: + - compatible + - reg + - ivdd-supply + - ovdd-supply + - txavcc18-supply + - txavcc33-supply + - pvcc1-supply + - pvcc2-supply + - avcc-supply + - anvdd-supply + - apvdd-supply + - ite,lvds-link-num-data-lanes + - ports + +additionalProperties: false + +examples: + - | + /* single-link LVDS input */ + #include + + i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + + hdmi@4c { + compatible =3D "ite,it6263"; + reg =3D <0x4c>; + reset-gpios =3D <&gpio1 10 GPIO_ACTIVE_LOW>; + ivdd-supply =3D <®_buck5>; + ovdd-supply =3D <®_vext_3v3>; + txavcc18-supply =3D <®_buck5>; + txavcc33-supply =3D <®_vext_3v3>; + pvcc1-supply =3D <®_buck5>; + pvcc2-supply =3D <®_buck5>; + avcc-supply =3D <®_vext_3v3>; + anvdd-supply =3D <®_buck5>; + apvdd-supply =3D <®_buck5>; + ite,lvds-link-num-data-lanes =3D /bits/ 8 <4>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + it6263_lvds_link1: endpoint { + remote-endpoint =3D <&ldb_lvds_ch0>; + }; + }; + + port@2 { + reg =3D <2>; + + it6263_out: endpoint { + remote-endpoint =3D <&hdmi_in>; + }; + }; + }; + }; + }; + + - | + /* dual-link LVDS input */ + #include + + i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + + hdmi@4c { + compatible =3D "ite,it6263"; + reg =3D <0x4c>; + reset-gpios =3D <&gpio1 10 GPIO_ACTIVE_LOW>; + ivdd-supply =3D <®_buck5>; + ovdd-supply =3D <®_vext_3v3>; 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Received: from AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) by DB8PR04MB6986.eurprd04.prod.outlook.com (2603:10a6:10:116::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.22; Sat, 12 Oct 2024 07:37:38 +0000 Received: from AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::d1ce:ea15:6648:6f90]) by AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::d1ce:ea15:6648:6f90%4]) with mapi id 15.20.8048.020; Sat, 12 Oct 2024 07:37:38 +0000 From: Liu Ying To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, geert+renesas@glider.be, dmitry.baryshkov@linaro.org, arnd@arndb.de, nfraprado@collabora.com, o.rempel@pengutronix.de, y.moog@phytec.de, marex@denx.de, isaac.scott@ideasonboard.com, biju.das.jz@bp.renesas.com Subject: [PATCH v2 6/9] drm/bridge: Add ITE IT6263 LVDS to HDMI converter Date: Sat, 12 Oct 2024 15:35:40 +0800 Message-Id: <20241012073543.1388069-7-victor.liu@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241012073543.1388069-1-victor.liu@nxp.com> References: <20241012073543.1388069-1-victor.liu@nxp.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SI2PR01CA0051.apcprd01.prod.exchangelabs.com (2603:1096:4:193::6) To AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM7PR04MB7046:EE_|DB8PR04MB6986:EE_ X-MS-Office365-Filtering-Correlation-Id: bd2ee53a-de67-45d3-b7ad-08dcea90beeb X-LD-Processed: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|366016|52116014|38350700014; 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charset="utf-8" Add basic HDMI video output support. Currently, only RGB888 output pixel format is supported. At the LVDS input side, the driver supports single LVDS link and dual LVDS links with "jeida-24" LVDS mapping. Product link: https://www.ite.com.tw/en/product/cate1/IT6263 Signed-off-by: Liu Ying --- v2: * Add AVI inforframe support. (Maxime) * Add DRM_MODE_CONNECTOR_HDMIA. (Biju) * Rename it6263_reset() to it6263_hw_reset(). (Biju) * Check number of LVDS link data lanes. (Biju) drivers/gpu/drm/bridge/Kconfig | 8 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/ite-it6263.c | 919 ++++++++++++++++++++++++++++ 3 files changed, 928 insertions(+) create mode 100644 drivers/gpu/drm/bridge/ite-it6263.c diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 3eb955333c80..93f99682a090 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -90,6 +90,14 @@ config DRM_FSL_LDB help Support for i.MX8MP DPI-to-LVDS on-SoC encoder. =20 +config DRM_ITE_IT6263 + tristate "ITE IT6263 LVDS/HDMI bridge" + depends on OF + select DRM_KMS_HELPER + select REGMAP_I2C + help + ITE IT6263 LVDS to HDMI bridge chip driver. + config DRM_ITE_IT6505 tristate "ITE IT6505 DisplayPort bridge" depends on OF diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makef= ile index 7df87b582dca..f3776dd473fd 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_DRM_CHRONTEL_CH7033) +=3D chrontel-ch7033.o obj-$(CONFIG_DRM_CROS_EC_ANX7688) +=3D cros-ec-anx7688.o obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) +=3D display-connector.o obj-$(CONFIG_DRM_FSL_LDB) +=3D fsl-ldb.o +obj-$(CONFIG_DRM_ITE_IT6263) +=3D ite-it6263.o obj-$(CONFIG_DRM_ITE_IT6505) +=3D ite-it6505.o obj-$(CONFIG_DRM_LONTIUM_LT8912B) +=3D lontium-lt8912b.o obj-$(CONFIG_DRM_LONTIUM_LT9211) +=3D lontium-lt9211.o diff --git a/drivers/gpu/drm/bridge/ite-it6263.c b/drivers/gpu/drm/bridge/i= te-it6263.c new file mode 100644 index 000000000000..9b3318792f15 --- /dev/null +++ b/drivers/gpu/drm/bridge/ite-it6263.c @@ -0,0 +1,919 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2024 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* -----------------------------------------------------------------------= ------ + * LVDS registers + */ + +/* LVDS software reset registers */ +#define LVDS_REG_05 0x05 +#define REG_SOFT_P_RST BIT(1) + +/* LVDS system configuration registers */ +/* 0x0b */ +#define LVDS_REG_0B 0x0b +#define REG_SSC_PCLK_RF BIT(0) +#define REG_LVDS_IN_SWAP BIT(1) + +/* LVDS test pattern gen control registers */ +/* 0x2c */ +#define LVDS_REG_2C 0x2c +#define REG_COL_DEP GENMASK(1, 0) +#define BIT8 FIELD_PREP(REG_COL_DEP, 2) +#define OUT_MAP BIT(4) +#define JEIDA 0 +#define REG_DESSC_ENB BIT(6) +#define DMODE BIT(7) +#define DISO BIT(7) +#define SISO 0 + +#define LVDS_REG_3C 0x3c +#define LVDS_REG_3F 0x3f +#define LVDS_REG_47 0x47 +#define LVDS_REG_48 0x48 +#define LVDS_REG_4F 0x4f +#define LVDS_REG_52 0x52 + +/* -----------------------------------------------------------------------= ------ + * HDMI registers are separated into three banks: + * 1) HDMI register common bank: 0x00 ~ 0x2f + */ + +/* HDMI genernal registers */ +#define HDMI_REG_SW_RST 0x04 +#define SOFTREF_RST BIT(5) +#define SOFTA_RST BIT(4) +#define SOFTV_RST BIT(3) +#define AUD_RST BIT(2) +#define HDCP_RST BIT(0) +#define HDMI_RST_ALL (SOFTREF_RST | SOFTA_RST | SOFTV_RST | \ + AUD_RST | HDCP_RST) + +#define HDMI_REG_SYS_STATUS 0x0e +#define HPDETECT BIT(6) +#define TXVIDSTABLE BIT(4) + +#define HDMI_REG_BANK_CTRL 0x0f +#define REG_BANK_SEL BIT(0) + +/* HDMI System DDC control registers */ +#define HDMI_REG_DDC_MASTER_CTRL 0x10 +#define MASTER_SEL_HOST BIT(0) + +#define HDMI_REG_DDC_HEADER 0x11 + +#define HDMI_REG_DDC_REQOFF 0x12 +#define HDMI_REG_DDC_REQCOUNT 0x13 +#define HDMI_REG_DDC_EDIDSEG 0x14 + +#define HDMI_REG_DDC_CMD 0x15 +#define DDC_CMD_EDID_READ 0x3 +#define DDC_CMD_FIFO_CLR 0x9 + +#define HDMI_REG_DDC_STATUS 0x16 +#define DDC_DONE BIT(7) +#define DDC_NOACK BIT(5) +#define DDC_WAITBUS BIT(4) +#define DDC_ARBILOSE BIT(3) +#define DDC_ERROR (DDC_NOACK | DDC_WAITBUS | DDC_ARBILOSE) + +#define HDMI_DDC_FIFO_BYTES 32 +#define HDMI_REG_DDC_READFIFO 0x17 +#define HDMI_REG_LVDS_PORT 0x1d /* LVDS input control I2C addr */ +#define HDMI_REG_LVDS_PORT_EN 0x1e +#define LVDS_INPUT_CTRL_I2C_ADDR 0x33 + +/* -----------------------------------------------------------------------= ------ + * 2) HDMI register bank0: 0x30 ~ 0xff + */ + +/* HDMI AFE registers */ +#define HDMI_REG_AFE_DRV_CTRL 0x61 +#define AFE_DRV_PWD BIT(5) +#define AFE_DRV_RST BIT(4) + +#define HDMI_REG_AFE_XP_CTRL 0x62 +#define AFE_XP_GAINBIT BIT(7) +#define AFE_XP_ER0 BIT(4) +#define AFE_XP_RESETB BIT(3) + +#define HDMI_REG_AFE_ISW_CTRL 0x63 + +#define HDMI_REG_AFE_IP_CTRL 0x64 +#define AFE_IP_GAINBIT BIT(7) +#define AFE_IP_ER0 BIT(3) +#define AFE_IP_RESETB BIT(2) + +/* HDMI input data format registers */ +#define HDMI_REG_INPUT_MODE 0x70 +#define IN_RGB 0x00 + +/* HDMI general control registers */ +#define HDMI_REG_HDMI_MODE 0xc0 +#define TX_HDMI_MODE BIT(0) + +#define HDMI_REG_GCP 0xc1 +#define AVMUTE BIT(0) +#define HDMI_COLOR_DEPTH GENMASK(6, 4) +#define HDMI_COLOR_DEPTH_24 FIELD_PREP(HDMI_COLOR_DEPTH, 4) + +#define HDMI_REG_PKT_GENERAL_CTRL 0xc6 +#define ENABLE_PKT BIT(0) +#define REPEAT_PKT BIT(1) + +/* -----------------------------------------------------------------------= ------ + * 3) HDMI register bank1: 0x130 ~ 0x1ff (HDMI packet registers) + */ + +/* AVI packet registers */ +#define HDMI_REG_AVI_DB1 0x158 +#define HDMI_REG_AVI_DB2 0x159 +#define HDMI_REG_AVI_DB3 0x15a +#define HDMI_REG_AVI_DB4 0x15b +#define HDMI_REG_AVI_DB5 0x15c +#define HDMI_REG_AVI_CSUM 0x15d +#define HDMI_REG_AVI_DB6 0x15e +#define HDMI_REG_AVI_DB7 0x15f +#define HDMI_REG_AVI_DB8 0x160 +#define HDMI_REG_AVI_DB9 0x161 +#define HDMI_REG_AVI_DB10 0x162 +#define HDMI_REG_AVI_DB11 0x163 +#define HDMI_REG_AVI_DB12 0x164 +#define HDMI_REG_AVI_DB13 0x165 + +#define HDMI_AVI_DB_CHUNK1_SIZE (HDMI_REG_AVI_DB5 - HDMI_REG_AVI_DB1 + 1) +#define HDMI_AVI_DB_CHUNK2_SIZE (HDMI_REG_AVI_DB13 - HDMI_REG_AVI_DB6 + 1) + +#define MAX_PIXEL_CLOCK_KHZ 150000 +#define HIGH_PIXEL_CLOCK_KHZ 80000 + +struct it6263 { + struct device *dev; + struct i2c_client *hdmi_i2c; + struct i2c_client *lvds_i2c; + struct regmap *hdmi_regmap; + struct regmap *lvds_regmap; + struct drm_bridge bridge; + struct drm_bridge *next_bridge; + struct drm_connector connector; + struct gpio_desc *reset_gpio; + u8 lvds_link_num_dlanes; + bool lvds_dual_link; + bool lvds_link12_swap; +}; + +static inline struct it6263 *bridge_to_it6263(struct drm_bridge *bridge) +{ + return container_of(bridge, struct it6263, bridge); +} + +static inline struct it6263 *connector_to_it6263(struct drm_connector *con= n) +{ + return container_of(conn, struct it6263, connector); +} + +static bool it6263_hdmi_writeable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case HDMI_REG_SW_RST: + case HDMI_REG_BANK_CTRL: + case HDMI_REG_DDC_MASTER_CTRL: + case HDMI_REG_DDC_HEADER: + case HDMI_REG_DDC_REQOFF: + case HDMI_REG_DDC_REQCOUNT: + case HDMI_REG_DDC_EDIDSEG: + case HDMI_REG_DDC_CMD: + case HDMI_REG_LVDS_PORT: + case HDMI_REG_LVDS_PORT_EN: + case HDMI_REG_AFE_DRV_CTRL: + case HDMI_REG_AFE_XP_CTRL: + case HDMI_REG_AFE_ISW_CTRL: + case HDMI_REG_AFE_IP_CTRL: + case HDMI_REG_INPUT_MODE: + case HDMI_REG_HDMI_MODE: + case HDMI_REG_GCP: + case HDMI_REG_PKT_GENERAL_CTRL: + case HDMI_REG_AVI_DB1: + case HDMI_REG_AVI_DB2: + case HDMI_REG_AVI_DB3: + case HDMI_REG_AVI_DB4: + case HDMI_REG_AVI_DB5: + case HDMI_REG_AVI_CSUM: + case HDMI_REG_AVI_DB6: + case HDMI_REG_AVI_DB7: + case HDMI_REG_AVI_DB8: + case HDMI_REG_AVI_DB9: + case HDMI_REG_AVI_DB10: + case HDMI_REG_AVI_DB11: + case HDMI_REG_AVI_DB12: + case HDMI_REG_AVI_DB13: + return true; + default: + return false; + } +} + +static bool it6263_hdmi_readable_reg(struct device *dev, unsigned int reg) +{ + if (it6263_hdmi_writeable_reg(dev, reg)) + return true; + + switch (reg) { + case HDMI_REG_SYS_STATUS: + case HDMI_REG_DDC_STATUS: + case HDMI_REG_DDC_READFIFO: + return true; + default: + return false; + } +} + +static bool it6263_hdmi_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case HDMI_REG_SW_RST: + case HDMI_REG_SYS_STATUS: + case HDMI_REG_DDC_STATUS: + case HDMI_REG_DDC_READFIFO: + return true; + default: + return false; + } +} + +static const struct regmap_range_cfg it6263_hdmi_range_cfg =3D { + .range_min =3D 0x00, + .range_max =3D HDMI_REG_AVI_DB13, + .selector_reg =3D HDMI_REG_BANK_CTRL, + .selector_mask =3D REG_BANK_SEL, + .selector_shift =3D 0, + .window_start =3D 0x00, + .window_len =3D 0x100, +}; + +static const struct regmap_config it6263_hdmi_regmap_config =3D { + .name =3D "it6263-hdmi", + .reg_bits =3D 8, + .val_bits =3D 8, + .writeable_reg =3D it6263_hdmi_writeable_reg, + .readable_reg =3D it6263_hdmi_readable_reg, + .volatile_reg =3D it6263_hdmi_volatile_reg, + .max_register =3D HDMI_REG_AVI_DB13, + .ranges =3D &it6263_hdmi_range_cfg, + .num_ranges =3D 1, + .cache_type =3D REGCACHE_MAPLE, +}; + +static bool it6263_lvds_writeable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case LVDS_REG_05: + case LVDS_REG_0B: + case LVDS_REG_2C: + case LVDS_REG_3C: + case LVDS_REG_3F: + case LVDS_REG_47: + case LVDS_REG_48: + case LVDS_REG_4F: + case LVDS_REG_52: + return true; + default: + return false; + } +} + +static bool it6263_lvds_readable_reg(struct device *dev, unsigned int reg) +{ + return it6263_lvds_writeable_reg(dev, reg); +} + +static bool it6263_lvds_volatile_reg(struct device *dev, unsigned int reg) +{ + return reg =3D=3D LVDS_REG_05; +} + +static const struct regmap_config it6263_lvds_regmap_config =3D { + .name =3D "it6263-lvds", + .reg_bits =3D 8, + .val_bits =3D 8, + .writeable_reg =3D it6263_lvds_writeable_reg, + .readable_reg =3D it6263_lvds_readable_reg, + .volatile_reg =3D it6263_lvds_volatile_reg, + .max_register =3D LVDS_REG_52, + .cache_type =3D REGCACHE_MAPLE, +}; + +static const char * const it6263_supplies[] =3D { + "ivdd", "ovdd", "txavcc18", "txavcc33", "pvcc1", "pvcc2", + "avcc", "anvdd", "apvdd" +}; + +static int it6263_parse_dt(struct it6263 *it) +{ + struct device *dev =3D it->dev; + struct device_node *port0, *port1; + int ret; + + ret =3D of_property_read_u8(dev->of_node, "ite,lvds-link-num-data-lanes", + &it->lvds_link_num_dlanes); + if (ret) { + dev_err(dev, "failed to get LVDS link number of data lanes: %d\n", + ret); + return ret; + } + + it->next_bridge =3D devm_drm_of_get_bridge(dev, dev->of_node, 2, 0); + if (IS_ERR(it->next_bridge)) + return dev_err_probe(dev, PTR_ERR(it->next_bridge), + "failed to get next bridge\n"); + + port0 =3D of_graph_get_port_by_id(dev->of_node, 0); + port1 =3D of_graph_get_port_by_id(dev->of_node, 1); + if (port0 && port1) { + if (of_property_read_bool(port0, "dual-lvds-even-pixels") && + of_property_read_bool(port1, "dual-lvds-odd-pixels")) { + it->lvds_dual_link =3D true; + it->lvds_link12_swap =3D true; + } else if (of_property_read_bool(port0, "dual-lvds-odd-pixels") && + of_property_read_bool(port1, "dual-lvds-even-pixels")) { + it->lvds_dual_link =3D true; + } + + if (!it->lvds_dual_link) { + dev_err(dev, + "failed to get LVDS dual link pixel order\n"); + ret =3D -EINVAL; + } + } else if (port1) { + ret =3D -EINVAL; + dev_err(dev, "single input LVDS port1 is not supported\n"); + } else if (!port0) { + ret =3D -EINVAL; + dev_err(dev, "no input LVDS port\n"); + } + + of_node_put(port0); + of_node_put(port1); + + return ret; +} + +static inline void it6263_hw_reset(struct it6263 *it) +{ + if (!it->reset_gpio) + return; + + gpiod_set_value_cansleep(it->reset_gpio, 0); + fsleep(1000); + gpiod_set_value_cansleep(it->reset_gpio, 1); + /* The chip maker says the low pulse should be at least 40ms. */ + fsleep(40000); + gpiod_set_value_cansleep(it->reset_gpio, 0); + /* addtional time to wait the high voltage to be stable */ + fsleep(5000); +} + +static inline int it6263_lvds_set_i2c_addr(struct it6263 *it) +{ + int ret; + + ret =3D regmap_write(it->hdmi_regmap, HDMI_REG_LVDS_PORT, + LVDS_INPUT_CTRL_I2C_ADDR << 1); + if (ret) + return ret; + + return regmap_write(it->hdmi_regmap, HDMI_REG_LVDS_PORT_EN, BIT(0)); +} + +static inline void it6263_lvds_reset(struct it6263 *it) +{ + /* AFE PLL reset */ + regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, BIT(0), 0x0); + fsleep(1000); + regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, BIT(0), BIT(0)); + + /* software pixel clock domain reset */ + regmap_write_bits(it->lvds_regmap, LVDS_REG_05, REG_SOFT_P_RST, + REG_SOFT_P_RST); + fsleep(1000); + regmap_write_bits(it->lvds_regmap, LVDS_REG_05, REG_SOFT_P_RST, 0x0); + fsleep(10000); +} + +static inline void it6263_lvds_set_interface(struct it6263 *it) +{ + /* color depth */ + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, REG_COL_DEP, BIT8); + /* output mapping */ + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, OUT_MAP, JEIDA); + + if (it->lvds_dual_link) { + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, DMODE, DISO); + regmap_write_bits(it->lvds_regmap, LVDS_REG_52, BIT(1), BIT(1)); + } else { + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, DMODE, SISO); + regmap_write_bits(it->lvds_regmap, LVDS_REG_52, BIT(1), 0); + } +} + +static inline void it6263_lvds_set_afe(struct it6263 *it) +{ + regmap_write(it->lvds_regmap, LVDS_REG_3C, 0xaa); + regmap_write(it->lvds_regmap, LVDS_REG_3F, 0x02); + regmap_write(it->lvds_regmap, LVDS_REG_47, 0xaa); + regmap_write(it->lvds_regmap, LVDS_REG_48, 0x02); + regmap_write(it->lvds_regmap, LVDS_REG_4F, 0x11); + + regmap_write_bits(it->lvds_regmap, LVDS_REG_0B, REG_SSC_PCLK_RF, + REG_SSC_PCLK_RF); + regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, 0x07, 0); + regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, REG_DESSC_ENB, + REG_DESSC_ENB); +} + +static inline void it6263_lvds_sys_cfg(struct it6263 *it) +{ + regmap_write_bits(it->lvds_regmap, LVDS_REG_0B, REG_LVDS_IN_SWAP, + it->lvds_link12_swap ? REG_LVDS_IN_SWAP : 0); +} + +static inline void it6263_lvds_config(struct it6263 *it) +{ + it6263_lvds_reset(it); + it6263_lvds_set_interface(it); + it6263_lvds_set_afe(it); + it6263_lvds_sys_cfg(it); +} + +static inline void it6263_hdmi_config(struct it6263 *it) +{ + regmap_write(it->hdmi_regmap, HDMI_REG_SW_RST, HDMI_RST_ALL); + regmap_write(it->hdmi_regmap, HDMI_REG_INPUT_MODE, IN_RGB); + regmap_write_bits(it->hdmi_regmap, HDMI_REG_GCP, HDMI_COLOR_DEPTH, + HDMI_COLOR_DEPTH_24); +} + +static enum drm_connector_status it6263_detect(struct it6263 *it) +{ + unsigned int val; + + regmap_read(it->hdmi_regmap, HDMI_REG_SYS_STATUS, &val); + if (val & HPDETECT) + return connector_status_connected; + else + return connector_status_disconnected; +} + +static enum drm_connector_status +it6263_connector_detect(struct drm_connector *connector, bool force) +{ + struct it6263 *it =3D connector_to_it6263(connector); + + return it6263_detect(it); +} + +static const struct drm_connector_funcs it6263_connector_funcs =3D { + .detect =3D it6263_connector_detect, + .fill_modes =3D drm_helper_probe_single_connector_modes, + .destroy =3D drm_connector_cleanup, + .reset =3D drm_atomic_helper_connector_reset, + .atomic_duplicate_state =3D drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state =3D drm_atomic_helper_connector_destroy_state, +}; + +static int it6263_read_edid(void *data, u8 *buf, unsigned int block, size_= t len) +{ + struct it6263 *it =3D data; + struct regmap *regmap =3D it->hdmi_regmap; + unsigned int start =3D (block % 2) * EDID_LENGTH; + unsigned int segment =3D block >> 1; + unsigned int count, val; + int ret; + + regmap_write(regmap, HDMI_REG_DDC_MASTER_CTRL, MASTER_SEL_HOST); + regmap_write(regmap, HDMI_REG_DDC_HEADER, DDC_ADDR << 1); + regmap_write(regmap, HDMI_REG_DDC_EDIDSEG, segment); + + while (len) { + /* clear DDC FIFO */ + regmap_write(regmap, HDMI_REG_DDC_CMD, DDC_CMD_FIFO_CLR); + + ret =3D regmap_read_poll_timeout(regmap, HDMI_REG_DDC_STATUS, + val, val & DDC_DONE, + 2000, 10000); + if (ret) { + dev_err(it->dev, "failed to clear DDC FIFO:%d\n", ret); + return ret; + } + + count =3D len > HDMI_DDC_FIFO_BYTES ? HDMI_DDC_FIFO_BYTES : len; + + /* fire the read command */ + regmap_write(regmap, HDMI_REG_DDC_REQOFF, start); + regmap_write(regmap, HDMI_REG_DDC_REQCOUNT, count); + regmap_write(regmap, HDMI_REG_DDC_CMD, DDC_CMD_EDID_READ); + + start +=3D count; + len -=3D count; + + ret =3D regmap_read_poll_timeout(regmap, HDMI_REG_DDC_STATUS, val, + val & (DDC_DONE | DDC_ERROR), + 20000, 250000); + if (ret && !(val & DDC_ERROR)) { + dev_err(it->dev, "failed to read EDID:%d\n", ret); + return ret; + } + + if (val & DDC_ERROR) { + dev_err(it->dev, "DDC error\n"); + return -EIO; + } + + /* cache to buffer */ + for (; count > 0; count--) { + regmap_read(regmap, HDMI_REG_DDC_READFIFO, &val); + *(buf++) =3D val; + } + } + + return 0; +} + +static int it6263_connector_get_modes(struct drm_connector *connector) +{ + struct it6263 *it =3D connector_to_it6263(connector); + const struct drm_edid *drm_edid; + int count; + + drm_edid =3D drm_edid_read_custom(connector, it6263_read_edid, it); + + drm_edid_connector_update(connector, drm_edid); + count =3D drm_edid_connector_add_modes(connector); + + drm_edid_free(drm_edid); + + return count; +} + +static const struct drm_connector_helper_funcs it6263_connector_helper_fun= cs =3D { + .get_modes =3D it6263_connector_get_modes, +}; + +static int it6263_bridge_atomic_check(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct drm_display_mode *mode =3D &crtc_state->adjusted_mode; + + return mode->clock > MAX_PIXEL_CLOCK_KHZ ? -EINVAL : 0; +} + +static void +it6263_bridge_atomic_disable(struct drm_bridge *bridge, + struct drm_bridge_state *old_bridge_state) +{ + struct it6263 *it =3D bridge_to_it6263(bridge); + + regmap_write_bits(it->hdmi_regmap, HDMI_REG_GCP, AVMUTE, AVMUTE); + regmap_write(it->hdmi_regmap, HDMI_REG_PKT_GENERAL_CTRL, 0); + regmap_write(it->hdmi_regmap, HDMI_REG_AFE_DRV_CTRL, + AFE_DRV_RST | AFE_DRV_PWD); +} + +static void +it6263_hdmi_avi_infoframe_configure(struct it6263 *it, + struct drm_connector *connector, + const struct drm_display_mode *mode) +{ + struct hdmi_avi_infoframe frame; + u8 buf[HDMI_INFOFRAME_SIZE(AVI)]; + int ret; + + ret =3D drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); + if (ret) { + dev_err(it->dev, "failed to setup AVI infoframe: %d\n", ret); + return; + } + + ret =3D hdmi_avi_infoframe_pack(&frame, buf, sizeof(buf)); + if (ret < 0) { + dev_err(it->dev, "failed to pack infoframe: %d\n", ret); + return; + } + + /* write the first AVI infoframe data byte chunk(DB1-DB5) */ + ret =3D regmap_bulk_write(it->hdmi_regmap, HDMI_REG_AVI_DB1, + &buf[HDMI_INFOFRAME_HEADER_SIZE], + HDMI_AVI_DB_CHUNK1_SIZE); + if (ret) { + dev_err(it->dev, "failed to write the 1st AVI infoframe data byte chunk:= %d\n", + ret); + return; + } + + /* write the second AVI infoframe data byte chunk(DB6-DB13) */ + ret =3D regmap_bulk_write(it->hdmi_regmap, HDMI_REG_AVI_DB6, + &buf[HDMI_INFOFRAME_HEADER_SIZE + + HDMI_AVI_DB_CHUNK1_SIZE], + HDMI_AVI_DB_CHUNK2_SIZE); + if (ret) { + dev_err(it->dev, "failed to write the 2nd AVI infoframe data byte chunk:= %d\n", + ret); + return; + } + + ret =3D regmap_write(it->hdmi_regmap, HDMI_REG_AVI_CSUM, buf[3]); + if (ret) + dev_err(it->dev, "failed to set AVI infoframe checksum: %d\n", + ret); +} + +static void +it6263_bridge_atomic_enable(struct drm_bridge *bridge, + struct drm_bridge_state *old_bridge_state) +{ + struct drm_atomic_state *state =3D old_bridge_state->base.state; + struct it6263 *it =3D bridge_to_it6263(bridge); + const struct drm_crtc_state *crtc_state; + struct regmap *regmap =3D it->hdmi_regmap; + const struct drm_display_mode *mode; + struct drm_connector *connector; + bool is_stable =3D false; + struct drm_crtc *crtc; + unsigned int val; + bool pclk_high; + int i, ret; + + connector =3D drm_atomic_get_new_connector_for_encoder(state, + bridge->encoder); + crtc =3D drm_atomic_get_new_connector_state(state, connector)->crtc; + crtc_state =3D drm_atomic_get_new_crtc_state(state, crtc); + mode =3D &crtc_state->adjusted_mode; + + regmap_write(regmap, HDMI_REG_HDMI_MODE, TX_HDMI_MODE); + + it6263_hdmi_avi_infoframe_configure(it, connector, mode); + + /* HDMI AFE setup */ + pclk_high =3D mode->clock > HIGH_PIXEL_CLOCK_KHZ ? true : false; + regmap_write(regmap, HDMI_REG_AFE_DRV_CTRL, AFE_DRV_RST); + if (pclk_high) + regmap_write(regmap, HDMI_REG_AFE_XP_CTRL, + AFE_XP_GAINBIT | AFE_XP_RESETB); + else + regmap_write(regmap, HDMI_REG_AFE_XP_CTRL, + AFE_XP_ER0 | AFE_XP_RESETB); + regmap_write(regmap, HDMI_REG_AFE_ISW_CTRL, 0x10); + if (pclk_high) + regmap_write(regmap, HDMI_REG_AFE_IP_CTRL, + AFE_IP_GAINBIT | AFE_IP_RESETB); + else + regmap_write(regmap, HDMI_REG_AFE_IP_CTRL, + AFE_IP_ER0 | AFE_IP_RESETB); + + /* HDMI software video reset */ + regmap_write_bits(regmap, HDMI_REG_SW_RST, SOFTV_RST, SOFTV_RST); + fsleep(1000); + regmap_write_bits(regmap, HDMI_REG_SW_RST, SOFTV_RST, 0); + + /* reconfigure LVDS and retry several times in case video is instable */ + for (i =3D 0; i < 3; i++) { + ret =3D regmap_read_poll_timeout(regmap, HDMI_REG_SYS_STATUS, val, + val & TXVIDSTABLE, + 20000, 500000); + if (!ret) { + is_stable =3D true; + break; + } + + it6263_lvds_config(it); + } + + if (!is_stable) + dev_warn(it->dev, "failed to wait for video stable\n"); + + /* HDMI AFE reset release and power up */ + regmap_write(regmap, HDMI_REG_AFE_DRV_CTRL, 0); + + regmap_write_bits(regmap, HDMI_REG_GCP, AVMUTE, 0); + + regmap_write(regmap, HDMI_REG_PKT_GENERAL_CTRL, ENABLE_PKT | REPEAT_PKT); +} + +static enum drm_mode_status +it6263_bridge_mode_valid(struct drm_bridge *bridge, + const struct drm_display_info *info, + const struct drm_display_mode *mode) +{ + return mode->clock > MAX_PIXEL_CLOCK_KHZ ? MODE_CLOCK_HIGH : MODE_OK; +} + +static int it6263_bridge_attach(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + struct it6263 *it =3D bridge_to_it6263(bridge); + int ret; + + ret =3D drm_bridge_attach(bridge->encoder, it->next_bridge, bridge, + flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR); + if (ret < 0) + return ret; + + if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) + return 0; + + it->connector.polled =3D DRM_CONNECTOR_POLL_CONNECT | + DRM_CONNECTOR_POLL_DISCONNECT; + + ret =3D drm_connector_init(bridge->dev, &it->connector, + &it6263_connector_funcs, + DRM_MODE_CONNECTOR_HDMIA); + if (ret) + return ret; + + drm_connector_helper_add(&it->connector, + &it6263_connector_helper_funcs); + drm_connector_attach_encoder(&it->connector, bridge->encoder); + + return 0; +} + +static enum drm_connector_status it6263_bridge_detect(struct drm_bridge *b= ridge) +{ + struct it6263 *it =3D bridge_to_it6263(bridge); + + return it6263_detect(it); +} + +static const struct drm_edid * +it6263_bridge_edid_read(struct drm_bridge *bridge, + struct drm_connector *connector) +{ + struct it6263 *it =3D bridge_to_it6263(bridge); + + return drm_edid_read_custom(connector, it6263_read_edid, it); +} + +static u32 * +it6263_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + u32 output_fmt, + unsigned int *num_input_fmts) +{ + struct it6263 *it =3D bridge_to_it6263(bridge); + u32 *input_fmts; + + *num_input_fmts =3D 0; + + if (it->lvds_link_num_dlanes =3D=3D 3) + return NULL; + + input_fmts =3D kmalloc(sizeof(*input_fmts), GFP_KERNEL); + if (!input_fmts) + return NULL; + + input_fmts[0] =3D MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA; + *num_input_fmts =3D 1; + + return input_fmts; +} + +static const struct drm_bridge_funcs it6263_bridge_funcs =3D { + .atomic_duplicate_state =3D drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state =3D drm_atomic_helper_bridge_destroy_state, + .atomic_reset =3D drm_atomic_helper_bridge_reset, + .attach =3D it6263_bridge_attach, + .mode_valid =3D it6263_bridge_mode_valid, + .atomic_disable =3D it6263_bridge_atomic_disable, + .atomic_enable =3D it6263_bridge_atomic_enable, + .atomic_check =3D it6263_bridge_atomic_check, + .detect =3D it6263_bridge_detect, + .edid_read =3D it6263_bridge_edid_read, + .atomic_get_input_bus_fmts =3D it6263_bridge_atomic_get_input_bus_fmts, +}; + +static int it6263_probe(struct i2c_client *client) +{ + struct device *dev =3D &client->dev; + struct it6263 *it; + int ret; + + it =3D devm_kzalloc(dev, sizeof(*it), GFP_KERNEL); + if (!it) + return -ENOMEM; + + it->dev =3D dev; + it->hdmi_i2c =3D client; + + it->hdmi_regmap =3D devm_regmap_init_i2c(client, + &it6263_hdmi_regmap_config); + if (IS_ERR(it->hdmi_regmap)) + return dev_err_probe(dev, PTR_ERR(it->hdmi_regmap), + "failed to init I2C regmap for HDMI\n"); + + it->reset_gpio =3D devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(it->reset_gpio)) + return dev_err_probe(dev, PTR_ERR(it->reset_gpio), + "failed to get reset gpio\n"); + + ret =3D devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(it6263_supplies), + it6263_supplies); + if (ret) + return dev_err_probe(dev, ret, "failed to get power supplies\n"); + + ret =3D it6263_parse_dt(it); + if (ret) + return ret; + + it6263_hw_reset(it); + + ret =3D it6263_lvds_set_i2c_addr(it); + if (ret) + return dev_err_probe(dev, ret, "failed to set I2C addr\n"); + + it->lvds_i2c =3D devm_i2c_new_dummy_device(dev, client->adapter, + LVDS_INPUT_CTRL_I2C_ADDR); + if (IS_ERR(it->lvds_i2c)) + dev_err_probe(it->dev, PTR_ERR(it->lvds_i2c), + "failed to allocate I2C device for LVDS\n"); + + it->lvds_regmap =3D devm_regmap_init_i2c(it->lvds_i2c, + &it6263_lvds_regmap_config); + if (IS_ERR(it->lvds_regmap)) + return dev_err_probe(dev, PTR_ERR(it->lvds_regmap), + "failed to init I2C regmap for LVDS\n"); + + it6263_lvds_config(it); + it6263_hdmi_config(it); + + i2c_set_clientdata(client, it); + + it->bridge.funcs =3D &it6263_bridge_funcs; + it->bridge.of_node =3D dev->of_node; + it->bridge.ops =3D DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_DETECT; + it->bridge.type =3D DRM_MODE_CONNECTOR_HDMIA; + drm_bridge_add(&it->bridge); + + return 0; +} + +static void it6263_remove(struct i2c_client *client) +{ + struct it6263 *it =3D i2c_get_clientdata(client); + + drm_bridge_remove(&it->bridge); +} + +static const struct of_device_id it6263_of_match[] =3D { + { .compatible =3D "ite,it6263", }, + { } +}; +MODULE_DEVICE_TABLE(of, it6263_of_match); + +static const struct i2c_device_id it6263_i2c_ids[] =3D { + { "it6263", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, it6263_i2c_ids); + +static struct i2c_driver it6263_driver =3D { + .probe =3D it6263_probe, + .remove =3D it6263_remove, + .driver =3D { + .name =3D "it6263", + .of_match_table =3D it6263_of_match, + }, + .id_table =3D it6263_i2c_ids, +}; +module_i2c_driver(it6263_driver); + +MODULE_DESCRIPTION("ITE Tech. Inc. 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charset="utf-8" One ITE IT6263 LVDS to HDMI converter is populated on NXP IMX-LVDS-HDMI and IMX-DLVDS-HDMI adapter cards. Card IMX-LVDS-HDMI supports single LVDS link(IT6263 link1). Card IMX-DLVDS-HDMI supports dual LVDS links(IT6263 link1 and link2). Only one card can be enabled with one i.MX8MP EVK. Add dedicated overlays to support the below four connections: 1) imx8mp-evk-lvds0-imx-lvds-hdmi.dtso: i.MX8MP EVK LVDS0 connector <=3D> LVDS adapter card J6(IT6263 link1) 2) imx8mp-evk-lvds1-imx-lvds-hdmi.dtso: i.MX8MP EVK LVDS1 connector <=3D> LVDS adapter card J6(IT6263 link1) 3) imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtso: i.MX8MP EVK LVDS0 connector <=3D> DLVDS adapter card channel0(IT6263 lin= k1) i.MX8MP EVK LVDS1 connector <=3D> DLVDS adapter card channel1(IT6263 lin= k2) 4) imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtso: i.MX8MP EVK LVDS1 connector <=3D> DLVDS adapter card channel0(IT6263 lin= k1) i.MX8MP EVK LVDS0 connector <=3D> DLVDS adapter card channel1(IT6263 lin= k2) Part links: https://www.nxp.com/part/IMX-LVDS-HDMI https://www.nxp.com/part/IMX-DLVDS-HDMI Signed-off-by: Liu Ying --- v2: * Add ite,lvds-link-num-data-lanes properties. arch/arm64/boot/dts/freescale/Makefile | 8 ++++ .../imx8mp-evk-imx-lvds-hdmi-common.dtsi | 29 ++++++++++++ ...8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtso | 44 +++++++++++++++++++ ...imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi | 43 ++++++++++++++++++ .../imx8mp-evk-lvds0-imx-lvds-hdmi.dtso | 28 ++++++++++++ ...8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtso | 44 +++++++++++++++++++ ...imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi | 43 ++++++++++++++++++ .../imx8mp-evk-lvds1-imx-lvds-hdmi.dtso | 28 ++++++++++++ arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 6 +++ 9 files changed, 273 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-evk-imx-lvds-hdmi-= common.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-dlvd= s-hdmi-channel0.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds= -hdmi-common.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds= -hdmi.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-dlvd= s-hdmi-channel0.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds= -hdmi-common.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds= -hdmi.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 9d3df8b218a2..cc4333f49c2d 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -196,7 +196,15 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-verdin-wifi-mallow.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-verdin-wifi-yavia.dtb =20 +imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0-dtbs +=3D imx8mp-evk.dtb imx8mp-e= vk-lvds0-imx-dlvds-hdmi-channel0.dtbo +imx8mp-evk-lvds0-imx-lvds-hdmi-dtbs +=3D imx8mp-evk.dtb imx8mp-evk-lvds0-i= mx-lvds-hdmi.dtbo +imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0-dtbs +=3D imx8mp-evk.dtb imx8mp-e= vk-lvds1-imx-dlvds-hdmi-channel0.dtbo +imx8mp-evk-lvds1-imx-lvds-hdmi-dtbs +=3D imx8mp-evk.dtb imx8mp-evk-lvds1-i= mx-lvds-hdmi.dtbo imx8mp-evk-mx8-dlvds-lcd1-dtbs +=3D imx8mp-evk.dtb imx8mp-evk-mx8-dlvds-lc= d1.dtbo +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-evk-lvds0-imx-lvds-hdmi.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-evk-lvds1-imx-lvds-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-evk-mx8-dlvds-lcd1.dtb =20 imx8mp-tqma8mpql-mba8mpxl-lvds-dtbs +=3D imx8mp-tqma8mpql-mba8mpxl.dtb imx= 8mp-tqma8mpql-mba8mpxl-lvds.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-imx-lvds-hdmi-common.= dtsi b/arch/arm64/boot/dts/freescale/imx8mp-evk-imx-lvds-hdmi-common.dtsi new file mode 100644 index 000000000000..44b30e9b3fde --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-imx-lvds-hdmi-common.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 NXP + */ + +/dts-v1/; +/plugin/; + +&{/} { + lvds-hdmi-connector { + compatible =3D "hdmi-connector"; + label =3D "J2"; + type =3D "a"; + + port { + lvds2hdmi_connector_in: endpoint { + remote-endpoint =3D <&it6263_out>; + }; + }; + }; +}; + +&lcdif2 { + status =3D "okay"; +}; + +&lvds_bridge { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-dlvds-hdmi-= channel0.dtso b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-dlvds-hd= mi-channel0.dtso new file mode 100644 index 000000000000..4008d2fd36d6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-dlvds-hdmi-channel= 0.dtso @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 NXP + */ + +#include "imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi" + +&it6263 { + ports { + port@0 { + reg =3D <0>; + dual-lvds-odd-pixels; + + it6263_lvds_link1: endpoint { + remote-endpoint =3D <&ldb_lvds_ch0>; + }; + }; + + port@1 { + reg =3D <1>; + dual-lvds-even-pixels; + + it6263_lvds_link2: endpoint { + remote-endpoint =3D <&ldb_lvds_ch1>; + }; + }; + }; +}; + +&lvds_bridge { + ports { + port@1 { + ldb_lvds_ch0: endpoint { + remote-endpoint =3D <&it6263_lvds_link1>; + }; + }; + + port@2 { + ldb_lvds_ch1: endpoint { + remote-endpoint =3D <&it6263_lvds_link2>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi-c= ommon.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi-c= ommon.dtsi new file mode 100644 index 000000000000..757ce878c7cb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi-common.d= tsi @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 NXP + */ + +#include +#include "imx8mp-evk-imx-lvds-hdmi-common.dtsi" + +&i2c2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + it6263: hdmi@4c { + compatible =3D "ite,it6263"; + reg =3D <0x4c>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lvds_en>; + reset-gpios =3D <&gpio1 10 GPIO_ACTIVE_LOW>; + ivdd-supply =3D <®_buck5>; + ovdd-supply =3D <®_vext_3v3>; + txavcc18-supply =3D <®_buck5>; + txavcc33-supply =3D <®_vext_3v3>; + pvcc1-supply =3D <®_buck5>; + pvcc2-supply =3D <®_buck5>; + avcc-supply =3D <®_vext_3v3>; + anvdd-supply =3D <®_buck5>; + apvdd-supply =3D <®_buck5>; + ite,lvds-link-num-data-lanes =3D /bits/ 8 <4>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@2 { + reg =3D <2>; + + it6263_out: endpoint { + remote-endpoint =3D <&lvds2hdmi_connector_in>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi.d= tso b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi.dtso new file mode 100644 index 000000000000..9e11f261ad13 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi.dtso @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 NXP + */ + +#include "imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi" + +&it6263 { + ports { + port@0 { + reg =3D <0>; + + it6263_lvds_link1: endpoint { + remote-endpoint =3D <&ldb_lvds_ch0>; + }; + }; + }; +}; + +&lvds_bridge { + ports { + port@1 { + ldb_lvds_ch0: endpoint { + remote-endpoint =3D <&it6263_lvds_link1>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-dlvds-hdmi-= channel0.dtso b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-dlvds-hd= mi-channel0.dtso new file mode 100644 index 000000000000..af2e73e36a1b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-dlvds-hdmi-channel= 0.dtso @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 NXP + */ + +#include "imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi" + +&it6263 { + ports { + port@0 { + reg =3D <0>; + dual-lvds-even-pixels; + + it6263_lvds_link1: endpoint { + remote-endpoint =3D <&ldb_lvds_ch1>; + }; + }; + + port@1 { + reg =3D <1>; + dual-lvds-odd-pixels; + + it6263_lvds_link2: endpoint { + remote-endpoint =3D <&ldb_lvds_ch0>; + }; + }; + }; +}; + +&lvds_bridge { + ports { + port@1 { + ldb_lvds_ch0: endpoint { + remote-endpoint =3D <&it6263_lvds_link2>; + }; + }; + + port@2 { + ldb_lvds_ch1: endpoint { + remote-endpoint =3D <&it6263_lvds_link1>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi-c= ommon.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi-c= ommon.dtsi new file mode 100644 index 000000000000..7381dbd0b7f6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi-common.d= tsi @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 NXP + */ + +#include +#include "imx8mp-evk-imx-lvds-hdmi-common.dtsi" + +&i2c3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + it6263: hdmi@4c { + compatible =3D "ite,it6263"; + reg =3D <0x4c>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lvds_en>; + reset-gpios =3D <&gpio1 10 GPIO_ACTIVE_LOW>; + ivdd-supply =3D <®_buck5>; + ovdd-supply =3D <®_vext_3v3>; + txavcc18-supply =3D <®_buck5>; + txavcc33-supply =3D <®_vext_3v3>; + pvcc1-supply =3D <®_buck5>; + pvcc2-supply =3D <®_buck5>; + avcc-supply =3D <®_vext_3v3>; + anvdd-supply =3D <®_buck5>; + apvdd-supply =3D <®_buck5>; + ite,lvds-link-num-data-lanes =3D /bits/ 8 <4>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@2 { + reg =3D <2>; + + it6263_out: endpoint { + remote-endpoint =3D <&lvds2hdmi_connector_in>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi.d= tso b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi.dtso new file mode 100644 index 000000000000..527a893a71b2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi.dtso @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 NXP + */ + +#include "imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi" + +&it6263 { + ports { + port@0 { + reg =3D <0>; + + it6263_lvds_link1: endpoint { + remote-endpoint =3D <&ldb_lvds_ch1>; + }; + }; + }; +}; + +&lvds_bridge { + ports { + port@2 { + ldb_lvds_ch1: endpoint { + remote-endpoint =3D <&it6263_lvds_link1>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot= /dts/freescale/imx8mp-evk.dts index d26930f1a9e9..68e12a752edd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -938,6 +938,12 @@ MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2 >; }; =20 + pinctrl_lvds_en: lvdsengrp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c0 + >; + }; + pinctrl_pcie0: pcie0grp { fsl,pins =3D < MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60 /* open drain, pull up */ --=20 2.34.1 From nobody Wed Nov 27 06:33:52 2024 Received: from EUR03-DBA-obe.outbound.protection.outlook.com (mail-dbaeur03on2062.outbound.protection.outlook.com [40.107.104.62]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 174111527B4; Sat, 12 Oct 2024 07:37:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.104.62 ARC-Seal: i=2; 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charset="utf-8" ITE IT6263 LVDS to HDMI converter is populated on NXP IMX-LVDS-HDMI and IMX-DLVDS-HDMI adapter cards. The adapter cards can connect to i.MX8MP EVK base board to support video output through HDMI connectors. Build the ITE IT6263 driver as a module. Signed-off-by: Liu Ying --- v2: * No change. arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 5fdbfea7a5b2..d8a232e285d4 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -899,6 +899,7 @@ CONFIG_DRM_PANEL_SITRONIX_ST7703=3Dm CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=3Dm CONFIG_DRM_PANEL_VISIONOX_VTDR6130=3Dm CONFIG_DRM_FSL_LDB=3Dm +CONFIG_DRM_ITE_IT6263=3Dm CONFIG_DRM_LONTIUM_LT8912B=3Dm CONFIG_DRM_LONTIUM_LT9611=3Dm CONFIG_DRM_LONTIUM_LT9611UXC=3Dm --=20 2.34.1 From nobody Wed Nov 27 06:33:52 2024 Received: from EUR03-AM7-obe.outbound.protection.outlook.com (mail-am7eur03on2043.outbound.protection.outlook.com [40.107.105.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9646143723; Sat, 12 Oct 2024 07:38:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Received: from AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) by DB8PR04MB6986.eurprd04.prod.outlook.com (2603:10a6:10:116::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.22; Sat, 12 Oct 2024 07:38:06 +0000 Received: from AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::d1ce:ea15:6648:6f90]) by AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::d1ce:ea15:6648:6f90%4]) with mapi id 15.20.8048.020; Sat, 12 Oct 2024 07:38:06 +0000 From: Liu Ying To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, geert+renesas@glider.be, dmitry.baryshkov@linaro.org, arnd@arndb.de, nfraprado@collabora.com, o.rempel@pengutronix.de, y.moog@phytec.de, marex@denx.de, isaac.scott@ideasonboard.com, biju.das.jz@bp.renesas.com Subject: [PATCH v2 9/9] MAINTAINERS: Add maintainer for ITE IT6263 driver Date: Sat, 12 Oct 2024 15:35:43 +0800 Message-Id: <20241012073543.1388069-10-victor.liu@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241012073543.1388069-1-victor.liu@nxp.com> References: <20241012073543.1388069-1-victor.liu@nxp.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SI2PR01CA0051.apcprd01.prod.exchangelabs.com (2603:1096:4:193::6) To AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM7PR04MB7046:EE_|DB8PR04MB6986:EE_ X-MS-Office365-Filtering-Correlation-Id: e1a235fb-07a3-49c8-a030-08dcea90cf9d X-LD-Processed: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|366016|52116014|38350700014; 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charset="utf-8" Add myself as the maintainer of ITE IT6263 LVDS TO HDMI BRIDGE DRIVER. Signed-off-by: Liu Ying --- v2: * New patch. (Maxime) MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a097afd76ded..3ce9ab8327e9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12142,6 +12142,14 @@ W: https://linuxtv.org Q: http://patchwork.linuxtv.org/project/linux-media/list/ F: drivers/media/tuners/it913x* =20 +ITE IT6263 LVDS TO HDMI BRIDGE DRIVER +M: Liu Ying +L: dri-devel@lists.freedesktop.org +S: Maintained +T: git https://gitlab.freedesktop.org/drm/misc/kernel.git +F: Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml +F: drivers/gpu/drm/bridge/ite-it6263.c + ITE IT66121 HDMI BRIDGE DRIVER M: Phong LE M: Neil Armstrong --=20 2.34.1