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Fri, 11 Oct 2024 20:30:31 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49BKUUIH024900 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 11 Oct 2024 20:30:30 GMT Received: from [10.213.111.143] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 11 Oct 2024 13:30:24 -0700 From: Akhil P Oommen Date: Sat, 12 Oct 2024 01:59:30 +0530 Subject: [PATCH RFC 3/3] arm64: dts: qcom: x1e80100: Add ACD levels for GPU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241012-gpu-acd-v1-3-1e5e91aa95b6@quicinc.com> References: <20241012-gpu-acd-v1-0-1e5e91aa95b6@quicinc.com> In-Reply-To: <20241012-gpu-acd-v1-0-1e5e91aa95b6@quicinc.com> To: Rob Clark , Sean Paul , "Konrad Dybcio" , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , "Simona Vetter" , Viresh Kumar , Nishanth Menon , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Akhil P Oommen , Bjorn Andersson CC: , , , , , X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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Signed-off-by: Akhil P Oommen --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index a36076e3c56b..e6c500480eb1 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3323,60 +3323,69 @@ zap-shader { }; =20 gpu_opp_table: opp-table { - compatible =3D "operating-points-v2"; + compatible =3D "operating-points-v2-adreno"; =20 opp-1100000000 { opp-hz =3D /bits/ 64 <1100000000>; opp-level =3D ; opp-peak-kBps =3D <16500000>; + qcom,opp-acd-level =3D <0xa82a5ffd>; }; =20 opp-1000000000 { opp-hz =3D /bits/ 64 <1000000000>; opp-level =3D ; opp-peak-kBps =3D <14398438>; + qcom,opp-acd-level =3D <0xa82b5ffd>; }; =20 opp-925000000 { opp-hz =3D /bits/ 64 <925000000>; opp-level =3D ; opp-peak-kBps =3D <14398438>; + qcom,opp-acd-level =3D <0xa82b5ffd>; }; =20 opp-800000000 { opp-hz =3D /bits/ 64 <800000000>; opp-level =3D ; opp-peak-kBps =3D <12449219>; + qcom,opp-acd-level =3D <0xa82c5ffd>; }; =20 opp-744000000 { opp-hz =3D /bits/ 64 <744000000>; opp-level =3D ; opp-peak-kBps =3D <10687500>; + qcom,opp-acd-level =3D <0x882e5ffd>; }; =20 opp-687000000 { opp-hz =3D /bits/ 64 <687000000>; opp-level =3D ; opp-peak-kBps =3D <8171875>; + qcom,opp-acd-level =3D <0x882e5ffd>; }; =20 opp-550000000 { opp-hz =3D /bits/ 64 <550000000>; opp-level =3D ; opp-peak-kBps =3D <6074219>; + qcom,opp-acd-level =3D <0xc0285ffd>; }; =20 opp-390000000 { opp-hz =3D /bits/ 64 <390000000>; opp-level =3D ; opp-peak-kBps =3D <3000000>; + qcom,opp-acd-level =3D <0xc0285ffd>; }; =20 opp-300000000 { opp-hz =3D /bits/ 64 <300000000>; opp-level =3D ; opp-peak-kBps =3D <2136719>; + qcom,opp-acd-level =3D <0xc02b5ffd>; }; }; }; --=20 2.45.2