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Fri, 11 Oct 2024 20:30:25 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49BKUOVx024444 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 11 Oct 2024 20:30:24 GMT Received: from [10.213.111.143] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 11 Oct 2024 13:30:18 -0700 From: Akhil P Oommen Date: Sat, 12 Oct 2024 01:59:29 +0530 Subject: [PATCH RFC 2/3] dt-bindings: opp: Add v2-qcom-adreno vendor bindings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241012-gpu-acd-v1-2-1e5e91aa95b6@quicinc.com> References: <20241012-gpu-acd-v1-0-1e5e91aa95b6@quicinc.com> In-Reply-To: <20241012-gpu-acd-v1-0-1e5e91aa95b6@quicinc.com> To: Rob Clark , Sean Paul , "Konrad Dybcio" , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , "Simona Vetter" , Viresh Kumar , Nishanth Menon , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Akhil P Oommen , Bjorn Andersson CC: , , , , , X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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The new property called "qcom,opp-acd-level" carries a u32 value recommended for each opp needs to be shared to GMU during runtime. Signed-off-by: Akhil P Oommen --- .../bindings/opp/opp-v2-qcom-adreno.yaml | 84 ++++++++++++++++++= ++++ 1 file changed, 84 insertions(+) diff --git a/Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml = b/Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml new file mode 100644 index 000000000000..9fb828e9da86 --- /dev/null +++ b/Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/opp/opp-v2-qcom-adreno.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Adreno compatible OPP supply + +description: + Adreno GPUs present in Qualcomm's Snapdragon chipsets uses an OPP specif= ic + ACD related information tailored for the specific chipset. This binding + provides the information needed to describe such a hardware value. + +maintainers: + - Rob Clark + +allOf: + - $ref: opp-v2-base.yaml# + +properties: + compatible: + const: operating-points-v2-adreno + +patternProperties: + '^opp-?[0-9]+$': + type: object + additionalProperties: false + + properties: + opp-hz: true + + opp-level: true + + opp-peak-kBps: true + + opp-supported-hw: true + + qcom,opp-acd-level: + description: | + A positive value representing the acd level associated with this + OPP node. This value is shared to GMU during GPU wake up. It may + not be present for some OPPs and GMU will disable ACD while + transitioning to that OPP. + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - opp-hz + - opp-level + +required: + - compatible + +additionalProperties: false + +examples: + - | + + #include + + gpu_opp_table: opp-table { + compatible =3D "operating-points-v2-adreno"; + + opp-550000000 { + opp-hz =3D /bits/ 64 <550000000>; + opp-level =3D ; + opp-peak-kBps =3D <6074219>; + qcom,opp-acd-level =3D <0xc0285ffd>; + }; + + opp-390000000 { + opp-hz =3D /bits/ 64 <390000000>; + opp-level =3D ; + opp-peak-kBps =3D <3000000>; + qcom,opp-acd-level =3D <0xc0285ffd>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + opp-level =3D ; + opp-peak-kBps =3D <2136719>; + /* Intentionally left out qcom,opp-acd-level property here= */ + }; + + }; --=20 2.45.2