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Signed-off-by: Jim Mattson --- arch/x86/include/asm/cpufeatures.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index dd4682857c12..644b3e1e1ab6 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -215,7 +215,7 @@ #define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23) /* Disable Specul= ative Store Bypass. */ #define X86_FEATURE_LS_CFG_SSBD ( 7*32+24) /* AMD SSBD implementation vi= a LS_CFG MSR */ #define X86_FEATURE_IBRS ( 7*32+25) /* "ibrs" Indirect Branch Restricted = Speculation */ -#define X86_FEATURE_IBPB ( 7*32+26) /* "ibpb" Indirect Branch Prediction = Barrier */ +#define X86_FEATURE_IBPB ( 7*32+26) /* "ibpb" Indirect Branch Prediction = Barrier without a guaranteed RSB flush */ #define X86_FEATURE_STIBP ( 7*32+27) /* "stibp" Single Thread Indirect Br= anch Predictors */ #define X86_FEATURE_ZEN ( 7*32+28) /* Generic flag for all Zen and newer= */ #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* L1TF workaround PTE inversi= on */ --=20 2.47.0.rc1.288.g06298d1525-goog From nobody Wed Nov 27 07:49:18 2024 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36CBB1D174E for ; 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Fri, 11 Oct 2024 14:44:19 -0700 (PDT) Date: Fri, 11 Oct 2024 14:43:51 -0700 In-Reply-To: <20241011214353.1625057-1-jmattson@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241011214353.1625057-1-jmattson@google.com> X-Mailer: git-send-email 2.47.0.rc1.288.g06298d1525-goog Message-ID: <20241011214353.1625057-3-jmattson@google.com> Subject: [PATCH v5 2/4] x86/cpufeatures: Define X86_FEATURE_AMD_IBPB_RET From: Jim Mattson To: kvm@vger.kernel.org Cc: bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, jpoimboe@kernel.org, kai.huang@intel.com, linux-kernel@vger.kernel.org, mingo@redhat.com, pawan.kumar.gupta@linux.intel.com, pbonzini@redhat.com, sandipan.das@amd.com, seanjc@google.com, tglx@linutronix.de, x86@kernel.org, Jim Mattson , Venkatesh Srinivas , Tom Lendacky Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AMD's initial implementation of IBPB did not clear the return address predictor. Beginning with Zen4, AMD's IBPB *does* clear the return address predictor. This behavior is enumerated by CPUID.80000008H:EBX.IBPB_RET[bit 30]. Define X86_FEATURE_AMD_IBPB_RET for use in KVM_GET_SUPPORTED_CPUID, when determining cross-vendor capabilities. Suggested-by: Venkatesh Srinivas Signed-off-by: Jim Mattson Reviewed-by: Tom Lendacky Reviewed-by: Thomas Gleixner --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 644b3e1e1ab6..a222a24677d7 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -348,6 +348,7 @@ #define X86_FEATURE_CPPC (13*32+27) /* "cppc" Collaborative Processor Per= formance Control */ #define X86_FEATURE_AMD_PSFD (13*32+28) /* Predictive Store For= warding Disable */ #define X86_FEATURE_BTC_NO (13*32+29) /* Not vulnerable to Branch Type Co= nfusion */ +#define X86_FEATURE_AMD_IBPB_RET (13*32+30) /* IBPB clears return address = predictor */ #define X86_FEATURE_BRS (13*32+31) /* "brs" Branch Sampling available */ =20 /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 1= 4 */ --=20 2.47.0.rc1.288.g06298d1525-goog From nobody Wed Nov 27 07:49:18 2024 Received: from mail-pf1-f202.google.com (mail-pf1-f202.google.com [209.85.210.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D24CC1D1753 for ; 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Fri, 11 Oct 2024 14:44:23 -0700 (PDT) Date: Fri, 11 Oct 2024 14:43:52 -0700 In-Reply-To: <20241011214353.1625057-1-jmattson@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241011214353.1625057-1-jmattson@google.com> X-Mailer: git-send-email 2.47.0.rc1.288.g06298d1525-goog Message-ID: <20241011214353.1625057-4-jmattson@google.com> Subject: [PATCH v5 3/4] KVM: x86: Advertise AMD_IBPB_RET to userspace From: Jim Mattson To: kvm@vger.kernel.org Cc: bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, jpoimboe@kernel.org, kai.huang@intel.com, linux-kernel@vger.kernel.org, mingo@redhat.com, pawan.kumar.gupta@linux.intel.com, pbonzini@redhat.com, sandipan.das@amd.com, seanjc@google.com, tglx@linutronix.de, x86@kernel.org, Jim Mattson , Tom Lendacky Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This is an inherent feature of IA32_PRED_CMD[0], so it is trivially virtualizable (as long as IA32_PRED_CMD[0] is virtualized). Suggested-by: Tom Lendacky Signed-off-by: Jim Mattson Reviewed-by: Tom Lendacky Reviewed-by: Thomas Gleixner --- arch/x86/kvm/cpuid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 41786b834b16..53112669be00 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -755,7 +755,7 @@ void kvm_set_cpu_caps(void) F(CLZERO) | F(XSAVEERPTR) | F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) | F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) | - F(AMD_PSFD) + F(AMD_PSFD) | F(AMD_IBPB_RET) ); =20 /* --=20 2.47.0.rc1.288.g06298d1525-goog From nobody Wed Nov 27 07:49:18 2024 Received: from mail-pl1-f202.google.com (mail-pl1-f202.google.com [209.85.214.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 585A61D1E72 for ; Fri, 11 Oct 2024 21:44:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 11 Oct 2024 14:44:26 -0700 (PDT) Date: Fri, 11 Oct 2024 14:43:53 -0700 In-Reply-To: <20241011214353.1625057-1-jmattson@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241011214353.1625057-1-jmattson@google.com> X-Mailer: git-send-email 2.47.0.rc1.288.g06298d1525-goog Message-ID: <20241011214353.1625057-5-jmattson@google.com> Subject: [PATCH v5 4/4] KVM: x86: AMD's IBPB is not equivalent to Intel's IBPB From: Jim Mattson To: kvm@vger.kernel.org Cc: bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, jpoimboe@kernel.org, kai.huang@intel.com, linux-kernel@vger.kernel.org, mingo@redhat.com, pawan.kumar.gupta@linux.intel.com, pbonzini@redhat.com, sandipan.das@amd.com, seanjc@google.com, tglx@linutronix.de, x86@kernel.org, Jim Mattson , Venkatesh Srinivas Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From Intel's documention [1], "CPUID.(EAX=3D07H,ECX=3D0):EDX[26] enumerates support for indirect branch restricted speculation (IBRS) and the indirect branch predictor barrier (IBPB)." Further, from [2], "Software that executed before the IBPB command cannot control the predicted targets of indirect branches (4) executed after the command on the same logical processor," where footnote 4 reads, "Note that indirect branches include near call indirect, near jump indirect and near return instructions. Because it includes near returns, it follows that **RSB entries created before an IBPB command cannot control the predicted targets of returns executed after the command on the same logical processor.**" [emphasis mine] On the other hand, AMD's IBPB "may not prevent return branch predictions from being specified by pre-IBPB branch targets" [3]. However, some AMD processors have an "enhanced IBPB" [terminology mine] which does clear the return address predictor. This feature is enumerated by CPUID.80000008:EDX.IBPB_RET[bit 30] [4]. Adjust the cross-vendor features enumerated by KVM_GET_SUPPORTED_CPUID accordingly. [1] https://www.intel.com/content/www/us/en/developer/articles/technical/so= ftware-security-guidance/technical-documentation/cpuid-enumeration-and-arch= itectural-msrs.html [2] https://www.intel.com/content/www/us/en/developer/articles/technical/so= ftware-security-guidance/technical-documentation/speculative-execution-side= -channel-mitigations.html#Footnotes [3] https://www.amd.com/en/resources/product-security/bulletin/amd-sb-1040.= html [4] https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/pr= ogrammer-references/24594.pdf Fixes: 0c54914d0c52 ("KVM: x86: use Intel speculation bugs and features as = derived in generic x86 code") Suggested-by: Venkatesh Srinivas Signed-off-by: Jim Mattson Reviewed-by: Tom Lendacky --- arch/x86/kvm/cpuid.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 53112669be00..d695e7bc41ed 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -690,7 +690,9 @@ void kvm_set_cpu_caps(void) kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST); kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES); =20 - if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS)) + if (boot_cpu_has(X86_FEATURE_AMD_IBPB_RET) && + boot_cpu_has(X86_FEATURE_AMD_IBPB) && + boot_cpu_has(X86_FEATURE_AMD_IBRS)) kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL); if (boot_cpu_has(X86_FEATURE_STIBP)) kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP); @@ -763,8 +765,12 @@ void kvm_set_cpu_caps(void) * arch/x86/kernel/cpu/bugs.c is kind enough to * record that in cpufeatures so use them. */ - if (boot_cpu_has(X86_FEATURE_IBPB)) + if (boot_cpu_has(X86_FEATURE_IBPB)) { kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB); + if (boot_cpu_has(X86_FEATURE_SPEC_CTRL) && + !boot_cpu_has_bug(X86_BUG_EIBRS_PBRSB)) + kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB_RET); + } if (boot_cpu_has(X86_FEATURE_IBRS)) kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS); if (boot_cpu_has(X86_FEATURE_STIBP)) --=20 2.47.0.rc1.288.g06298d1525-goog