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([194.62.169.86]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a99c0c89bfasm54134666b.162.2024.10.11.07.48.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2024 07:48:28 -0700 (PDT) From: Emil Renner Berthing To: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Linus Walleij , Jisheng Zhang , Guo Ren , Fu Wei , Paul Walmsley , Palmer Dabbelt , Thomas Bonnefille Subject: [PATCH v1 1/3] pinctrl: th1520: Fix pinconf return values Date: Fri, 11 Oct 2024 16:48:23 +0200 Message-ID: <20241011144826.381104-2-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241011144826.381104-1-emil.renner.berthing@canonical.com> References: <20241011144826.381104-1-emil.renner.berthing@canonical.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When Drew took over the pinctrl driver he must have changed all the -ENOTSUPP returns into -EOPNOTSUPP. This subtle change was most likely not spotted because it was never mentioned in the changelog of the patchset, but it breaks all the places in the pin control and GPIO frameworks where -ENOTSUPP is expected. Fixes: bed5cd6f8a98 ("pinctrl: Add driver for the T-Head TH1520 SoC") Signed-off-by: Emil Renner Berthing Reviewed-by: Drew Fustini Tested-by: Drew Fustini --- drivers/pinctrl/pinctrl-th1520.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/pinctrl-th1520.c b/drivers/pinctrl/pinctrl-th1= 520.c index c8d2ee6defa7..03326df69668 100644 --- a/drivers/pinctrl/pinctrl-th1520.c +++ b/drivers/pinctrl/pinctrl-th1520.c @@ -591,7 +591,7 @@ static int th1520_pinconf_get(struct pinctrl_dev *pctld= ev, u32 arg; =20 if ((uintptr_t)desc->drv_data & TH1520_PAD_NO_PADCFG) - return -EOPNOTSUPP; + return -ENOTSUPP; =20 value =3D readl_relaxed(th1520_padcfg(thp, pin)); value =3D (value >> th1520_padcfg_shift(pin)) & GENMASK(9, 0); @@ -636,7 +636,7 @@ static int th1520_pinconf_get(struct pinctrl_dev *pctld= ev, arg =3D enabled ? 1 : 0; break; default: - return -EOPNOTSUPP; + return -ENOTSUPP; } =20 *config =3D pinconf_to_config_packed(param, arg); @@ -661,7 +661,7 @@ static int th1520_pinconf_set(struct pinctrl_dev *pctld= ev, unsigned int pin, u16 mask, value; =20 if ((uintptr_t)desc->drv_data & TH1520_PAD_NO_PADCFG) - return -EOPNOTSUPP; + return -ENOTSUPP; =20 mask =3D 0; value =3D 0; @@ -676,14 +676,14 @@ static int th1520_pinconf_set(struct pinctrl_dev *pct= ldev, unsigned int pin, break; case PIN_CONFIG_BIAS_PULL_DOWN: if (arg =3D=3D 0) - return -EOPNOTSUPP; + return -ENOTSUPP; mask |=3D TH1520_PADCFG_BIAS; value &=3D ~TH1520_PADCFG_BIAS; value |=3D TH1520_PADCFG_PE; break; case PIN_CONFIG_BIAS_PULL_UP: if (arg =3D=3D 0) - return -EOPNOTSUPP; + return -ENOTSUPP; mask |=3D TH1520_PADCFG_BIAS; value &=3D ~TH1520_PADCFG_BIAS; if (arg =3D=3D TH1520_PULL_STRONG_OHM) @@ -718,7 +718,7 @@ static int th1520_pinconf_set(struct pinctrl_dev *pctld= ev, unsigned int pin, value &=3D ~TH1520_PADCFG_SL; break; default: - return -EOPNOTSUPP; + return -ENOTSUPP; } } =20 --=20 2.43.0 From nobody Wed Nov 27 06:45:42 2024 Received: from smtp-relay-internal-0.canonical.com (smtp-relay-internal-0.canonical.com [185.125.188.122]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2EFCA19146E for ; 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([194.62.169.86]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a99c0c89bfasm54134666b.162.2024.10.11.07.48.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2024 07:48:30 -0700 (PDT) From: Emil Renner Berthing To: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Linus Walleij , Jisheng Zhang , Guo Ren , Fu Wei , Paul Walmsley , Palmer Dabbelt , Thomas Bonnefille Subject: [PATCH v1 2/3] pinctrl: th1520: Update pinmux tables Date: Fri, 11 Oct 2024 16:48:24 +0200 Message-ID: <20241011144826.381104-3-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241011144826.381104-1-emil.renner.berthing@canonical.com> References: <20241011144826.381104-1-emil.renner.berthing@canonical.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When Drew took over the pinctrl driver it seems like he didn't use the git tree I pointed him at and thus missed some important fixes to the tables describing valid pinmux settings. The documentation has a nice overview table of these settings but unfortunately it doesn't fully match the register descriptions, which seem to be the correct version. Fixes: bed5cd6f8a98 ("pinctrl: Add driver for the T-Head TH1520 SoC") Signed-off-by: Emil Renner Berthing Reviewed-by: Drew Fustini Tested-by: Drew Fustini --- drivers/pinctrl/pinctrl-th1520.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/pinctrl/pinctrl-th1520.c b/drivers/pinctrl/pinctrl-th1= 520.c index 03326df69668..8bd40cb2f013 100644 --- a/drivers/pinctrl/pinctrl-th1520.c +++ b/drivers/pinctrl/pinctrl-th1520.c @@ -221,9 +221,9 @@ static const struct pinctrl_pin_desc th1520_group2_pins= [] =3D { TH1520_PAD(15, UART4_RTSN, UART, ____, ____, GPIO, ____, ____, 0), TH1520_PAD(16, UART3_TXD, DBG, UART, ____, GPIO, ____, ____, 0), TH1520_PAD(17, UART3_RXD, DBG, UART, ____, GPIO, ____, ____, 0), - TH1520_PAD(18, GPIO0_18, GPIO, I2C, ____, ____, ____, ____, 0), - TH1520_PAD(19, GPIO0_19, GPIO, I2C, ____, ____, ____, ____, 0), - TH1520_PAD(20, GPIO0_20, GPIO, UART, IR, ____, ____, ____, 0), + TH1520_PAD(18, GPIO0_18, GPIO, I2C, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(19, GPIO0_19, GPIO, I2C, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(20, GPIO0_20, GPIO, UART, IR, ____, DPU0, DPU1, 0), TH1520_PAD(21, GPIO0_21, GPIO, UART, IR, ____, DPU0, DPU1, 0), TH1520_PAD(22, GPIO0_22, GPIO, JTAG, I2C, ____, DPU0, DPU1, 0), TH1520_PAD(23, GPIO0_23, GPIO, JTAG, I2C, ____, DPU0, DPU1, 0), @@ -241,7 +241,7 @@ static const struct pinctrl_pin_desc th1520_group2_pins= [] =3D { TH1520_PAD(35, GPIO1_3, GPIO, JTAG, ____, ____, DPU0, DPU1, 0), TH1520_PAD(36, GPIO1_4, GPIO, JTAG, ____, ____, DPU0, DPU1, 0), TH1520_PAD(37, GPIO1_5, GPIO, ____, ____, ____, DPU0, DPU1, 0), - TH1520_PAD(38, GPIO1_6, GPIO, ____, ____, ____, DPU0, DPU1, 0), + TH1520_PAD(38, GPIO1_6, GPIO, QSPI, ____, ____, DPU0, DPU1, 0), TH1520_PAD(39, GPIO1_7, GPIO, QSPI, ____, ____, DPU0, DPU1, 0), TH1520_PAD(40, GPIO1_8, GPIO, QSPI, ____, ____, DPU0, DPU1, 0), TH1520_PAD(41, GPIO1_9, GPIO, QSPI, ____, ____, DPU0, DPU1, 0), @@ -256,11 +256,11 @@ static const struct pinctrl_pin_desc th1520_group2_pi= ns[] =3D { TH1520_PAD(50, CLK_OUT_1, BSEL, CLK, ____, GPIO, ____, ____, 0), TH1520_PAD(51, CLK_OUT_2, BSEL, CLK, ____, GPIO, ____, ____, 0), TH1520_PAD(52, CLK_OUT_3, BSEL, CLK, ____, GPIO, ____, ____, 0), - TH1520_PAD(53, GPIO1_21, GPIO, ____, ISP, ____, ____, ____, 0), - TH1520_PAD(54, GPIO1_22, GPIO, ____, ISP, ____, ____, ____, 0), - TH1520_PAD(55, GPIO1_23, GPIO, ____, ISP, ____, ____, ____, 0), - TH1520_PAD(56, GPIO1_24, GPIO, ____, ISP, ____, ____, ____, 0), - TH1520_PAD(57, GPIO1_25, GPIO, ____, ISP, ____, ____, ____, 0), + TH1520_PAD(53, GPIO1_21, JTAG, ____, ISP, GPIO, ____, ____, 0), + TH1520_PAD(54, GPIO1_22, JTAG, ____, ISP, GPIO, ____, ____, 0), + TH1520_PAD(55, GPIO1_23, JTAG, ____, ISP, GPIO, ____, ____, 0), + TH1520_PAD(56, GPIO1_24, JTAG, ____, ISP, GPIO, ____, ____, 0), + TH1520_PAD(57, GPIO1_25, JTAG, ____, ISP, GPIO, ____, ____, 0), TH1520_PAD(58, GPIO1_26, GPIO, ____, ISP, ____, ____, ____, 0), TH1520_PAD(59, GPIO1_27, GPIO, ____, ISP, ____, ____, ____, 0), TH1520_PAD(60, GPIO1_28, GPIO, ____, ISP, ____, ____, ____, 0), --=20 2.43.0 From nobody Wed Nov 27 06:45:42 2024 Received: from smtp-relay-internal-0.canonical.com (smtp-relay-internal-0.canonical.com [185.125.188.122]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C217194085 for ; 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([194.62.169.86]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a99c0c89bfasm54134666b.162.2024.10.11.07.48.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2024 07:48:31 -0700 (PDT) From: Emil Renner Berthing To: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Linus Walleij , Jisheng Zhang , Guo Ren , Fu Wei , Paul Walmsley , Palmer Dabbelt , Thomas Bonnefille Subject: [PATCH v1 3/3] pinctrl: th1520: Factor out casts Date: Fri, 11 Oct 2024 16:48:25 +0200 Message-ID: <20241011144826.381104-4-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241011144826.381104-1-emil.renner.berthing@canonical.com> References: <20241011144826.381104-1-emil.renner.berthing@canonical.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Limit the casts to get the mux data and flags from the driver data pointer with each pin to two inline functions as requested by Andy during review. Signed-off-by: Emil Renner Berthing Reviewed-by: Drew Fustini Tested-by: Drew Fustini --- drivers/pinctrl/pinctrl-th1520.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/pinctrl-th1520.c b/drivers/pinctrl/pinctrl-th1= 520.c index 8bd40cb2f013..7474d8da32f9 100644 --- a/drivers/pinctrl/pinctrl-th1520.c +++ b/drivers/pinctrl/pinctrl-th1520.c @@ -152,6 +152,16 @@ static enum th1520_muxtype th1520_muxtype_get(const ch= ar *str) (TH1520_MUX_##m0 << 0) | (TH1520_MUX_##m1 << 5) | (TH1520_MUX_##m2 << = 10) | \ (TH1520_MUX_##m3 << 15) | (TH1520_MUX_##m4 << 20) | (TH1520_MUX_##m5 << = 25)) } =20 +static unsigned long th1520_pad_muxdata(void *drv_data) +{ + return (uintptr_t)drv_data & TH1520_PAD_MUXDATA; +} + +static bool th1520_pad_no_padcfg(void *drv_data) +{ + return (uintptr_t)drv_data & TH1520_PAD_NO_PADCFG; +} + static const struct pinctrl_pin_desc th1520_group1_pins[] =3D { TH1520_PAD(0, OSC_CLK_IN, ____, ____, ____, ____, ____, ____, TH1520_= PAD_NO_PADCFG), TH1520_PAD(1, OSC_CLK_OUT, ____, ____, ____, ____, ____, ____, TH1520_= PAD_NO_PADCFG), @@ -590,7 +600,7 @@ static int th1520_pinconf_get(struct pinctrl_dev *pctld= ev, u32 value; u32 arg; =20 - if ((uintptr_t)desc->drv_data & TH1520_PAD_NO_PADCFG) + if (th1520_pad_no_padcfg(desc->drv_data)) return -ENOTSUPP; =20 value =3D readl_relaxed(th1520_padcfg(thp, pin)); @@ -660,7 +670,7 @@ static int th1520_pinconf_set(struct pinctrl_dev *pctld= ev, unsigned int pin, unsigned int i; u16 mask, value; =20 - if ((uintptr_t)desc->drv_data & TH1520_PAD_NO_PADCFG) + if (th1520_pad_no_padcfg(desc->drv_data)) return -ENOTSUPP; =20 mask =3D 0; @@ -793,12 +803,14 @@ static int th1520_pinmux_set_mux(struct pinctrl_dev *= pctldev, { struct th1520_pinctrl *thp =3D pinctrl_dev_get_drvdata(pctldev); const struct function_desc *func =3D pinmux_generic_get_function(pctldev,= fsel); + enum th1520_muxtype muxtype =3D (uintptr_t)func->data; =20 if (!func) return -EINVAL; + return th1520_pinmux_set(thp, thp->desc.pins[gsel].number, - (uintptr_t)thp->desc.pins[gsel].drv_data & TH1520_PAD_MUXDATA, - (uintptr_t)func->data); + th1520_pad_muxdata(thp->desc.pins[gsel].drv_data), + muxtype); } =20 static int th1520_gpio_request_enable(struct pinctrl_dev *pctldev, @@ -809,7 +821,7 @@ static int th1520_gpio_request_enable(struct pinctrl_de= v *pctldev, const struct pin_desc *desc =3D pin_desc_get(pctldev, offset); =20 return th1520_pinmux_set(thp, offset, - (uintptr_t)desc->drv_data & TH1520_PAD_MUXDATA, + th1520_pad_muxdata(desc->drv_data), TH1520_MUX_GPIO); } =20 --=20 2.43.0