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charset="utf-8" On SC8280X family SoC, PCIe controllers are connected to SMMUv3, hence they don't need the config_sid() callback in ops_1_9_0 struct. Fix it by introducing a new ops struct, namely ops_1_21_0, so that BDF2SID mapping won't be configured during init. Fixes: d1997c987814 ("PCI: qcom: Disable ASPM L0s for sc8280xp, sa8540p and= sa8295p") Signed-off-by: Qiang Yu Reviewed-by: Dmitry Baryshkov Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 88a98be930e3..468bd4242e61 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1367,6 +1367,16 @@ static const struct qcom_pcie_ops ops_2_9_0 =3D { .ltssm_enable =3D qcom_pcie_2_3_2_ltssm_enable, }; =20 +/* Qcom IP rev.: 1.21.0 */ +static const struct qcom_pcie_ops ops_1_21_0 =3D { + .get_resources =3D qcom_pcie_get_resources_2_7_0, + .init =3D qcom_pcie_init_2_7_0, + .post_init =3D qcom_pcie_post_init_2_7_0, + .host_post_init =3D qcom_pcie_host_post_init_2_7_0, + .deinit =3D qcom_pcie_deinit_2_7_0, + .ltssm_enable =3D qcom_pcie_2_3_2_ltssm_enable, +}; + static const struct qcom_pcie_cfg cfg_1_0_0 =3D { .ops =3D &ops_1_0_0, }; @@ -1405,7 +1415,7 @@ static const struct qcom_pcie_cfg cfg_2_9_0 =3D { }; =20 static const struct qcom_pcie_cfg cfg_sc8280xp =3D { - .ops =3D &ops_1_9_0, + .ops =3D &ops_1_21_0, .no_l0s =3D true, }; =20 --=20 2.34.1