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charset="utf-8" Document 'global' SPI interrupt along with the existing MSI interrupts so that QCOM PCIe RC driver can make use of it to get events such as PCIe link specific events, safety events, etc. Though adding a new interrupt will break the ABI, it is required to accurately describe the hardware. Signed-off-by: Qiang Yu --- .../devicetree/bindings/pci/qcom,pcie-x1e80100.yaml | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml = b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml index a9db0a231563..2c0e01fc0ab8 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml @@ -46,8 +46,8 @@ properties: - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock =20 interrupts: - minItems: 8 - maxItems: 8 + minItems: 9 + maxItems: 9 =20 interrupt-names: items: @@ -59,6 +59,7 @@ properties: - const: msi5 - const: msi6 - const: msi7 + - const: global =20 resets: minItems: 1 @@ -130,9 +131,10 @@ examples: , , , - ; + , + ; interrupt-names =3D "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7"; + "msi4", "msi5", "msi6", "msi7", "global"; #interrupt-cells =3D <1>; interrupt-map-mask =3D <0 0 0 0x7>; interrupt-map =3D <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH= >, /* int_a */ --=20 2.34.1