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[2001:b400:e38a:6880:f424:8486:7476:9f9d]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71e2aa93876sm1946980b3a.114.2024.10.10.22.52.42 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 Oct 2024 22:52:43 -0700 (PDT) From: Tyrone Ting X-Google-Original-From: Tyrone Ting To: avifishman70@gmail.com, tmaimon77@gmail.com, tali.perry1@gmail.com, venture@google.com, yuenn@google.com, benjaminfair@google.com, andi.shyti@kernel.org, andriy.shevchenko@linux.intel.com, wsa@kernel.org, rand.sec96@gmail.com, wsa+renesas@sang-engineering.com, warp5tw@gmail.com, tali.perry@nuvoton.com, Avi.Fishman@nuvoton.com, tomer.maimon@nuvoton.com, KWLIU@nuvoton.com, JJLIU0@nuvoton.com, kfting@nuvoton.com Cc: openbmc@lists.ozlabs.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 1/4] i2c: npcm: Modify timeout evaluation mechanism Date: Fri, 11 Oct 2024 13:52:28 +0800 Message-Id: <20241011055231.9826-2-kfting@nuvoton.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241011055231.9826-1-kfting@nuvoton.com> References: <20241011055231.9826-1-kfting@nuvoton.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Tyrone Ting The users want to connect a lot of masters on the same bus. This timeout is used to determine the time it takes to take bus ownership. The transactions are very long, so waiting 35ms is not enough. Increase the timeout and treat it as the total timeout, including retries. The total timeout is 2 seconds now. The i2c core layer will have chances to retry to call the i2c driver transfer function if the i2c driver reports that the bus is busy and returns -EAGAIN. Signed-off-by: Tyrone Ting Reviewed-by: Tali Perry --- drivers/i2c/busses/i2c-npcm7xx.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/drivers/i2c/busses/i2c-npcm7xx.c b/drivers/i2c/busses/i2c-npcm= 7xx.c index 482a0074d448..c96a25d37c14 100644 --- a/drivers/i2c/busses/i2c-npcm7xx.c +++ b/drivers/i2c/busses/i2c-npcm7xx.c @@ -2132,19 +2132,12 @@ static int npcm_i2c_master_xfer(struct i2c_adapter = *adap, struct i2c_msg *msgs, } } =20 - /* - * Adaptive TimeOut: estimated time in usec + 100% margin: - * 2: double the timeout for clock stretching case - * 9: bits per transaction (including the ack/nack) - */ - timeout_usec =3D (2 * 9 * USEC_PER_SEC / bus->bus_freq) * (2 + nread + nw= rite); - timeout =3D max_t(unsigned long, bus->adap.timeout, usecs_to_jiffies(time= out_usec)); if (nwrite >=3D 32 * 1024 || nread >=3D 32 * 1024) { dev_err(bus->dev, "i2c%d buffer too big\n", bus->num); return -EINVAL; } =20 - time_left =3D jiffies + timeout + 1; + time_left =3D jiffies + bus->adap.timeout / bus->adap.retries + 1; do { /* * we must clear slave address immediately when the bus is not @@ -2192,6 +2185,14 @@ static int npcm_i2c_master_xfer(struct i2c_adapter *= adap, struct i2c_msg *msgs, if (npcm_i2c_master_start_xmit(bus, slave_addr, nwrite, nread, write_data, read_data, read_PEC, read_block)) { + /* + * Adaptive TimeOut: estimated time in usec + 100% margin: + * 2: double the timeout for clock stretching case + * 9: bits per transaction (including the ack/nack) + */ + timeout_usec =3D (2 * 9 * USEC_PER_SEC / bus->bus_freq) * (2 + nread + n= write); + timeout =3D max_t(unsigned long, bus->adap.timeout / bus->adap.retries, + usecs_to_jiffies(timeout_usec)); time_left =3D wait_for_completion_timeout(&bus->cmd_complete, timeout); =20 @@ -2317,7 +2318,12 @@ static int npcm_i2c_probe_bus(struct platform_device= *pdev) adap =3D &bus->adap; adap->owner =3D THIS_MODULE; adap->retries =3D 3; - adap->timeout =3D msecs_to_jiffies(35); + /* + * The users want to connect a lot of masters on the same bus. + * This timeout is used to determine the time it takes to take bus owners= hip. + * The transactions are very long, so waiting 35ms is not enough. + */ + adap->timeout =3D 2 * HZ; adap->algo =3D &npcm_i2c_algo; adap->quirks =3D &npcm_i2c_quirks; adap->algo_data =3D bus; --=20 2.34.1 From nobody Wed Nov 27 09:50:39 2024 Received: from mail-ot1-f45.google.com (mail-ot1-f45.google.com [209.85.210.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6408D1EABA2; Fri, 11 Oct 2024 05:52:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728625970; cv=none; b=hdvI9gzuawO1ijKOIGoOMo7IeTMulV5FusesN2EgK5QlJD2E/jRhObl19KYZIerWaoFNRp5pxdu32TeeYoAX6Naibn75Hbpe/O7qBANNfs8ih7pu0twoEHTjuRcAJZxhWLKeimYg3w9RpirSHkqMRDe+hWMfS+Yb0NGmy60ioWI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728625970; c=relaxed/simple; bh=+Zy2b8GIOJelJNHOlnTeXcJBLrhjFz0c7jN0NoS7G+U=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; 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[2001:b400:e38a:6880:f424:8486:7476:9f9d]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7ea449663e7sm1910843a12.76.2024.10.10.22.52.47 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 Oct 2024 22:52:47 -0700 (PDT) From: Tyrone Ting X-Google-Original-From: Tyrone Ting To: avifishman70@gmail.com, tmaimon77@gmail.com, tali.perry1@gmail.com, venture@google.com, yuenn@google.com, benjaminfair@google.com, andi.shyti@kernel.org, andriy.shevchenko@linux.intel.com, wsa@kernel.org, rand.sec96@gmail.com, wsa+renesas@sang-engineering.com, warp5tw@gmail.com, tali.perry@nuvoton.com, Avi.Fishman@nuvoton.com, tomer.maimon@nuvoton.com, KWLIU@nuvoton.com, JJLIU0@nuvoton.com, kfting@nuvoton.com Cc: openbmc@lists.ozlabs.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 2/4] i2c: npcm: Modify the client address assignment Date: Fri, 11 Oct 2024 13:52:29 +0800 Message-Id: <20241011055231.9826-3-kfting@nuvoton.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241011055231.9826-1-kfting@nuvoton.com> References: <20241011055231.9826-1-kfting@nuvoton.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Tyrone Ting Store the client address earlier since it might get called in the i2c_recover_bus() logic flow at the early stage of npcm_i2c_master_xfer(). Signed-off-by: Tyrone Ting Reviewed-by: Tali Perry --- drivers/i2c/busses/i2c-npcm7xx.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-npcm7xx.c b/drivers/i2c/busses/i2c-npcm= 7xx.c index c96a25d37c14..349492f114e7 100644 --- a/drivers/i2c/busses/i2c-npcm7xx.c +++ b/drivers/i2c/busses/i2c-npcm7xx.c @@ -2155,6 +2155,19 @@ static int npcm_i2c_master_xfer(struct i2c_adapter *= adap, struct i2c_msg *msgs, =20 } while (time_is_after_jiffies(time_left) && bus_busy); =20 + /* + * Previously, the address was stored w/o left-shift by one bit and + * with that shift in the following call to npcm_i2c_master_start_xmit(). + * + * Since there are cases that the i2c_recover_bus() gets called at the + * early stage of npcm_i2c_master_xfer(), the address is stored with + * the shift and used in the i2c_recover_bus(). + * + * The address is stored from bit 1 to bit 7 in the register for + * sending the i2c address later so it's left-shifted by 1 bit. + */ + bus->dest_addr =3D i2c_8bit_addr_from_msg(msg0); + /* * Check the BER (bus error) state, when ber_state is true, it means that= the module * detects the bus error which is caused by some factor like that the ele= ctricity @@ -2165,6 +2178,16 @@ static int npcm_i2c_master_xfer(struct i2c_adapter *= adap, struct i2c_msg *msgs, * bus is busy. */ if (bus_busy || bus->ber_state) { + /* + * Since the transfer might be a read operation, remove the I2C_M_RD flag + * from the bus->dest_addr for the i2c_recover_bus() call later. + * + * The i2c_recover_bus() uses the address in a write direction to recover + * the i2c bus if some error condition occurs. + */ + if (bus->dest_addr & I2C_M_RD) + bus->dest_addr &=3D ~I2C_M_RD; + iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST); npcm_i2c_reset(bus); i2c_recover_bus(adap); @@ -2172,7 +2195,6 @@ static int npcm_i2c_master_xfer(struct i2c_adapter *a= dap, struct i2c_msg *msgs, } =20 npcm_i2c_init_params(bus); - bus->dest_addr =3D slave_addr; bus->msgs =3D msgs; bus->msgs_num =3D num; bus->cmd_err =3D 0; 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[2001:b400:e38a:6880:f424:8486:7476:9f9d]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2d5fc5e35sm2393669a91.54.2024.10.10.22.52.51 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 Oct 2024 22:52:51 -0700 (PDT) From: Tyrone Ting X-Google-Original-From: Tyrone Ting To: avifishman70@gmail.com, tmaimon77@gmail.com, tali.perry1@gmail.com, venture@google.com, yuenn@google.com, benjaminfair@google.com, andi.shyti@kernel.org, andriy.shevchenko@linux.intel.com, wsa@kernel.org, rand.sec96@gmail.com, wsa+renesas@sang-engineering.com, warp5tw@gmail.com, tali.perry@nuvoton.com, Avi.Fishman@nuvoton.com, tomer.maimon@nuvoton.com, KWLIU@nuvoton.com, JJLIU0@nuvoton.com, kfting@nuvoton.com Cc: openbmc@lists.ozlabs.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 3/4] i2c: npcm: use i2c frequency table Date: Fri, 11 Oct 2024 13:52:30 +0800 Message-Id: <20241011055231.9826-4-kfting@nuvoton.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241011055231.9826-1-kfting@nuvoton.com> References: <20241011055231.9826-1-kfting@nuvoton.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Tyrone Ting Modify i2c frequency from table parameters for NPCM i2c modules. Supported frequencies are: 1. 100KHz 2. 400KHz 3. 1MHz The original equations were tested on a variety of chips and base clocks. Since we added devices that use higher frequencies of the module we saw that there is a mismatch between the equation and the actual results on the bus itself, measured on scope. Meanwhile, the equations were not accurate to begin with. They are an approximation of the ideal value. The ideal value is calculated per frequency of the core module. So instead of using the equations we did an optimization per module frequency, verified on a device. Most of the work was focused on the rise time of the SCL and SDA, which depends on external load of the bus and PU. Different PCB designs, or specifically to this case: the number and type of targets on the bus, impact the required values for the timing registers. Users can recalculate the numbers for each bus and get an even better optimization, but our users chose not to. We manually picked values per frequency that match the entire valid range of targets (from 1 to max number). Then we check against the AMR described in SMB spec and make sure that none of the values is exceeding. This process was led by the chip architect and included a lot of testing. Signed-off-by: Tyrone Ting Reviewed-by: Tali Perry --- drivers/i2c/busses/i2c-npcm7xx.c | 374 ++++++++++++++++++++++++------- 1 file changed, 288 insertions(+), 86 deletions(-) diff --git a/drivers/i2c/busses/i2c-npcm7xx.c b/drivers/i2c/busses/i2c-npcm= 7xx.c index 349492f114e7..fcecb098298f 100644 --- a/drivers/i2c/busses/i2c-npcm7xx.c +++ b/drivers/i2c/busses/i2c-npcm7xx.c @@ -263,6 +263,265 @@ static const int npcm_i2caddr[I2C_NUM_OWN_ADDR] =3D { #define I2C_FREQ_MIN_HZ 10000 #define I2C_FREQ_MAX_HZ I2C_MAX_FAST_MODE_PLUS_FREQ =20 +struct smb_timing_t { + u32 core_clk; + u8 hldt; + u8 dbcnt; + u16 sclfrq; + u8 scllt; + u8 sclht; + bool fast_mode; +}; + +static struct smb_timing_t smb_timing_100khz[] =3D { + { + .core_clk =3D 100000000, .hldt =3D 0x2A, .dbcnt =3D 0x4, + .sclfrq =3D 0xFB, .scllt =3D 0x0, .sclht =3D 0x0, + .fast_mode =3D false, + }, + { + .core_clk =3D 62500000, .hldt =3D 0x2A, .dbcnt =3D 0x1, + .sclfrq =3D 0x9D, .scllt =3D 0x0, .sclht =3D 0x0, + .fast_mode =3D false, + }, + { + .core_clk =3D 50000000, .hldt =3D 0x2A, .dbcnt =3D 0x1, + .sclfrq =3D 0x7E, .scllt =3D 0x0, .sclht =3D 0x0, + .fast_mode =3D false, + }, + { + .core_clk =3D 48000000, .hldt =3D 0x2A, .dbcnt =3D 0x1, + .sclfrq =3D 0x79, .scllt =3D 0x0, .sclht =3D 0x0, + .fast_mode =3D false, + }, + { + .core_clk =3D 40000000, .hldt =3D 0x2A, .dbcnt =3D 0x1, + .sclfrq =3D 0x65, .scllt =3D 0x0, .sclht =3D 0x0, + .fast_mode =3D false, + }, + { + .core_clk =3D 30000000, .hldt =3D 0x2A, .dbcnt =3D 0x1, + .sclfrq =3D 0x4C, .scllt =3D 0x0, .sclht =3D 0x0, + .fast_mode =3D false, + }, + { + .core_clk =3D 29000000, .hldt =3D 0x2A, .dbcnt =3D 0x1, + .sclfrq =3D 0x49, .scllt =3D 0x0, .sclht =3D 0x0, + .fast_mode =3D false, + }, + { + .core_clk =3D 26000000, .hldt =3D 0x2A, .dbcnt =3D 0x1, + .sclfrq =3D 0x42, .scllt =3D 0x0, .sclht =3D 0x0, + .fast_mode =3D false, + }, + { + .core_clk =3D 25000000, .hldt =3D 0x2A, .dbcnt =3D 0x1, + .sclfrq =3D 0x3F, .scllt =3D 0x0, .sclht =3D 0x0, + .fast_mode =3D false, + }, + { + .core_clk =3D 24000000, .hldt =3D 0x2A, .dbcnt =3D 0x1, + .sclfrq =3D 0x3D, .scllt =3D 0x0, .sclht =3D 0x0, + .fast_mode =3D false, + }, + { + .core_clk =3D 20000000, .hldt =3D 0x2A, .dbcnt =3D 0x1, + .sclfrq =3D 0x33, .scllt =3D 0x0, .sclht =3D 0x0, + .fast_mode =3D false, + }, + { + .core_clk =3D 16180000, .hldt =3D 0x2A, .dbcnt =3D 0x1, + .sclfrq =3D 0x29, .scllt =3D 0x0, .sclht =3D 0x0, + .fast_mode =3D false, + }, + { + .core_clk =3D 15000000, .hldt =3D 0x23, .dbcnt =3D 0x1, + .sclfrq =3D 0x26, .scllt =3D 0x0, .sclht =3D 0x0, + .fast_mode =3D false, + }, + { + .core_clk =3D 13000000, .hldt =3D 0x1D, .dbcnt =3D 0x1, + .sclfrq =3D 0x21, .scllt =3D 0x0, .sclht =3D 0x0, + .fast_mode =3D false, + }, + { + .core_clk =3D 12000000, .hldt =3D 0x1B, .dbcnt =3D 0x1, + .sclfrq =3D 0x1F, .scllt =3D 0x0, .sclht =3D 0x0, + .fast_mode =3D false, + }, + { + .core_clk =3D 10000000, .hldt =3D 0x18, .dbcnt =3D 0x1, + .sclfrq =3D 0x1A, .scllt =3D 0x0, .sclht =3D 0x0, + .fast_mode =3D false, + }, + { + .core_clk =3D 9000000, .hldt =3D 0x16, .dbcnt =3D 0x1, + .sclfrq =3D 0x17, .scllt =3D 0x0, .sclht =3D 0x0, + .fast_mode =3D false, + }, + { + .core_clk =3D 8090000, .hldt =3D 0x14, .dbcnt =3D 0x1, + .sclfrq =3D 0x15, .scllt =3D 0x0, .sclht =3D 0x0, + .fast_mode =3D false, + }, + { + .core_clk =3D 7500000, .hldt =3D 0x7, .dbcnt =3D 0x1, + .sclfrq =3D 0x13, .scllt =3D 0x0, .sclht =3D 0x0, + .fast_mode =3D false, + }, + { + .core_clk =3D 6500000, .hldt =3D 0xE, .dbcnt =3D 0x1, + .sclfrq =3D 0x11, .scllt =3D 0x0, .sclht =3D 0x0, + .fast_mode =3D false, + }, + { + .core_clk =3D 4000000, .hldt =3D 0x9, .dbcnt =3D 0x1, + .sclfrq =3D 0xB, .scllt =3D 0x0, .sclht =3D 0x0, + .fast_mode =3D false, + }, +}; + +static struct smb_timing_t smb_timing_400khz[] =3D { + { + .core_clk =3D 100000000, .hldt =3D 0x2A, .dbcnt =3D 0x3, + .sclfrq =3D 0x0, .scllt =3D 0x47, .sclht =3D 0x35, + .fast_mode =3D true, + }, + { + .core_clk =3D 62500000, .hldt =3D 0x2A, .dbcnt =3D 0x2, + .sclfrq =3D 0x0, .scllt =3D 0x2C, .sclht =3D 0x22, + .fast_mode =3D true, + }, + { + .core_clk =3D 50000000, .hldt =3D 0x21, .dbcnt =3D 0x1, + .sclfrq =3D 0x0, .scllt =3D 0x24, .sclht =3D 0x1B, + .fast_mode =3D true, + }, + { + .core_clk =3D 48000000, .hldt =3D 0x1E, .dbcnt =3D 0x1, + .sclfrq =3D 0x0, .scllt =3D 0x24, .sclht =3D 0x19, + .fast_mode =3D true, + }, + { + .core_clk =3D 40000000, .hldt =3D 0x1B, .dbcnt =3D 0x1, + .sclfrq =3D 0x0, .scllt =3D 0x1E, .sclht =3D 0x14, + .fast_mode =3D true, + }, + { + .core_clk =3D 33000000, .hldt =3D 0x15, .dbcnt =3D 0x1, + .sclfrq =3D 0x0, .scllt =3D 0x19, .sclht =3D 0x11, + .fast_mode =3D true, + }, + { + .core_clk =3D 30000000, .hldt =3D 0x15, .dbcnt =3D 0x1, + .sclfrq =3D 0x0, .scllt =3D 0x19, .sclht =3D 0xD, + .fast_mode =3D true, + }, + { + .core_clk =3D 29000000, .hldt =3D 0x11, .dbcnt =3D 0x1, + .sclfrq =3D 0x0, .scllt =3D 0x15, .sclht =3D 0x10, + .fast_mode =3D true, + }, + { + .core_clk =3D 26000000, .hldt =3D 0x10, .dbcnt =3D 0x1, + .sclfrq =3D 0x0, .scllt =3D 0x13, .sclht =3D 0xE, + .fast_mode =3D true, + }, + { + .core_clk =3D 25000000, .hldt =3D 0xF, .dbcnt =3D 0x1, + .sclfrq =3D 0x0, .scllt =3D 0x13, .sclht =3D 0xD, + .fast_mode =3D true, + }, + { + .core_clk =3D 24000000, .hldt =3D 0xD, .dbcnt =3D 0x1, + .sclfrq =3D 0x0, .scllt =3D 0x12, .sclht =3D 0xD, + .fast_mode =3D true, + }, + { + .core_clk =3D 20000000, .hldt =3D 0xB, .dbcnt =3D 0x1, + .sclfrq =3D 0x0, .scllt =3D 0xF, .sclht =3D 0xA, + .fast_mode =3D true, + }, + { + .core_clk =3D 16180000, .hldt =3D 0xA, .dbcnt =3D 0x1, + .sclfrq =3D 0x0, .scllt =3D 0xC, .sclht =3D 0x9, + .fast_mode =3D true, + }, + { + .core_clk =3D 15000000, .hldt =3D 0x9, .dbcnt =3D 0x1, + .sclfrq =3D 0x0, .scllt =3D 0xB, .sclht =3D 0x8, + .fast_mode =3D true, + }, + { + .core_clk =3D 13000000, .hldt =3D 0x7, .dbcnt =3D 0x1, + .sclfrq =3D 0x0, .scllt =3D 0xA, .sclht =3D 0x7, + .fast_mode =3D true, + }, + { + .core_clk =3D 12000000, .hldt =3D 0x7, .dbcnt =3D 0x1, + .sclfrq =3D 0x0, .scllt =3D 0xA, .sclht =3D 0x6, + .fast_mode =3D true, + }, + { + .core_clk =3D 10000000, .hldt =3D 0x6, .dbcnt =3D 0x1, + .sclfrq =3D 0x0, .scllt =3D 0x8, .sclht =3D 0x5, + .fast_mode =3D true, + }, +}; + +static struct smb_timing_t smb_timing_1000khz[] =3D { + { + .core_clk =3D 100000000, .hldt =3D 0x15, .dbcnt =3D 0x4, + .sclfrq =3D 0x0, .scllt =3D 0x1C, .sclht =3D 0x15, + .fast_mode =3D true, + }, + { + .core_clk =3D 62500000, .hldt =3D 0xF, .dbcnt =3D 0x3, + .sclfrq =3D 0x0, .scllt =3D 0x11, .sclht =3D 0xE, + .fast_mode =3D true, + }, + { + .core_clk =3D 50000000, .hldt =3D 0xA, .dbcnt =3D 0x2, + .sclfrq =3D 0x0, .scllt =3D 0xE, .sclht =3D 0xB, + .fast_mode =3D true, + }, + { + .core_clk =3D 48000000, .hldt =3D 0x9, .dbcnt =3D 0x2, + .sclfrq =3D 0x0, .scllt =3D 0xD, .sclht =3D 0xB, + .fast_mode =3D true, + }, + { + .core_clk =3D 41000000, .hldt =3D 0x9, .dbcnt =3D 0x2, + .sclfrq =3D 0x0, .scllt =3D 0xC, .sclht =3D 0x9, + .fast_mode =3D true, + }, + { + .core_clk =3D 40000000, .hldt =3D 0x8, .dbcnt =3D 0x2, + .sclfrq =3D 0x0, .scllt =3D 0xB, .sclht =3D 0x9, + .fast_mode =3D true, + }, + { + .core_clk =3D 33000000, .hldt =3D 0x7, .dbcnt =3D 0x1, + .sclfrq =3D 0x0, .scllt =3D 0xA, .sclht =3D 0x7, + .fast_mode =3D true, + }, + { + .core_clk =3D 25000000, .hldt =3D 0x4, .dbcnt =3D 0x1, + .sclfrq =3D 0x0, .scllt =3D 0x7, .sclht =3D 0x6, + .fast_mode =3D true, + }, + { + .core_clk =3D 24000000, .hldt =3D 0x7, .dbcnt =3D 0x1, + .sclfrq =3D 0x0, .scllt =3D 0x8, .sclht =3D 0x5, + .fast_mode =3D true, + }, + { + .core_clk =3D 20000000, .hldt =3D 0x4, .dbcnt =3D 0x1, + .sclfrq =3D 0x0, .scllt =3D 0x6, .sclht =3D 0x4, + .fast_mode =3D true, + }, +}; + struct npcm_i2c_data { u8 fifo_size; u32 segctl_init_val; @@ -1805,102 +2064,45 @@ static void npcm_i2c_recovery_init(struct i2c_adap= ter *_adap) */ static int npcm_i2c_init_clk(struct npcm_i2c *bus, u32 bus_freq_hz) { - u32 k1 =3D 0; - u32 k2 =3D 0; - u8 dbnct =3D 0; - u32 sclfrq =3D 0; - u8 hldt =3D 7; + struct smb_timing_t *smb_timing; + u8 scl_table_cnt =3D 0, table_size =3D 0; u8 fast_mode =3D 0; - u32 src_clk_khz; - u32 bus_freq_khz; =20 - src_clk_khz =3D bus->apb_clk / 1000; - bus_freq_khz =3D bus_freq_hz / 1000; bus->bus_freq =3D bus_freq_hz; =20 - /* 100KHz and below: */ - if (bus_freq_hz <=3D I2C_MAX_STANDARD_MODE_FREQ) { - sclfrq =3D src_clk_khz / (bus_freq_khz * 4); - - if (sclfrq < SCLFRQ_MIN || sclfrq > SCLFRQ_MAX) - return -EDOM; - - if (src_clk_khz >=3D 40000) - hldt =3D 17; - else if (src_clk_khz >=3D 12500) - hldt =3D 15; - else - hldt =3D 7; - } - - /* 400KHz: */ - else if (bus_freq_hz <=3D I2C_MAX_FAST_MODE_FREQ) { - sclfrq =3D 0; + switch (bus_freq_hz) { + case I2C_MAX_STANDARD_MODE_FREQ: + smb_timing =3D smb_timing_100khz; + table_size =3D ARRAY_SIZE(smb_timing_100khz); + break; + case I2C_MAX_FAST_MODE_FREQ: + smb_timing =3D smb_timing_400khz; + table_size =3D ARRAY_SIZE(smb_timing_400khz); fast_mode =3D I2CCTL3_400K_MODE; - - if (src_clk_khz < 7500) - /* 400KHZ cannot be supported for core clock < 7.5MHz */ - return -EDOM; - - else if (src_clk_khz >=3D 50000) { - k1 =3D 80; - k2 =3D 48; - hldt =3D 12; - dbnct =3D 7; - } - - /* Master or Slave with frequency > 25MHz */ - else if (src_clk_khz > 25000) { - hldt =3D clk_coef(src_clk_khz, 300) + 7; - k1 =3D clk_coef(src_clk_khz, 1600); - k2 =3D clk_coef(src_clk_khz, 900); - } - } - - /* 1MHz: */ - else if (bus_freq_hz <=3D I2C_MAX_FAST_MODE_PLUS_FREQ) { - sclfrq =3D 0; + break; + case I2C_MAX_FAST_MODE_PLUS_FREQ: + smb_timing =3D smb_timing_1000khz; + table_size =3D ARRAY_SIZE(smb_timing_1000khz); fast_mode =3D I2CCTL3_400K_MODE; - - /* 1MHZ cannot be supported for core clock < 24 MHz */ - if (src_clk_khz < 24000) - return -EDOM; - - k1 =3D clk_coef(src_clk_khz, 620); - k2 =3D clk_coef(src_clk_khz, 380); - - /* Core clk > 40 MHz */ - if (src_clk_khz > 40000) { - /* - * Set HLDT: - * SDA hold time: (HLDT-7) * T(CLK) >=3D 120 - * HLDT =3D 120/T(CLK) + 7 =3D 120 * FREQ(CLK) + 7 - */ - hldt =3D clk_coef(src_clk_khz, 120) + 7; - } else { - hldt =3D 7; - dbnct =3D 2; - } + break; + default: + return -EINVAL; } =20 - /* Frequency larger than 1 MHz is not supported */ - else - return -EINVAL; + for (scl_table_cnt =3D 0; scl_table_cnt < table_size; scl_table_cnt++) + if (bus->apb_clk >=3D smb_timing[scl_table_cnt].core_clk) + break; =20 - if (bus_freq_hz >=3D I2C_MAX_FAST_MODE_FREQ) { - k1 =3D round_up(k1, 2); - k2 =3D round_up(k2 + 1, 2); - if (k1 < SCLFRQ_MIN || k1 > SCLFRQ_MAX || - k2 < SCLFRQ_MIN || k2 > SCLFRQ_MAX) - return -EDOM; - } + if (scl_table_cnt =3D=3D table_size) + return -EINVAL; =20 /* write sclfrq value. bits [6:0] are in I2CCTL2 reg */ - iowrite8(FIELD_PREP(I2CCTL2_SCLFRQ6_0, sclfrq & 0x7F), + iowrite8(FIELD_PREP(I2CCTL2_SCLFRQ6_0, smb_timing[scl_table_cnt].sclfrq &= 0x7F), bus->reg + NPCM_I2CCTL2); =20 /* bits [8:7] are in I2CCTL3 reg */ - iowrite8(fast_mode | FIELD_PREP(I2CCTL3_SCLFRQ8_7, (sclfrq >> 7) & 0x3), + iowrite8(FIELD_PREP(I2CCTL3_SCLFRQ8_7, (smb_timing[scl_table_cnt].sclfrq = >> 7) & 0x3) | + fast_mode, bus->reg + NPCM_I2CCTL3); =20 /* Select Bank 0 to access NPCM_I2CCTL4/NPCM_I2CCTL5 */ @@ -1912,13 +2114,13 @@ static int npcm_i2c_init_clk(struct npcm_i2c *bus, = u32 bus_freq_hz) * k1 =3D 2 * SCLLT7-0 -> Low Time =3D k1 / 2 * k2 =3D 2 * SCLLT7-0 -> High Time =3D k2 / 2 */ - iowrite8(k1 / 2, bus->reg + NPCM_I2CSCLLT); - iowrite8(k2 / 2, bus->reg + NPCM_I2CSCLHT); + iowrite8(smb_timing[scl_table_cnt].scllt, bus->reg + NPCM_I2CSCLLT); + iowrite8(smb_timing[scl_table_cnt].sclht, bus->reg + NPCM_I2CSCLHT); =20 - iowrite8(dbnct, bus->reg + NPCM_I2CCTL5); + iowrite8(smb_timing[scl_table_cnt].dbcnt, bus->reg + NPCM_I2CCTL5); } =20 - iowrite8(hldt, bus->reg + NPCM_I2CCTL4); + iowrite8(smb_timing[scl_table_cnt].hldt, bus->reg + NPCM_I2CCTL4); =20 /* Return to Bank 1, and stay there by default: */ npcm_i2c_select_bank(bus, I2C_BANK_1); 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[2001:b400:e38a:6880:f424:8486:7476:9f9d]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c8bc13394sm17764775ad.108.2024.10.10.22.52.55 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 Oct 2024 22:52:55 -0700 (PDT) From: Tyrone Ting X-Google-Original-From: Tyrone Ting To: avifishman70@gmail.com, tmaimon77@gmail.com, tali.perry1@gmail.com, venture@google.com, yuenn@google.com, benjaminfair@google.com, andi.shyti@kernel.org, andriy.shevchenko@linux.intel.com, wsa@kernel.org, rand.sec96@gmail.com, wsa+renesas@sang-engineering.com, warp5tw@gmail.com, tali.perry@nuvoton.com, Avi.Fishman@nuvoton.com, tomer.maimon@nuvoton.com, KWLIU@nuvoton.com, JJLIU0@nuvoton.com, kfting@nuvoton.com Cc: openbmc@lists.ozlabs.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, Charles Boyer , Vivekanand Veeracholan Subject: [PATCH v6 4/4] i2c: npcm: Enable slave in eob interrupt Date: Fri, 11 Oct 2024 13:52:31 +0800 Message-Id: <20241011055231.9826-5-kfting@nuvoton.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241011055231.9826-1-kfting@nuvoton.com> References: <20241011055231.9826-1-kfting@nuvoton.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Charles Boyer Nuvoton slave enable was in user space API call master_xfer, so it is subject to delays from the OS scheduler. If the BMC is not enabled for slave mode in time for master to send response, then it will NAK the address match. Then the PLDM request timeout occurs. If the slave enable is moved to the EOB interrupt service routine, then the BMC can be ready in slave mode by the time it needs to receive a response. Signed-off-by: Charles Boyer Signed-off-by: Vivekanand Veeracholan Signed-off-by: Tyrone Ting Reviewed-by: Tali Perry --- drivers/i2c/busses/i2c-npcm7xx.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/i2c/busses/i2c-npcm7xx.c b/drivers/i2c/busses/i2c-npcm= 7xx.c index fcecb098298f..55348308b992 100644 --- a/drivers/i2c/busses/i2c-npcm7xx.c +++ b/drivers/i2c/busses/i2c-npcm7xx.c @@ -1925,6 +1925,12 @@ static int npcm_i2c_int_master_handler(struct npcm_i= 2c *bus) (FIELD_GET(NPCM_I2CCST3_EO_BUSY, ioread8(bus->reg + NPCM_I2CCST3)))) { npcm_i2c_irq_handle_eob(bus); +#if IS_ENABLED(CONFIG_I2C_SLAVE) + /* reenable slave if it was enabled */ + if (bus->slave) + iowrite8((bus->slave->addr & 0x7F) | NPCM_I2CADDR_SAEN, + bus->reg + NPCM_I2CADDR1); +#endif return 0; } =20 --=20 2.34.1