From nobody Wed Nov 27 12:38:36 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F09C83232; Fri, 11 Oct 2024 00:07:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728605250; cv=none; b=QLuDIgVnEu72UoUBzvUMhCXoaS2Btwsi3ubTz22OEacGRPv/s24AJxC2DDEv9DzuWl8xLqMA+kTc4eDLNLz2g+D+U/Bqd4cive7ZRlaFCNfIGnib2xXtG7Dy3xsXzDuOuDzV5oxttABHtX40nGWMiT5Vimd557Jf2I3VKeleMvc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728605250; c=relaxed/simple; bh=Kp5ddds6Gc1T8ofGoRt/Ck6ZScfTXnzSZienvxMHqq8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=KXoNsj4RdJIYSCQ9XqJ9+aMlYrikWjwHKmxT+x6Bo1hXCMEN4U1VHmvsKmPMfJoiecrjLLN6a3XYPkPVt4hrQKji4Zl7oMQ2IDgYEOJT9gs+L5Dx5tSU3/Rt/xy6xLeSo7gMPmqlLUJbpgHIV+xy0c/CWUs/owyf5rl+kdd/GQY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=hbwygdPK; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="hbwygdPK" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49ACiZVs009190; Fri, 11 Oct 2024 00:07:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= CIiOO9bHFnAQkxDw9TUjFKgKhWCq4HlRtM5F6BZuU9Q=; b=hbwygdPK8d++JQGw 31PhFYshcEU0pFrDUnWoh5NN7VZKf1VVvcEK1enoTSKjbkLfwvYXQgCWQ3Nocao+ +Rs20WKKyNdIFXnqBRf4+ICeK3JG33zK6z9/8IExC5WofjGgvYMqRICQdDTQ3UM+ ViuvG+Ex8nG06GkpgarM+RRNA0QKoSNAqcWUWBu4+MWK4csCSJ0s3IbnfQ5OCFu0 kiWndYASEUUKOe5+hm+L5RgZHXjQYD4vEa/1E2xNZ9wGRfZU+ilnuTDEh1L/ix+X lhZZMLofzm+rgBItuJ1bq2U/5O1UP9EeLppgiO76eyogaAvoLBQ8jpVWopwCRIvx J0JnUw== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 425tn150vs-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 11 Oct 2024 00:07:06 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49B075oi008755 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 11 Oct 2024 00:07:05 GMT Received: from hu-wcheng-lv.qualcomm.com (10.49.16.6) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 10 Oct 2024 17:07:05 -0700 From: Wesley Cheng To: , , , , , , , , , , , , , , CC: , , , , , , , , Wesley Cheng Subject: [PATCH v28 05/32] usb: host: xhci-mem: Cleanup pending secondary event ring events Date: Thu, 10 Oct 2024 17:05:54 -0700 Message-ID: <20241011000650.2585600-10-quic_wcheng@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241011000650.2585600-1-quic_wcheng@quicinc.com> References: <20241011000650.2585600-1-quic_wcheng@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: pT8MVpdJ2CYcmlBRyMTcxT0xtGbz191F X-Proofpoint-GUID: pT8MVpdJ2CYcmlBRyMTcxT0xtGbz191F X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 mlxlogscore=960 impostorscore=0 spamscore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 malwarescore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410100159 Content-Type: text/plain; charset="utf-8" As part of xHCI bus suspend, the xHCI is halted. However, if there are pending events in the secondary event ring, it is observed that the xHCI controller stops responding to further commands upon host or device initiated bus resume. Iterate through all pending events and update the dequeue pointer to the beginning of the event ring. Signed-off-by: Wesley Cheng --- drivers/usb/host/xhci-mem.c | 7 ++++++- drivers/usb/host/xhci-ring.c | 37 +++++++++++++++++++++++++++++++++--- drivers/usb/host/xhci.c | 2 +- drivers/usb/host/xhci.h | 7 +++++++ 4 files changed, 48 insertions(+), 5 deletions(-) diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c index a25576f27e66..5e022ce3a8fe 100644 --- a/drivers/usb/host/xhci-mem.c +++ b/drivers/usb/host/xhci-mem.c @@ -1816,7 +1816,7 @@ xhci_remove_interrupter(struct xhci_hcd *xhci, struct= xhci_interrupter *ir) tmp &=3D ERST_SIZE_MASK; writel(tmp, &ir->ir_set->erst_size); =20 - xhci_write_64(xhci, ERST_EHB, &ir->ir_set->erst_dequeue); + xhci_update_erst_dequeue(xhci, ir, true); } } =20 @@ -1859,6 +1859,11 @@ void xhci_remove_secondary_interrupter(struct usb_hc= d *hcd, struct xhci_interrup return; } =20 + /* + * Cleanup secondary interrupter to ensure there are no pending events. + * This also updates event ring dequeue pointer back to the start. + */ + xhci_skip_sec_intr_events(xhci, ir->event_ring, ir); intr_num =3D ir->intr_num; =20 xhci_remove_interrupter(xhci, ir); diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index 74bdc94d863b..b7009aee4130 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c @@ -3012,9 +3012,9 @@ static int xhci_handle_event_trb(struct xhci_hcd *xhc= i, struct xhci_interrupter * - When all events have finished * - To avoid "Event Ring Full Error" condition */ -static void xhci_update_erst_dequeue(struct xhci_hcd *xhci, - struct xhci_interrupter *ir, - bool clear_ehb) +void xhci_update_erst_dequeue(struct xhci_hcd *xhci, + struct xhci_interrupter *ir, + bool clear_ehb) { u64 temp_64; dma_addr_t deq; @@ -3112,6 +3112,37 @@ static int xhci_handle_events(struct xhci_hcd *xhci,= struct xhci_interrupter *ir return 0; } =20 +/* + * Move the event ring dequeue pointer to skip events kept in the secondary + * event ring. This is used to ensure that pending events in the ring are + * acknowledged, so the xHCI HCD can properly enter suspend/resume. The + * secondary ring is typically maintained by an external component. + */ +void xhci_skip_sec_intr_events(struct xhci_hcd *xhci, + struct xhci_ring *ring, struct xhci_interrupter *ir) +{ + union xhci_trb *current_trb; + u64 erdp_reg; + dma_addr_t deq; + + /* disable irq, ack pending interrupt and ack all pending events */ + xhci_disable_interrupter(ir); + + /* last acked event trb is in erdp reg */ + erdp_reg =3D xhci_read_64(xhci, &ir->ir_set->erst_dequeue); + deq =3D (dma_addr_t)(erdp_reg & ERST_PTR_MASK); + if (!deq) { + xhci_err(xhci, "event ring handling not required\n"); + return; + } + + current_trb =3D ir->event_ring->dequeue; + /* read cycle state of the last acked trb to find out CCS */ + ring->cycle_state =3D le32_to_cpu(current_trb->event_cmd.flags) & TRB_CYC= LE; + + xhci_handle_events(xhci, ir); +} + /* * xHCI spec says we can get an interrupt, and if the HC has an error cond= ition, * we might get bad data out of the event ring. Section 4.10.2.7 has a li= st of diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index 8d7566e33faf..ed8853accab3 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -333,7 +333,7 @@ static int xhci_enable_interrupter(struct xhci_interrup= ter *ir) return 0; } =20 -static int xhci_disable_interrupter(struct xhci_interrupter *ir) +int xhci_disable_interrupter(struct xhci_interrupter *ir) { u32 iman; =20 diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index 503784345787..e37d27190e3c 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h @@ -1836,6 +1836,9 @@ xhci_create_secondary_interrupter(struct usb_hcd *hcd= , unsigned int segs, u32 imod_interval); void xhci_remove_secondary_interrupter(struct usb_hcd *hcd, struct xhci_interrupter *ir); +void xhci_skip_sec_intr_events(struct xhci_hcd *xhci, + struct xhci_ring *ring, + struct xhci_interrupter *ir); =20 /* xHCI host controller glue */ typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *); @@ -1875,6 +1878,7 @@ int xhci_alloc_tt_info(struct xhci_hcd *xhci, struct usb_tt *tt, gfp_t mem_flags); int xhci_set_interrupter_moderation(struct xhci_interrupter *ir, u32 imod_interval); +int xhci_disable_interrupter(struct xhci_interrupter *ir); =20 /* xHCI ring, segment, TRB, and TD functions */ dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *= trb); @@ -1924,6 +1928,9 @@ void inc_deq(struct xhci_hcd *xhci, struct xhci_ring = *ring); unsigned int count_trbs(u64 addr, u64 len); int xhci_stop_endpoint_sync(struct xhci_hcd *xhci, struct xhci_virt_ep *ep, int suspend, gfp_t gfp_flags); +void xhci_update_erst_dequeue(struct xhci_hcd *xhci, + struct xhci_interrupter *ir, + bool clear_ehb); =20 /* xHCI roothub code */ void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,