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Reviewed-by: Krzysztof Kozlowski Signed-off-by: Taniya Das --- .../bindings/clock/qcom,sa8775p-videocc.yaml | 62 ++++++++++++++++++= ++++ include/dt-bindings/clock/qcom,sa8775p-videocc.h | 47 ++++++++++++++++ 2 files changed, 109 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.y= aml b/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..928131bff4c1954871cd4067ba3= 31d0cc7233307 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sa8775p-videocc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Video Clock & Reset Controller on SA8775P + +maintainers: + - Taniya Das + +description: | + Qualcomm video clock control module provides the clocks, resets and power + domains on SA8775P. + + See also: include/dt-bindings/clock/qcom,sa8775p-videocc.h + +properties: + compatible: + enum: + - qcom,sa8775p-videocc + + clocks: + items: + - description: Video AHB clock from GCC + - description: Board XO source + - description: Board active XO source + - description: Sleep Clock source + + power-domains: + maxItems: 1 + description: MMCX power domain + +required: + - compatible + - clocks + - power-domains + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + videocc: clock-controller@abf0000 { + compatible =3D "qcom,sa8775p-videocc"; + reg =3D <0x0abf0000 0x10000>; + clocks =3D <&gcc GCC_VIDEO_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains =3D <&rpmhpd SA8775P_MMCX>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,sa8775p-videocc.h b/include/dt-= bindings/clock/qcom,sa8775p-videocc.h new file mode 100644 index 0000000000000000000000000000000000000000..e6325f68c31733f46e5d33281df= 86902e1f75095 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sa8775p-videocc.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_SA8775P_VIDEO_CC_H +#define _DT_BINDINGS_CLK_QCOM_SA8775P_VIDEO_CC_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_AHB_CLK 0 +#define VIDEO_CC_AHB_CLK_SRC 1 +#define VIDEO_CC_MVS0_CLK 2 +#define VIDEO_CC_MVS0_CLK_SRC 3 +#define VIDEO_CC_MVS0_DIV_CLK_SRC 4 +#define VIDEO_CC_MVS0C_CLK 5 +#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 6 +#define VIDEO_CC_MVS1_CLK 7 +#define VIDEO_CC_MVS1_CLK_SRC 8 +#define VIDEO_CC_MVS1_DIV_CLK_SRC 9 +#define VIDEO_CC_MVS1C_CLK 10 +#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 11 +#define VIDEO_CC_PLL_LOCK_MONITOR_CLK 12 +#define VIDEO_CC_SLEEP_CLK 13 +#define VIDEO_CC_SLEEP_CLK_SRC 14 +#define VIDEO_CC_SM_DIV_CLK_SRC 15 +#define VIDEO_CC_SM_OBS_CLK 16 +#define VIDEO_CC_XO_CLK 17 +#define VIDEO_CC_XO_CLK_SRC 18 +#define VIDEO_PLL0 19 +#define VIDEO_PLL1 20 + +/* VIDEO_CC power domains */ +#define VIDEO_CC_MVS0C_GDSC 0 +#define VIDEO_CC_MVS0_GDSC 1 +#define VIDEO_CC_MVS1C_GDSC 2 +#define VIDEO_CC_MVS1_GDSC 3 + +/* VIDEO_CC resets */ +#define VIDEO_CC_INTERFACE_BCR 0 +#define VIDEO_CC_MVS0_BCR 1 +#define VIDEO_CC_MVS0C_CLK_ARES 2 +#define VIDEO_CC_MVS0C_BCR 3 +#define VIDEO_CC_MVS1_BCR 4 +#define VIDEO_CC_MVS1C_CLK_ARES 5 +#define VIDEO_CC_MVS1C_BCR 6 + +#endif --=20 2.45.2 From nobody Wed Nov 27 08:41:06 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C8F81E9061; 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Reviewed-by: Jagadeesh Kona Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 11 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/videocc-sa8775p.c | 576 +++++++++++++++++++++++++++++++++= ++++ 3 files changed, 588 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 30eb8236c9d80071a87e0332cfac7b667a08824a..bd0f14dad02d2acdfc5c1ccc84b= bf3f747ff98f6 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -1189,6 +1189,17 @@ config SM_TCSRCC_8650 Support for the TCSR clock controller on SM8650 devices. Say Y if you want to use peripheral devices such as SD/UFS. =20 +config SA_VIDEOCC_8775P + tristate "SA8775P Video Clock Controller" + depends on ARM64 || COMPILE_TEST + select SA_GCC_8775P + select QCOM_GDSC + help + Support for the video clock controller on Qualcomm Technologies, Inc. + SA8775P devices. + Say Y if you want to support video devices and functionality such as + video encode/decode. + config SM_VIDEOCC_7150 tristate "SM7150 Video Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 2b378667a63ff6eca843d7bef638a5422d35c3d3..548c124c0f990353bd7b8b66e41= b0dbbbf3a04e3 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -82,6 +82,7 @@ obj-$(CONFIG_SC_DISPCC_7280) +=3D dispcc-sc7280.o obj-$(CONFIG_SC_DISPCC_8280XP) +=3D dispcc-sc8280xp.o obj-$(CONFIG_SA_GCC_8775P) +=3D gcc-sa8775p.o obj-$(CONFIG_SA_GPUCC_8775P) +=3D gpucc-sa8775p.o +obj-$(CONFIG_SA_VIDEOCC_8775P) +=3D videocc-sa8775p.o obj-$(CONFIG_SC_GCC_7180) +=3D gcc-sc7180.o obj-$(CONFIG_SC_GCC_7280) +=3D gcc-sc7280.o obj-$(CONFIG_SC_GCC_8180X) +=3D gcc-sc8180x.o diff --git a/drivers/clk/qcom/videocc-sa8775p.c b/drivers/clk/qcom/videocc-= sa8775p.c new file mode 100644 index 0000000000000000000000000000000000000000..bf5de411fd5d634f84a924a78a4= e3aa00b72f90a --- /dev/null +++ b/drivers/clk/qcom/videocc-sa8775p.c @@ -0,0 +1,576 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_IFACE, + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_BI_TCXO_AO, + P_SLEEP_CLK, + P_VIDEO_PLL0_OUT_MAIN, + P_VIDEO_PLL1_OUT_MAIN, +}; + +static const struct pll_vco lucid_evo_vco[] =3D { + { 249600000, 2020000000, 0 }, +}; + +static const struct alpha_pll_config video_pll0_config =3D { + .l =3D 0x39, + .alpha =3D 0x3000, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x32aa299c, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00400805, +}; + +static struct clk_alpha_pll video_pll0 =3D { + .offset =3D 0x0, + .vco_table =3D lucid_evo_vco, + .num_vco =3D ARRAY_SIZE(lucid_evo_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct alpha_pll_config video_pll1_config =3D { + .l =3D 0x39, + .alpha =3D 0x3000, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x32aa299c, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00400805, +}; + +static struct clk_alpha_pll video_pll1 =3D { + .offset =3D 0x1000, + .vco_table =3D lucid_evo_vco, + .num_vco =3D ARRAY_SIZE(lucid_evo_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_pll1", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct parent_map video_cc_parent_map_0_ao[] =3D { + { P_BI_TCXO_AO, 0 }, +}; + +static const struct clk_parent_data video_cc_parent_data_0_ao[] =3D { + { .index =3D DT_BI_TCXO_AO }, +}; + +static const struct parent_map video_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_VIDEO_PLL0_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data video_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &video_pll0.clkr.hw }, +}; + +static const struct parent_map video_cc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_VIDEO_PLL1_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data video_cc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &video_pll1.clkr.hw }, +}; + +static const struct parent_map video_cc_parent_map_3[] =3D { + { P_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data video_cc_parent_data_3[] =3D { + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] =3D { + F(19200000, P_BI_TCXO_AO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_ahb_clk_src =3D { + .cmd_rcgr =3D 0x8030, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_0_ao, + .freq_tbl =3D ftbl_video_cc_ahb_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_ahb_clk_src", + .parent_data =3D video_cc_parent_data_0_ao, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_0_ao), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] =3D { + F(1098000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), + F(1332000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), + F(1599000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), + F(1680000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs0_clk_src =3D { + .cmd_rcgr =3D 0x8000, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_1, + .freq_tbl =3D ftbl_video_cc_mvs0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_clk_src", + .parent_data =3D video_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] =3D { + F(1098000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0), + F(1332000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0), + F(1600000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0), + F(1800000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs1_clk_src =3D { + .cmd_rcgr =3D 0x8018, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_2, + .freq_tbl =3D ftbl_video_cc_mvs1_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs1_clk_src", + .parent_data =3D video_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] =3D { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_sleep_clk_src =3D { + .cmd_rcgr =3D 0x812c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_3, + .freq_tbl =3D ftbl_video_cc_sleep_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_sleep_clk_src", + .parent_data =3D video_cc_parent_data_3, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 video_cc_xo_clk_src =3D { + .cmd_rcgr =3D 0x8110, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_0_ao, + .freq_tbl =3D ftbl_video_cc_ahb_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_xo_clk_src", + .parent_data =3D video_cc_parent_data_0_ao, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_0_ao), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs0_div_clk_src =3D { + .reg =3D 0x80b8, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src =3D { + .reg =3D 0x806c, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_div2_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs1_div_clk_src =3D { + .reg =3D 0x80dc, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs1_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src =3D { + .reg =3D 0x8094, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs1c_div2_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div video_cc_sm_div_clk_src =3D { + .reg =3D 0x8108, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_sm_div_clk_src", + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch video_cc_mvs0_clk =3D { + .halt_reg =3D 0x80b0, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x80b0, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x80b0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_clk =3D { + .halt_reg =3D 0x8064, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8064, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0c_div2_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs1_clk =3D { + .halt_reg =3D 0x80d4, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x80d4, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x80d4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs1_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs1c_clk =3D { + .halt_reg =3D 0x808c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x808c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs1c_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs1c_div2_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_pll_lock_monitor_clk =3D { + .halt_reg =3D 0x9000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_pll_lock_monitor_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_sm_obs_clk =3D { + .halt_reg =3D 0x810c, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0x810c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_sm_obs_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_sm_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc video_cc_mvs0c_gdsc =3D { + .gdscr =3D 0x804c, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x6, + .pd =3D { + .name =3D "video_cc_mvs0c_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D RETAIN_FF_ENABLE | POLL_CFG_GDSCR, +}; + +static struct gdsc video_cc_mvs0_gdsc =3D { + .gdscr =3D 0x809c, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x6, + .pd =3D { + .name =3D "video_cc_mvs0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .parent =3D &video_cc_mvs0c_gdsc.pd, + .flags =3D RETAIN_FF_ENABLE | POLL_CFG_GDSCR | HW_CTRL_TRIGGER, +}; + +static struct gdsc video_cc_mvs1c_gdsc =3D { + .gdscr =3D 0x8074, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x6, + .pd =3D { + .name =3D "video_cc_mvs1c_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D RETAIN_FF_ENABLE | POLL_CFG_GDSCR, +}; + +static struct gdsc video_cc_mvs1_gdsc =3D { + .gdscr =3D 0x80c0, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x6, + .pd =3D { + .name =3D "video_cc_mvs1_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .parent =3D &video_cc_mvs1c_gdsc.pd, + .flags =3D RETAIN_FF_ENABLE | POLL_CFG_GDSCR | HW_CTRL_TRIGGER, +}; + +static struct clk_regmap *video_cc_sa8775p_clocks[] =3D { + [VIDEO_CC_AHB_CLK_SRC] =3D &video_cc_ahb_clk_src.clkr, + [VIDEO_CC_MVS0_CLK] =3D &video_cc_mvs0_clk.clkr, + [VIDEO_CC_MVS0_CLK_SRC] =3D &video_cc_mvs0_clk_src.clkr, + [VIDEO_CC_MVS0_DIV_CLK_SRC] =3D &video_cc_mvs0_div_clk_src.clkr, + [VIDEO_CC_MVS0C_CLK] =3D &video_cc_mvs0c_clk.clkr, + [VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] =3D &video_cc_mvs0c_div2_div_clk_src.cl= kr, + [VIDEO_CC_MVS1_CLK] =3D &video_cc_mvs1_clk.clkr, + [VIDEO_CC_MVS1_CLK_SRC] =3D &video_cc_mvs1_clk_src.clkr, + [VIDEO_CC_MVS1_DIV_CLK_SRC] =3D &video_cc_mvs1_div_clk_src.clkr, + [VIDEO_CC_MVS1C_CLK] =3D &video_cc_mvs1c_clk.clkr, + [VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] =3D &video_cc_mvs1c_div2_div_clk_src.cl= kr, + [VIDEO_CC_PLL_LOCK_MONITOR_CLK] =3D &video_cc_pll_lock_monitor_clk.clkr, + [VIDEO_CC_SLEEP_CLK_SRC] =3D &video_cc_sleep_clk_src.clkr, + [VIDEO_CC_SM_DIV_CLK_SRC] =3D &video_cc_sm_div_clk_src.clkr, + [VIDEO_CC_SM_OBS_CLK] =3D &video_cc_sm_obs_clk.clkr, + [VIDEO_CC_XO_CLK_SRC] =3D &video_cc_xo_clk_src.clkr, + [VIDEO_PLL0] =3D &video_pll0.clkr, + [VIDEO_PLL1] =3D &video_pll1.clkr, +}; + +static struct gdsc *video_cc_sa8775p_gdscs[] =3D { + [VIDEO_CC_MVS0_GDSC] =3D &video_cc_mvs0_gdsc, + [VIDEO_CC_MVS0C_GDSC] =3D &video_cc_mvs0c_gdsc, + [VIDEO_CC_MVS1_GDSC] =3D &video_cc_mvs1_gdsc, + [VIDEO_CC_MVS1C_GDSC] =3D &video_cc_mvs1c_gdsc, +}; + +static const struct qcom_reset_map video_cc_sa8775p_resets[] =3D { + [VIDEO_CC_INTERFACE_BCR] =3D { 0x80e8 }, + [VIDEO_CC_MVS0_BCR] =3D { 0x8098 }, + [VIDEO_CC_MVS0C_CLK_ARES] =3D { 0x8064, 2 }, + [VIDEO_CC_MVS0C_BCR] =3D { 0x8048 }, + [VIDEO_CC_MVS1_BCR] =3D { 0x80bc }, + [VIDEO_CC_MVS1C_CLK_ARES] =3D { 0x808c, 2 }, + [VIDEO_CC_MVS1C_BCR] =3D { 0x8070 }, +}; + +static const struct regmap_config video_cc_sa8775p_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xb000, + .fast_io =3D true, +}; + +static struct qcom_cc_desc video_cc_sa8775p_desc =3D { + .config =3D &video_cc_sa8775p_regmap_config, + .clks =3D video_cc_sa8775p_clocks, + .num_clks =3D ARRAY_SIZE(video_cc_sa8775p_clocks), + .resets =3D video_cc_sa8775p_resets, + .num_resets =3D ARRAY_SIZE(video_cc_sa8775p_resets), + .gdscs =3D video_cc_sa8775p_gdscs, + .num_gdscs =3D ARRAY_SIZE(video_cc_sa8775p_gdscs), +}; + +static const struct of_device_id video_cc_sa8775p_match_table[] =3D { + { .compatible =3D "qcom,sa8775p-videocc" }, + { } +}; +MODULE_DEVICE_TABLE(of, video_cc_sa8775p_match_table); + +static int video_cc_sa8775p_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + ret =3D devm_pm_runtime_enable(&pdev->dev); + if (ret) + return ret; + + ret =3D pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; + + regmap =3D qcom_cc_map(pdev, &video_cc_sa8775p_desc); + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); + return PTR_ERR(regmap); + } + + clk_lucid_evo_pll_configure(&video_pll0, regmap, &video_pll0_config); + clk_lucid_evo_pll_configure(&video_pll1, regmap, &video_pll1_config); + + /* Keep some clocks always enabled */ + qcom_branch_set_clk_en(regmap, 0x80ec); /* VIDEO_CC_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x8144); /* VIDEO_CC_SLEEP_CLK */ + qcom_branch_set_clk_en(regmap, 0x8128); /* VIDEO_CC_XO_CLK */ + + ret =3D qcom_cc_really_probe(&pdev->dev, &video_cc_sa8775p_desc, regmap); + + pm_runtime_put(&pdev->dev); + + return ret; +} + +static struct platform_driver video_cc_sa8775p_driver =3D { + .probe =3D video_cc_sa8775p_probe, + .driver =3D { + .name =3D "videocc-sa8775p", + .of_match_table =3D video_cc_sa8775p_match_table, + }, +}; + +module_platform_driver(video_cc_sa8775p_driver); + +MODULE_DESCRIPTION("QTI VIDEOCC SA8775P Driver"); +MODULE_LICENSE("GPL"); --=20 2.45.2 From nobody Wed Nov 27 08:41:06 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC4EA1EABA1; Thu, 10 Oct 2024 18:59:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728586756; cv=none; b=Z+C8ZB2BeVenNujjvaP9jpMUUzoRQC8OMqJmKB/5950kl0lICJrPt9elNSY1vCvaRlXySL0DMhuPjWBXwhsSlO8z5Zi38mtNT5YRGqQztxmcUhJFszBOAobx69PONslbimLf9Ig3PrH6hF3/Lc33MRIQ+uYULA0IQk7HVZqIH7w= ARC-Message-Signature: i=1; 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Reviewed-by: Krzysztof Kozlowski Signed-off-by: Taniya Das --- .../bindings/clock/qcom,sa8775p-camcc.yaml | 62 ++++++++++++ include/dt-bindings/clock/qcom,sa8775p-camcc.h | 108 +++++++++++++++++= ++++ 2 files changed, 170 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yam= l b/Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..36a60d8f5ae3a5e0d86219d0329= 1403f8029772d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sa8775p-camcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera Clock & Reset Controller on SA8775P + +maintainers: + - Taniya Das + +description: | + Qualcomm camera clock control module provides the clocks, resets and pow= er + domains on SA8775p. + + See also: include/dt-bindings/clock/qcom,sa8775p-camcc.h + +properties: + compatible: + enum: + - qcom,sa8775p-camcc + + clocks: + items: + - description: Camera AHB clock from GCC + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + + power-domains: + maxItems: 1 + description: MMCX power domain + +required: + - compatible + - clocks + - power-domains + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + clock-controller@ade0000 { + compatible =3D "qcom,sa8775p-camcc"; + reg =3D <0x0ade0000 0x20000>; + clocks =3D <&gcc GCC_CAMERA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains =3D <&rpmhpd SA8775P_MMCX>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,sa8775p-camcc.h b/include/dt-bi= ndings/clock/qcom,sa8775p-camcc.h new file mode 100644 index 0000000000000000000000000000000000000000..38531acd699fe82a3384451c509= cf8f79d3a8d80 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sa8775p-camcc.h @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_SA8775P_CAM_CC_H +#define _DT_BINDINGS_CLK_QCOM_SA8775P_CAM_CC_H + +/* CAM_CC clocks */ +#define CAM_CC_CAMNOC_AXI_CLK 0 +#define CAM_CC_CAMNOC_AXI_CLK_SRC 1 +#define CAM_CC_CAMNOC_DCD_XO_CLK 2 +#define CAM_CC_CAMNOC_XO_CLK 3 +#define CAM_CC_CCI_0_CLK 4 +#define CAM_CC_CCI_0_CLK_SRC 5 +#define CAM_CC_CCI_1_CLK 6 +#define CAM_CC_CCI_1_CLK_SRC 7 +#define CAM_CC_CCI_2_CLK 8 +#define CAM_CC_CCI_2_CLK_SRC 9 +#define CAM_CC_CCI_3_CLK 10 +#define CAM_CC_CCI_3_CLK_SRC 11 +#define CAM_CC_CORE_AHB_CLK 12 +#define CAM_CC_CPAS_AHB_CLK 13 +#define CAM_CC_CPAS_FAST_AHB_CLK 14 +#define CAM_CC_CPAS_IFE_0_CLK 15 +#define CAM_CC_CPAS_IFE_1_CLK 16 +#define CAM_CC_CPAS_IFE_LITE_CLK 17 +#define CAM_CC_CPAS_IPE_CLK 18 +#define CAM_CC_CPAS_SFE_LITE_0_CLK 19 +#define CAM_CC_CPAS_SFE_LITE_1_CLK 20 +#define CAM_CC_CPHY_RX_CLK_SRC 21 +#define CAM_CC_CSI0PHYTIMER_CLK 22 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 23 +#define CAM_CC_CSI1PHYTIMER_CLK 24 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 25 +#define CAM_CC_CSI2PHYTIMER_CLK 26 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC 27 +#define CAM_CC_CSI3PHYTIMER_CLK 28 +#define CAM_CC_CSI3PHYTIMER_CLK_SRC 29 +#define CAM_CC_CSID_CLK 30 +#define CAM_CC_CSID_CLK_SRC 31 +#define CAM_CC_CSID_CSIPHY_RX_CLK 32 +#define CAM_CC_CSIPHY0_CLK 33 +#define CAM_CC_CSIPHY1_CLK 34 +#define CAM_CC_CSIPHY2_CLK 35 +#define CAM_CC_CSIPHY3_CLK 36 +#define CAM_CC_FAST_AHB_CLK_SRC 37 +#define CAM_CC_GDSC_CLK 38 +#define CAM_CC_ICP_AHB_CLK 39 +#define CAM_CC_ICP_CLK 40 +#define CAM_CC_ICP_CLK_SRC 41 +#define CAM_CC_IFE_0_CLK 42 +#define CAM_CC_IFE_0_CLK_SRC 43 +#define CAM_CC_IFE_0_FAST_AHB_CLK 44 +#define CAM_CC_IFE_1_CLK 45 +#define CAM_CC_IFE_1_CLK_SRC 46 +#define CAM_CC_IFE_1_FAST_AHB_CLK 47 +#define CAM_CC_IFE_LITE_AHB_CLK 48 +#define CAM_CC_IFE_LITE_CLK 49 +#define CAM_CC_IFE_LITE_CLK_SRC 50 +#define CAM_CC_IFE_LITE_CPHY_RX_CLK 51 +#define CAM_CC_IFE_LITE_CSID_CLK 52 +#define CAM_CC_IFE_LITE_CSID_CLK_SRC 53 +#define CAM_CC_IPE_AHB_CLK 54 +#define CAM_CC_IPE_CLK 55 +#define CAM_CC_IPE_CLK_SRC 56 +#define CAM_CC_IPE_FAST_AHB_CLK 57 +#define CAM_CC_MCLK0_CLK 58 +#define CAM_CC_MCLK0_CLK_SRC 59 +#define CAM_CC_MCLK1_CLK 60 +#define CAM_CC_MCLK1_CLK_SRC 61 +#define CAM_CC_MCLK2_CLK 62 +#define CAM_CC_MCLK2_CLK_SRC 63 +#define CAM_CC_MCLK3_CLK 64 +#define CAM_CC_MCLK3_CLK_SRC 65 +#define CAM_CC_PLL0 66 +#define CAM_CC_PLL0_OUT_EVEN 67 +#define CAM_CC_PLL0_OUT_ODD 68 +#define CAM_CC_PLL2 69 +#define CAM_CC_PLL3 70 +#define CAM_CC_PLL3_OUT_EVEN 71 +#define CAM_CC_PLL4 72 +#define CAM_CC_PLL4_OUT_EVEN 73 +#define CAM_CC_PLL5 74 +#define CAM_CC_PLL5_OUT_EVEN 75 +#define CAM_CC_SFE_LITE_0_CLK 76 +#define CAM_CC_SFE_LITE_0_FAST_AHB_CLK 77 +#define CAM_CC_SFE_LITE_1_CLK 78 +#define CAM_CC_SFE_LITE_1_FAST_AHB_CLK 79 +#define CAM_CC_SLEEP_CLK 80 +#define CAM_CC_SLEEP_CLK_SRC 81 +#define CAM_CC_SLOW_AHB_CLK_SRC 82 +#define CAM_CC_SM_OBS_CLK 83 +#define CAM_CC_XO_CLK_SRC 84 +#define CAM_CC_QDSS_DEBUG_XO_CLK 85 + +/* CAM_CC power domains */ +#define CAM_CC_TITAN_TOP_GDSC 0 + +/* CAM_CC resets */ +#define CAM_CC_ICP_BCR 0 +#define CAM_CC_IFE_0_BCR 1 +#define CAM_CC_IFE_1_BCR 2 +#define CAM_CC_IPE_0_BCR 3 +#define CAM_CC_SFE_LITE_0_BCR 4 +#define CAM_CC_SFE_LITE_1_BCR 5 + +#endif --=20 2.45.2 From nobody Wed Nov 27 08:41:06 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 366531EABA1; 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Reviewed-by: Jagadeesh Kona Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/camcc-sa8775p.c | 1868 ++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 1879 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index bd0f14dad02d2acdfc5c1ccc84bbf3f747ff98f6..72a503168612fdf3ce28e0229b3= f5670afdd81be 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -467,6 +467,16 @@ config QCS_GCC_404 Say Y if you want to use multimedia devices or peripheral devices such as UART, SPI, I2C, USB, SD/eMMC, PCIe etc. =20 +config SA_CAMCC_8775P + tristate "SA8775P Camera Clock Controller" + depends on ARM64 || COMPILE_TEST + select SA_GCC_8775P + help + Support for the camera clock controller on Qualcomm Technologies, Inc + SA8775P devices. + Say Y if you want to support camera devices and functionality such as + capturing pictures. + config SC_CAMCC_7180 tristate "SC7180 Camera Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 548c124c0f990353bd7b8b66e41b0dbbbf3a04e3..b4825528e2b7dc6145032d0c119= 76639c16e651e 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -80,6 +80,7 @@ obj-$(CONFIG_SC_CAMCC_8280XP) +=3D camcc-sc8280xp.o obj-$(CONFIG_SC_DISPCC_7180) +=3D dispcc-sc7180.o obj-$(CONFIG_SC_DISPCC_7280) +=3D dispcc-sc7280.o obj-$(CONFIG_SC_DISPCC_8280XP) +=3D dispcc-sc8280xp.o +obj-$(CONFIG_SA_CAMCC_8775P) +=3D camcc-sa8775p.o obj-$(CONFIG_SA_GCC_8775P) +=3D gcc-sa8775p.o obj-$(CONFIG_SA_GPUCC_8775P) +=3D gpucc-sa8775p.o obj-$(CONFIG_SA_VIDEOCC_8775P) +=3D videocc-sa8775p.o diff --git a/drivers/clk/qcom/camcc-sa8775p.c b/drivers/clk/qcom/camcc-sa87= 75p.c new file mode 100644 index 0000000000000000000000000000000000000000..c04801a5af35089dceac08ac46e= 920576cd0d719 --- /dev/null +++ b/drivers/clk/qcom/camcc-sa8775p.c @@ -0,0 +1,1868 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_IFACE, + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_BI_TCXO_AO, + P_CAM_CC_PLL0_OUT_EVEN, + P_CAM_CC_PLL0_OUT_MAIN, + P_CAM_CC_PLL0_OUT_ODD, + P_CAM_CC_PLL2_OUT_EVEN, + P_CAM_CC_PLL2_OUT_MAIN, + P_CAM_CC_PLL3_OUT_EVEN, + P_CAM_CC_PLL4_OUT_EVEN, + P_CAM_CC_PLL5_OUT_EVEN, + P_SLEEP_CLK, +}; + +static const struct pll_vco lucid_evo_vco[] =3D { + { 249600000, 2020000000, 0 }, +}; + +static const struct pll_vco rivian_evo_vco[] =3D { + { 864000000, 1056000000, 0 }, +}; + +static const struct alpha_pll_config cam_cc_pll0_config =3D { + .l =3D 0x3e, + .alpha =3D 0x8000, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x32aa299c, + .user_ctl_val =3D 0x00008400, + .user_ctl_hi_val =3D 0x00400805, +}; + +static struct clk_alpha_pll cam_cc_pll0 =3D { + .offset =3D 0x0, + .vco_table =3D lucid_evo_vco, + .num_vco =3D ARRAY_SIZE(lucid_evo_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even =3D { + .offset =3D 0x0, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll0_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll0_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] =3D= { + { 0x2, 3 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd =3D { + .offset =3D 0x0, + .post_div_shift =3D 14, + .post_div_table =3D post_div_table_cam_cc_pll0_out_odd, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll0_out_odd", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll2_config =3D { + .l =3D 0x32, + .alpha =3D 0x0, + .config_ctl_val =3D 0x90008820, + .config_ctl_hi_val =3D 0x00890263, + .config_ctl_hi1_val =3D 0x00000247, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00400000, +}; + +static struct clk_alpha_pll cam_cc_pll2 =3D { + .offset =3D 0x1000, + .vco_table =3D rivian_evo_vco, + .num_vco =3D ARRAY_SIZE(rivian_evo_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll2", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_rivian_evo_ops, + }, + }, +}; + +static const struct alpha_pll_config cam_cc_pll3_config =3D { + .l =3D 0x32, + .alpha =3D 0x0, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x32aa299c, + .user_ctl_val =3D 0x00000400, + .user_ctl_hi_val =3D 0x00400805, +}; + +static struct clk_alpha_pll cam_cc_pll3 =3D { + .offset =3D 0x2000, + .vco_table =3D lucid_evo_vco, + .num_vco =3D ARRAY_SIZE(lucid_evo_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll3", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even =3D { + .offset =3D 0x2000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll3_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll3_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll3.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll4_config =3D { + .l =3D 0x32, + .alpha =3D 0x0, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x32aa299c, + .user_ctl_val =3D 0x00000400, + .user_ctl_hi_val =3D 0x00400805, +}; + +static struct clk_alpha_pll cam_cc_pll4 =3D { + .offset =3D 0x3000, + .vco_table =3D lucid_evo_vco, + .num_vco =3D ARRAY_SIZE(lucid_evo_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll4", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even =3D { + .offset =3D 0x3000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll4_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll4_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll4.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll5_config =3D { + .l =3D 0x32, + .alpha =3D 0x0, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x32aa299c, + .user_ctl_val =3D 0x00000400, + .user_ctl_hi_val =3D 0x00400805, +}; + +static struct clk_alpha_pll cam_cc_pll5 =3D { + .offset =3D 0x4000, + .vco_table =3D lucid_evo_vco, + .num_vco =3D ARRAY_SIZE(lucid_evo_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll5", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even =3D { + .offset =3D 0x4000, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_cam_cc_pll5_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_pll5_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_pll5.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +static const struct parent_map cam_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL0_OUT_MAIN, 1 }, + { P_CAM_CC_PLL0_OUT_EVEN, 2 }, + { P_CAM_CC_PLL0_OUT_ODD, 3 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll0.clkr.hw }, + { .hw =3D &cam_cc_pll0_out_even.clkr.hw }, + { .hw =3D &cam_cc_pll0_out_odd.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL2_OUT_EVEN, 3 }, + { P_CAM_CC_PLL2_OUT_MAIN, 5 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll2.clkr.hw }, + { .hw =3D &cam_cc_pll2.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL4_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll4_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL5_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_3[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll5_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_4[] =3D { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL3_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_4[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &cam_cc_pll3_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_5[] =3D { + { P_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_5[] =3D { + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map cam_cc_parent_map_6_ao[] =3D { + { P_BI_TCXO_AO, 0 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_6_ao[] =3D { + { .index =3D DT_BI_TCXO_AO }, +}; + +static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] =3D { + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_camnoc_axi_clk_src =3D { + .cmd_rcgr =3D 0x13170, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_camnoc_axi_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_axi_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] =3D { + F(37500000, P_CAM_CC_PLL0_OUT_MAIN, 16, 1, 2), + { } +}; + +static struct clk_rcg2 cam_cc_cci_0_clk_src =3D { + .cmd_rcgr =3D 0x130a0, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_cci_0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_0_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_cci_1_clk_src =3D { + .cmd_rcgr =3D 0x130bc, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_cci_0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_1_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_cci_2_clk_src =3D { + .cmd_rcgr =3D 0x130d8, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_cci_0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_2_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_cci_3_clk_src =3D { + .cmd_rcgr =3D 0x130f4, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_cci_0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_3_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] =3D { + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_cphy_rx_clk_src =3D { + .cmd_rcgr =3D 0x11034, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_cphy_rx_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cphy_rx_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi0phytimer_clk_src =3D { + .cmd_rcgr =3D 0x15074, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_cphy_rx_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi0phytimer_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi1phytimer_clk_src =3D { + .cmd_rcgr =3D 0x15098, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_cphy_rx_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi1phytimer_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi2phytimer_clk_src =3D { + .cmd_rcgr =3D 0x150b8, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_cphy_rx_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi2phytimer_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi3phytimer_clk_src =3D { + .cmd_rcgr =3D 0x150d8, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_cphy_rx_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi3phytimer_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csid_clk_src =3D { + .cmd_rcgr =3D 0x13150, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_cphy_rx_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csid_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] =3D { + F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_fast_ahb_clk_src =3D { + .cmd_rcgr =3D 0x13120, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_fast_ahb_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_fast_ahb_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] =3D { + F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_icp_clk_src =3D { + .cmd_rcgr =3D 0x1307c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_icp_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_icp_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] =3D { + F(480000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(600000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_0_clk_src =3D { + .cmd_rcgr =3D 0x11004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_2, + .freq_tbl =3D ftbl_cam_cc_ife_0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_0_clk_src", + .parent_data =3D cam_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] =3D { + F(480000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(600000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_1_clk_src =3D { + .cmd_rcgr =3D 0x12004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_3, + .freq_tbl =3D ftbl_cam_cc_ife_1_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_1_clk_src", + .parent_data =3D cam_cc_parent_data_3, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_lite_clk_src[] =3D { + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_lite_clk_src =3D { + .cmd_rcgr =3D 0x13000, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_ife_lite_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src =3D { + .cmd_rcgr =3D 0x13020, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_cphy_rx_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_csid_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ipe_clk_src[] =3D { + F(480000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(600000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ipe_clk_src =3D { + .cmd_rcgr =3D 0x10004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_4, + .freq_tbl =3D ftbl_cam_cc_ipe_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_clk_src", + .parent_data =3D cam_cc_parent_data_4, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_4), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] =3D { + F(19200000, P_CAM_CC_PLL2_OUT_MAIN, 1, 1, 50), + F(24000000, P_CAM_CC_PLL2_OUT_MAIN, 10, 1, 4), + F(64000000, P_CAM_CC_PLL2_OUT_MAIN, 15, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_mclk0_clk_src =3D { + .cmd_rcgr =3D 0x15004, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_mclk0_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk1_clk_src =3D { + .cmd_rcgr =3D 0x15020, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_mclk1_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk2_clk_src =3D { + .cmd_rcgr =3D 0x1503c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_mclk2_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk3_clk_src =3D { + .cmd_rcgr =3D 0x15058, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_1, + .freq_tbl =3D ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_mclk3_clk_src", + .parent_data =3D cam_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] =3D { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_sleep_clk_src =3D { + .cmd_rcgr =3D 0x131f0, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_5, + .freq_tbl =3D ftbl_cam_cc_sleep_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_sleep_clk_src", + .parent_data =3D cam_cc_parent_data_5, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_5), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] =3D { + F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_slow_ahb_clk_src =3D { + .cmd_rcgr =3D 0x13138, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_slow_ahb_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_slow_ahb_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] =3D { + F(19200000, P_BI_TCXO_AO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_xo_clk_src =3D { + .cmd_rcgr =3D 0x131d4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_6_ao, + .freq_tbl =3D ftbl_cam_cc_xo_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_xo_clk_src", + .parent_data =3D cam_cc_parent_data_6_ao, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_6_ao), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_branch cam_cc_camnoc_axi_clk =3D { + .halt_reg =3D 0x13188, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x13188, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_axi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_camnoc_axi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_dcd_xo_clk =3D { + .halt_reg =3D 0x13190, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x13190, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_camnoc_dcd_xo_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qdss_debug_xo_clk =3D { + .halt_reg =3D 0x131b8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x131b8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_qdss_debug_xo_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_0_clk =3D { + .halt_reg =3D 0x130b8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x130b8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cci_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_1_clk =3D { + .halt_reg =3D 0x130d4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x130d4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cci_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_2_clk =3D { + .halt_reg =3D 0x130f0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x130f0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cci_2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_3_clk =3D { + .halt_reg =3D 0x1310c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1310c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cci_3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cci_3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_core_ahb_clk =3D { + .halt_reg =3D 0x131d0, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x131d0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_core_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ahb_clk =3D { + .halt_reg =3D 0x13110, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x13110, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cpas_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_fast_ahb_clk =3D { + .halt_reg =3D 0x13118, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x13118, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cpas_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ife_0_clk =3D { + .halt_reg =3D 0x11024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cpas_ife_0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ife_1_clk =3D { + .halt_reg =3D 0x12024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x12024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cpas_ife_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ife_lite_clk =3D { + .halt_reg =3D 0x1301c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1301c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cpas_ife_lite_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_lite_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ipe_clk =3D { + .halt_reg =3D 0x10024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x10024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cpas_ipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_sfe_lite_0_clk =3D { + .halt_reg =3D 0x13050, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x13050, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cpas_sfe_lite_0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_sfe_lite_1_clk =3D { + .halt_reg =3D 0x13068, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x13068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_cpas_sfe_lite_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi0phytimer_clk =3D { + .halt_reg =3D 0x1508c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1508c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi0phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csi0phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi1phytimer_clk =3D { + .halt_reg =3D 0x150b0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x150b0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi1phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csi1phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi2phytimer_clk =3D { + .halt_reg =3D 0x150d0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x150d0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi2phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csi2phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi3phytimer_clk =3D { + .halt_reg =3D 0x150f0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x150f0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csi3phytimer_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csi3phytimer_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csid_clk =3D { + .halt_reg =3D 0x13168, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x13168, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csid_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_csid_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csid_csiphy_rx_clk =3D { + .halt_reg =3D 0x15094, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x15094, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csid_csiphy_rx_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy0_clk =3D { + .halt_reg =3D 0x15090, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x15090, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csiphy0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy1_clk =3D { + .halt_reg =3D 0x150b4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x150b4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csiphy1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy2_clk =3D { + .halt_reg =3D 0x150d4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x150d4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csiphy2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy3_clk =3D { + .halt_reg =3D 0x150f4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x150f4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_csiphy3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_ahb_clk =3D { + .halt_reg =3D 0x1309c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1309c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_icp_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_clk =3D { + .halt_reg =3D 0x13094, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x13094, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_icp_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_icp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_clk =3D { + .halt_reg =3D 0x1101c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1101c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_fast_ahb_clk =3D { + .halt_reg =3D 0x11030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x11030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_0_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_clk =3D { + .halt_reg =3D 0x1201c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1201c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_fast_ahb_clk =3D { + .halt_reg =3D 0x12030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x12030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_1_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_ahb_clk =3D { + .halt_reg =3D 0x13044, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x13044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_clk =3D { + .halt_reg =3D 0x13018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x13018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_lite_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_cphy_rx_clk =3D { + .halt_reg =3D 0x13040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x13040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_cphy_rx_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_csid_clk =3D { + .halt_reg =3D 0x13038, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x13038, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ife_lite_csid_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_lite_csid_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_ahb_clk =3D { + .halt_reg =3D 0x10030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x10030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_clk =3D { + .halt_reg =3D 0x1001c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1001c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_fast_ahb_clk =3D { + .halt_reg =3D 0x10034, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x10034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_ipe_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk0_clk =3D { + .halt_reg =3D 0x1501c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1501c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_mclk0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_mclk0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk1_clk =3D { + .halt_reg =3D 0x15038, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x15038, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_mclk1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_mclk1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk2_clk =3D { + .halt_reg =3D 0x15054, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x15054, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_mclk2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_mclk2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk3_clk =3D { + .halt_reg =3D 0x15070, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x15070, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_mclk3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_mclk3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_lite_0_clk =3D { + .halt_reg =3D 0x1304c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1304c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_sfe_lite_0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_lite_0_fast_ahb_clk =3D { + .halt_reg =3D 0x1305c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1305c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_sfe_lite_0_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_lite_1_clk =3D { + .halt_reg =3D 0x13064, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x13064, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_sfe_lite_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_ife_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_lite_1_fast_ahb_clk =3D { + .halt_reg =3D 0x13074, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x13074, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_sfe_lite_1_fast_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sm_obs_clk =3D { + .halt_reg =3D 0x1510c, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0x1510c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_sm_obs_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc cam_cc_titan_top_gdsc =3D { + .gdscr =3D 0x131bc, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "cam_cc_titan_top_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *cam_cc_sa8775p_clocks[] =3D { + [CAM_CC_CAMNOC_AXI_CLK] =3D &cam_cc_camnoc_axi_clk.clkr, + [CAM_CC_CAMNOC_AXI_CLK_SRC] =3D &cam_cc_camnoc_axi_clk_src.clkr, + [CAM_CC_CAMNOC_DCD_XO_CLK] =3D &cam_cc_camnoc_dcd_xo_clk.clkr, + [CAM_CC_CCI_0_CLK] =3D &cam_cc_cci_0_clk.clkr, + [CAM_CC_CCI_0_CLK_SRC] =3D &cam_cc_cci_0_clk_src.clkr, + [CAM_CC_CCI_1_CLK] =3D &cam_cc_cci_1_clk.clkr, + [CAM_CC_CCI_1_CLK_SRC] =3D &cam_cc_cci_1_clk_src.clkr, + [CAM_CC_CCI_2_CLK] =3D &cam_cc_cci_2_clk.clkr, + [CAM_CC_CCI_2_CLK_SRC] =3D &cam_cc_cci_2_clk_src.clkr, + [CAM_CC_CCI_3_CLK] =3D &cam_cc_cci_3_clk.clkr, + [CAM_CC_CCI_3_CLK_SRC] =3D &cam_cc_cci_3_clk_src.clkr, + [CAM_CC_CORE_AHB_CLK] =3D &cam_cc_core_ahb_clk.clkr, + [CAM_CC_CPAS_AHB_CLK] =3D &cam_cc_cpas_ahb_clk.clkr, + [CAM_CC_CPAS_FAST_AHB_CLK] =3D &cam_cc_cpas_fast_ahb_clk.clkr, + [CAM_CC_CPAS_IFE_0_CLK] =3D &cam_cc_cpas_ife_0_clk.clkr, + [CAM_CC_CPAS_IFE_1_CLK] =3D &cam_cc_cpas_ife_1_clk.clkr, + [CAM_CC_CPAS_IFE_LITE_CLK] =3D &cam_cc_cpas_ife_lite_clk.clkr, + [CAM_CC_CPAS_IPE_CLK] =3D &cam_cc_cpas_ipe_clk.clkr, + [CAM_CC_CPAS_SFE_LITE_0_CLK] =3D &cam_cc_cpas_sfe_lite_0_clk.clkr, + [CAM_CC_CPAS_SFE_LITE_1_CLK] =3D &cam_cc_cpas_sfe_lite_1_clk.clkr, + [CAM_CC_CPHY_RX_CLK_SRC] =3D &cam_cc_cphy_rx_clk_src.clkr, + [CAM_CC_CSI0PHYTIMER_CLK] =3D &cam_cc_csi0phytimer_clk.clkr, + [CAM_CC_CSI0PHYTIMER_CLK_SRC] =3D &cam_cc_csi0phytimer_clk_src.clkr, + [CAM_CC_CSI1PHYTIMER_CLK] =3D &cam_cc_csi1phytimer_clk.clkr, + [CAM_CC_CSI1PHYTIMER_CLK_SRC] =3D &cam_cc_csi1phytimer_clk_src.clkr, + [CAM_CC_CSI2PHYTIMER_CLK] =3D &cam_cc_csi2phytimer_clk.clkr, + [CAM_CC_CSI2PHYTIMER_CLK_SRC] =3D &cam_cc_csi2phytimer_clk_src.clkr, + [CAM_CC_CSI3PHYTIMER_CLK] =3D &cam_cc_csi3phytimer_clk.clkr, + [CAM_CC_CSI3PHYTIMER_CLK_SRC] =3D &cam_cc_csi3phytimer_clk_src.clkr, + [CAM_CC_CSID_CLK] =3D &cam_cc_csid_clk.clkr, + [CAM_CC_CSID_CLK_SRC] =3D &cam_cc_csid_clk_src.clkr, + [CAM_CC_CSID_CSIPHY_RX_CLK] =3D &cam_cc_csid_csiphy_rx_clk.clkr, + [CAM_CC_CSIPHY0_CLK] =3D &cam_cc_csiphy0_clk.clkr, + [CAM_CC_CSIPHY1_CLK] =3D &cam_cc_csiphy1_clk.clkr, + [CAM_CC_CSIPHY2_CLK] =3D &cam_cc_csiphy2_clk.clkr, + [CAM_CC_CSIPHY3_CLK] =3D &cam_cc_csiphy3_clk.clkr, + [CAM_CC_FAST_AHB_CLK_SRC] =3D &cam_cc_fast_ahb_clk_src.clkr, + [CAM_CC_ICP_AHB_CLK] =3D &cam_cc_icp_ahb_clk.clkr, + [CAM_CC_ICP_CLK] =3D &cam_cc_icp_clk.clkr, + [CAM_CC_ICP_CLK_SRC] =3D &cam_cc_icp_clk_src.clkr, + [CAM_CC_IFE_0_CLK] =3D &cam_cc_ife_0_clk.clkr, + [CAM_CC_IFE_0_CLK_SRC] =3D &cam_cc_ife_0_clk_src.clkr, + [CAM_CC_IFE_0_FAST_AHB_CLK] =3D &cam_cc_ife_0_fast_ahb_clk.clkr, + [CAM_CC_IFE_1_CLK] =3D &cam_cc_ife_1_clk.clkr, + [CAM_CC_IFE_1_CLK_SRC] =3D &cam_cc_ife_1_clk_src.clkr, + [CAM_CC_IFE_1_FAST_AHB_CLK] =3D &cam_cc_ife_1_fast_ahb_clk.clkr, + [CAM_CC_IFE_LITE_AHB_CLK] =3D &cam_cc_ife_lite_ahb_clk.clkr, + [CAM_CC_IFE_LITE_CLK] =3D &cam_cc_ife_lite_clk.clkr, + [CAM_CC_IFE_LITE_CLK_SRC] =3D &cam_cc_ife_lite_clk_src.clkr, + [CAM_CC_IFE_LITE_CPHY_RX_CLK] =3D &cam_cc_ife_lite_cphy_rx_clk.clkr, + [CAM_CC_IFE_LITE_CSID_CLK] =3D &cam_cc_ife_lite_csid_clk.clkr, + [CAM_CC_IFE_LITE_CSID_CLK_SRC] =3D &cam_cc_ife_lite_csid_clk_src.clkr, + [CAM_CC_IPE_AHB_CLK] =3D &cam_cc_ipe_ahb_clk.clkr, + [CAM_CC_IPE_CLK] =3D &cam_cc_ipe_clk.clkr, + [CAM_CC_IPE_CLK_SRC] =3D &cam_cc_ipe_clk_src.clkr, + [CAM_CC_IPE_FAST_AHB_CLK] =3D &cam_cc_ipe_fast_ahb_clk.clkr, + [CAM_CC_MCLK0_CLK] =3D &cam_cc_mclk0_clk.clkr, + [CAM_CC_MCLK0_CLK_SRC] =3D &cam_cc_mclk0_clk_src.clkr, + [CAM_CC_MCLK1_CLK] =3D &cam_cc_mclk1_clk.clkr, + [CAM_CC_MCLK1_CLK_SRC] =3D &cam_cc_mclk1_clk_src.clkr, + [CAM_CC_MCLK2_CLK] =3D &cam_cc_mclk2_clk.clkr, + [CAM_CC_MCLK2_CLK_SRC] =3D &cam_cc_mclk2_clk_src.clkr, + [CAM_CC_MCLK3_CLK] =3D &cam_cc_mclk3_clk.clkr, + [CAM_CC_MCLK3_CLK_SRC] =3D &cam_cc_mclk3_clk_src.clkr, + [CAM_CC_PLL0] =3D &cam_cc_pll0.clkr, + [CAM_CC_PLL0_OUT_EVEN] =3D &cam_cc_pll0_out_even.clkr, + [CAM_CC_PLL0_OUT_ODD] =3D &cam_cc_pll0_out_odd.clkr, + [CAM_CC_PLL2] =3D &cam_cc_pll2.clkr, + [CAM_CC_PLL3] =3D &cam_cc_pll3.clkr, + [CAM_CC_PLL3_OUT_EVEN] =3D &cam_cc_pll3_out_even.clkr, + [CAM_CC_PLL4] =3D &cam_cc_pll4.clkr, + [CAM_CC_PLL4_OUT_EVEN] =3D &cam_cc_pll4_out_even.clkr, + [CAM_CC_PLL5] =3D &cam_cc_pll5.clkr, + [CAM_CC_PLL5_OUT_EVEN] =3D &cam_cc_pll5_out_even.clkr, + [CAM_CC_SFE_LITE_0_CLK] =3D &cam_cc_sfe_lite_0_clk.clkr, + [CAM_CC_SFE_LITE_0_FAST_AHB_CLK] =3D &cam_cc_sfe_lite_0_fast_ahb_clk.clkr, + [CAM_CC_SFE_LITE_1_CLK] =3D &cam_cc_sfe_lite_1_clk.clkr, + [CAM_CC_SFE_LITE_1_FAST_AHB_CLK] =3D &cam_cc_sfe_lite_1_fast_ahb_clk.clkr, + [CAM_CC_SLEEP_CLK_SRC] =3D &cam_cc_sleep_clk_src.clkr, + [CAM_CC_SLOW_AHB_CLK_SRC] =3D &cam_cc_slow_ahb_clk_src.clkr, + [CAM_CC_SM_OBS_CLK] =3D &cam_cc_sm_obs_clk.clkr, + [CAM_CC_XO_CLK_SRC] =3D &cam_cc_xo_clk_src.clkr, + [CAM_CC_QDSS_DEBUG_XO_CLK] =3D &cam_cc_qdss_debug_xo_clk.clkr, +}; + +static struct gdsc *cam_cc_sa8775p_gdscs[] =3D { + [CAM_CC_TITAN_TOP_GDSC] =3D &cam_cc_titan_top_gdsc, +}; + +static const struct qcom_reset_map cam_cc_sa8775p_resets[] =3D { + [CAM_CC_ICP_BCR] =3D { 0x13078 }, + [CAM_CC_IFE_0_BCR] =3D { 0x11000 }, + [CAM_CC_IFE_1_BCR] =3D { 0x12000 }, + [CAM_CC_IPE_0_BCR] =3D { 0x10000 }, + [CAM_CC_SFE_LITE_0_BCR] =3D { 0x13048 }, + [CAM_CC_SFE_LITE_1_BCR] =3D { 0x13060 }, +}; + +static const struct regmap_config cam_cc_sa8775p_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x16218, + .fast_io =3D true, +}; + +static struct qcom_cc_desc cam_cc_sa8775p_desc =3D { + .config =3D &cam_cc_sa8775p_regmap_config, + .clks =3D cam_cc_sa8775p_clocks, + .num_clks =3D ARRAY_SIZE(cam_cc_sa8775p_clocks), + .resets =3D cam_cc_sa8775p_resets, + .num_resets =3D ARRAY_SIZE(cam_cc_sa8775p_resets), + .gdscs =3D cam_cc_sa8775p_gdscs, + .num_gdscs =3D ARRAY_SIZE(cam_cc_sa8775p_gdscs), +}; + +static const struct of_device_id cam_cc_sa8775p_match_table[] =3D { + { .compatible =3D "qcom,sa8775p-camcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, cam_cc_sa8775p_match_table); + +static int cam_cc_sa8775p_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + ret =3D devm_pm_runtime_enable(&pdev->dev); + if (ret) + return ret; + + ret =3D pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; + + regmap =3D qcom_cc_map(pdev, &cam_cc_sa8775p_desc); + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); + return PTR_ERR(regmap); + } + + clk_lucid_evo_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); + clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); + clk_lucid_evo_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); + clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); + clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config); + + /* Keep some clocks always enabled */ + qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */ + qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */ + + ret =3D qcom_cc_really_probe(&pdev->dev, &cam_cc_sa8775p_desc, regmap); + + pm_runtime_put(&pdev->dev); + + return ret; +} + +static struct platform_driver cam_cc_sa8775p_driver =3D { + .probe =3D cam_cc_sa8775p_probe, + .driver =3D { + .name =3D "camcc-sa8775p", + .of_match_table =3D cam_cc_sa8775p_match_table, + }, +}; + +module_platform_driver(cam_cc_sa8775p_driver); + +MODULE_DESCRIPTION("QTI CAMCC SA8775P Driver"); +MODULE_LICENSE("GPL"); --=20 2.45.2 From nobody Wed Nov 27 08:41:06 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C4891EB9F6; Thu, 10 Oct 2024 18:59:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728586765; cv=none; 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Reviewed-by: Krzysztof Kozlowski Signed-off-by: Taniya Das --- .../bindings/clock/qcom,sa8775p-dispcc.yaml | 79 ++++++++++++++++++= ++ include/dt-bindings/clock/qcom,sa8775p-dispcc.h | 87 ++++++++++++++++++= ++++ 2 files changed, 166 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sa8775p-dispcc.ya= ml b/Documentation/devicetree/bindings/clock/qcom,sa8775p-dispcc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..ce61755e62d40b8615899b6ead1= 1d00df96b7754 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sa8775p-dispcc.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sa8775p-dispcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller on SA8775P + +maintainers: + - Taniya Das + +description: | + Qualcomm display clock control module provides the clocks, resets and po= wer + domains on SA8775P. + + See also: include/dt-bindings/clock/qcom,sa8775p-dispcc.h + +properties: + compatible: + enum: + - qcom,sa8775p-dispcc0 + - qcom,sa8775p-dispcc1 + + clocks: + items: + - description: GCC AHB clock source + - description: Board XO source + - description: Board XO_AO source + - description: Sleep clock source + - description: Link clock from DP0 PHY + - description: VCO DIV clock from DP0 PHY + - description: Link clock from DP1 PHY + - description: VCO DIV clock from DP1 PHY + - description: Byte clock from DSI0 PHY + - description: Pixel clock from DSI0 PHY + - description: Byte clock from DSI1 PHY + - description: Pixel clock from DSI1 PHY + + power-domains: + maxItems: 1 + description: MMCX power domain + +required: + - compatible + - clocks + - power-domains + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + clock-controller@af00000 { + compatible =3D "qcom,sa8775p-dispcc0"; + reg =3D <0x0af00000 0x20000>; + clocks =3D <&gcc GCC_DISP_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&dp_phy0 0>, + <&dp_phy0 1>, + <&dp_phy1 2>, + <&dp_phy1 3>, + <&dsi_phy0 0>, + <&dsi_phy0 1>, + <&dsi_phy1 2>, + <&dsi_phy1 3>; + power-domains =3D <&rpmhpd SA8775P_MMCX>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,sa8775p-dispcc.h b/include/dt-b= indings/clock/qcom,sa8775p-dispcc.h new file mode 100644 index 0000000000000000000000000000000000000000..e2049e5106587f55526fba02d06= 16c9d41649dc7 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sa8775p-dispcc.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_SA8775P_DISP_CC_H +#define _DT_BINDINGS_CLK_QCOM_SA8775P_DISP_CC_H + +/* DISP_CC_0/1 clocks */ +#define MDSS_DISP_CC_MDSS_AHB1_CLK 0 +#define MDSS_DISP_CC_MDSS_AHB_CLK 1 +#define MDSS_DISP_CC_MDSS_AHB_CLK_SRC 2 +#define MDSS_DISP_CC_MDSS_BYTE0_CLK 3 +#define MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC 4 +#define MDSS_DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5 +#define MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK 6 +#define MDSS_DISP_CC_MDSS_BYTE1_CLK 7 +#define MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC 8 +#define MDSS_DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 9 +#define MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK 10 +#define MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK 11 +#define MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 12 +#define MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK 13 +#define MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK_SRC 14 +#define MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK 15 +#define MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 16 +#define MDSS_DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 17 +#define MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 18 +#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK 19 +#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 20 +#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK 21 +#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 22 +#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK 23 +#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC 24 +#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK 25 +#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC 26 +#define MDSS_DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 27 +#define MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK 28 +#define MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 29 +#define MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK 30 +#define MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK_SRC 31 +#define MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK 32 +#define MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 33 +#define MDSS_DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 34 +#define MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 35 +#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK 36 +#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 37 +#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK 38 +#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 39 +#define MDSS_DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 40 +#define MDSS_DISP_CC_MDSS_ESC0_CLK 41 +#define MDSS_DISP_CC_MDSS_ESC0_CLK_SRC 42 +#define MDSS_DISP_CC_MDSS_ESC1_CLK 43 +#define MDSS_DISP_CC_MDSS_ESC1_CLK_SRC 44 +#define MDSS_DISP_CC_MDSS_MDP1_CLK 45 +#define MDSS_DISP_CC_MDSS_MDP_CLK 46 +#define MDSS_DISP_CC_MDSS_MDP_CLK_SRC 47 +#define MDSS_DISP_CC_MDSS_MDP_LUT1_CLK 48 +#define MDSS_DISP_CC_MDSS_MDP_LUT_CLK 49 +#define MDSS_DISP_CC_MDSS_NON_GDSC_AHB_CLK 50 +#define MDSS_DISP_CC_MDSS_PCLK0_CLK 51 +#define MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC 52 +#define MDSS_DISP_CC_MDSS_PCLK1_CLK 53 +#define MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC 54 +#define MDSS_DISP_CC_MDSS_PLL_LOCK_MONITOR_CLK 55 +#define MDSS_DISP_CC_MDSS_RSCC_AHB_CLK 56 +#define MDSS_DISP_CC_MDSS_RSCC_VSYNC_CLK 57 +#define MDSS_DISP_CC_MDSS_VSYNC1_CLK 58 +#define MDSS_DISP_CC_MDSS_VSYNC_CLK 59 +#define MDSS_DISP_CC_MDSS_VSYNC_CLK_SRC 60 +#define MDSS_DISP_CC_PLL0 61 +#define MDSS_DISP_CC_PLL1 62 +#define MDSS_DISP_CC_SLEEP_CLK 63 +#define MDSS_DISP_CC_SLEEP_CLK_SRC 64 +#define MDSS_DISP_CC_SM_OBS_CLK 65 +#define MDSS_DISP_CC_XO_CLK 66 +#define MDSS_DISP_CC_XO_CLK_SRC 67 + +/* DISP_CC_0/1 power domains */ +#define MDSS_DISP_CC_MDSS_CORE_GDSC 0 +#define MDSS_DISP_CC_MDSS_CORE_INT2_GDSC 1 + +/* DISP_CC_0/1 resets */ +#define MDSS_DISP_CC_MDSS_CORE_BCR 0 +#define MDSS_DISP_CC_MDSS_RSCC_BCR 1 + +#endif --=20 2.45.2 From nobody Wed Nov 27 08:41:06 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D932D1EF0A2; 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Thu, 10 Oct 2024 18:59:24 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49AIxNVQ026383 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 10 Oct 2024 18:59:23 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 10 Oct 2024 11:59:18 -0700 From: Taniya Das Date: Fri, 11 Oct 2024 00:28:36 +0530 Subject: [PATCH v5 6/8] clk: qcom: Add support for Display clock Controllers on SA8775P Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241011-sa8775p-mm-v4-resend-patches-v5-6-4a9f17dc683a@quicinc.com> References: <20241011-sa8775p-mm-v4-resend-patches-v5-0-4a9f17dc683a@quicinc.com> In-Reply-To: <20241011-sa8775p-mm-v4-resend-patches-v5-0-4a9f17dc683a@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , , , Bartosz Golaszewski CC: , , , , Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: IZCqZEUAfl-5tx4he5YbEbYjtVRDL8uA X-Proofpoint-ORIG-GUID: IZCqZEUAfl-5tx4he5YbEbYjtVRDL8uA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxlogscore=999 lowpriorityscore=0 spamscore=0 malwarescore=0 adultscore=0 suspectscore=0 clxscore=1015 mlxscore=0 impostorscore=0 priorityscore=1501 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410100125 Add support for display0 and display1 clock controllers on SA8775P platform. Reviewed-by: Jagadeesh Kona Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/dispcc0-sa8775p.c | 1481 ++++++++++++++++++++++++++++++++= ++++ drivers/clk/qcom/dispcc1-sa8775p.c | 1481 ++++++++++++++++++++++++++++++++= ++++ 4 files changed, 2973 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 72a503168612fdf3ce28e0229b3f5670afdd81be..8aa95fc7a45781f792d1db642b4= 7a37e7bd1eaf7 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -507,6 +507,16 @@ config SC_CAMCC_8280XP Say Y if you want to support camera devices and functionality such as capturing pictures. =20 +config SA_DISPCC_8775P + tristate "SA8775P Display Clock Controller" + depends on ARM64 || COMPILE_TEST + select SA_GCC_8775P + help + Support for the two display clock controllers on Qualcomm + Technologies, Inc. SA8775P devices. + Say Y if you want to support display devices and functionality such as + splash screen. + config SC_DISPCC_7180 tristate "SC7180 Display Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index b4825528e2b7dc6145032d0c11976639c16e651e..fac4b9b61e55e879d8dc73f041a= 74043ec61aa89 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -81,6 +81,7 @@ obj-$(CONFIG_SC_DISPCC_7180) +=3D dispcc-sc7180.o obj-$(CONFIG_SC_DISPCC_7280) +=3D dispcc-sc7280.o obj-$(CONFIG_SC_DISPCC_8280XP) +=3D dispcc-sc8280xp.o obj-$(CONFIG_SA_CAMCC_8775P) +=3D camcc-sa8775p.o +obj-$(CONFIG_SA_DISPCC_8775P) +=3D dispcc0-sa8775p.o dispcc1-sa8775p.o obj-$(CONFIG_SA_GCC_8775P) +=3D gcc-sa8775p.o obj-$(CONFIG_SA_GPUCC_8775P) +=3D gpucc-sa8775p.o obj-$(CONFIG_SA_VIDEOCC_8775P) +=3D videocc-sa8775p.o diff --git a/drivers/clk/qcom/dispcc0-sa8775p.c b/drivers/clk/qcom/dispcc0-= sa8775p.c new file mode 100644 index 0000000000000000000000000000000000000000..6e399b5f138371e81e24500433a= 36e5f22d93016 --- /dev/null +++ b/drivers/clk/qcom/dispcc0-sa8775p.c @@ -0,0 +1,1481 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_IFACE, + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_SLEEP_CLK, + DT_DP0_PHY_PLL_LINK_CLK, + DT_DP0_PHY_PLL_VCO_DIV_CLK, + DT_DP1_PHY_PLL_LINK_CLK, + DT_DP1_PHY_PLL_VCO_DIV_CLK, + DT_DSI0_PHY_PLL_OUT_BYTECLK, + DT_DSI0_PHY_PLL_OUT_DSICLK, + DT_DSI1_PHY_PLL_OUT_BYTECLK, + DT_DSI1_PHY_PLL_OUT_DSICLK, +}; + +enum { + P_BI_TCXO, + P_DP0_PHY_PLL_LINK_CLK, + P_DP0_PHY_PLL_VCO_DIV_CLK, + P_DP1_PHY_PLL_LINK_CLK, + P_DP1_PHY_PLL_VCO_DIV_CLK, + P_DSI0_PHY_PLL_OUT_BYTECLK, + P_DSI0_PHY_PLL_OUT_DSICLK, + P_DSI1_PHY_PLL_OUT_BYTECLK, + P_DSI1_PHY_PLL_OUT_DSICLK, + P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, + P_MDSS_0_DISP_CC_PLL1_OUT_EVEN, + P_MDSS_0_DISP_CC_PLL1_OUT_MAIN, + P_SLEEP_CLK, +}; + +static const struct pll_vco lucid_evo_vco[] =3D { + { 249600000, 2020000000, 0 }, +}; + +static const struct alpha_pll_config mdss_0_disp_cc_pll0_config =3D { + .l =3D 0x3a, + .alpha =3D 0x9800, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x32aa299c, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00400805, +}; + +static struct clk_alpha_pll mdss_0_disp_cc_pll0 =3D { + .offset =3D 0x0, + .vco_table =3D lucid_evo_vco, + .num_vco =3D ARRAY_SIZE(lucid_evo_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct alpha_pll_config mdss_0_disp_cc_pll1_config =3D { + .l =3D 0x1f, + .alpha =3D 0x4000, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x32aa299c, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00400805, +}; + +static struct clk_alpha_pll mdss_0_disp_cc_pll1 =3D { + .offset =3D 0x1000, + .vco_table =3D lucid_evo_vco, + .num_vco =3D ARRAY_SIZE(lucid_evo_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_pll1", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct parent_map disp_cc_0_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_DP0_PHY_PLL_LINK_CLK, 1 }, + { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 }, + { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, +}; + +static const struct clk_parent_data disp_cc_0_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DP0_PHY_PLL_LINK_CLK }, + { .index =3D DT_DP0_PHY_PLL_VCO_DIV_CLK }, + { .index =3D DT_DP1_PHY_PLL_VCO_DIV_CLK }, +}; + +static const struct parent_map disp_cc_0_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, + { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, + { P_DSI1_PHY_PLL_OUT_DSICLK, 3 }, + { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, +}; + +static const struct clk_parent_data disp_cc_0_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DSI0_PHY_PLL_OUT_DSICLK }, + { .index =3D DT_DSI0_PHY_PLL_OUT_BYTECLK }, + { .index =3D DT_DSI1_PHY_PLL_OUT_DSICLK }, + { .index =3D DT_DSI1_PHY_PLL_OUT_BYTECLK }, +}; + +static const struct parent_map disp_cc_0_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data disp_cc_0_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, +}; + +static const struct clk_parent_data disp_cc_0_parent_data_2_ao[] =3D { + { .index =3D DT_BI_TCXO_AO }, +}; + +static const struct parent_map disp_cc_0_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, + { P_DP0_PHY_PLL_LINK_CLK, 1 }, + { P_DP1_PHY_PLL_LINK_CLK, 2 }, +}; + +static const struct clk_parent_data disp_cc_0_parent_data_3[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DP0_PHY_PLL_LINK_CLK }, + { .index =3D DT_DP1_PHY_PLL_LINK_CLK }, +}; + +static const struct parent_map disp_cc_0_parent_map_4[] =3D { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, + { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, +}; + +static const struct clk_parent_data disp_cc_0_parent_data_4[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DSI0_PHY_PLL_OUT_BYTECLK }, + { .index =3D DT_DSI1_PHY_PLL_OUT_BYTECLK }, +}; + +static const struct parent_map disp_cc_0_parent_map_5[] =3D { + { P_BI_TCXO, 0 }, + { P_MDSS_0_DISP_CC_PLL1_OUT_MAIN, 4 }, + { P_MDSS_0_DISP_CC_PLL1_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data disp_cc_0_parent_data_5[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &mdss_0_disp_cc_pll1.clkr.hw }, + { .hw =3D &mdss_0_disp_cc_pll1.clkr.hw }, +}; + +static const struct parent_map disp_cc_0_parent_map_6[] =3D { + { P_BI_TCXO, 0 }, + { P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, 1 }, + { P_MDSS_0_DISP_CC_PLL1_OUT_MAIN, 4 }, + { P_MDSS_0_DISP_CC_PLL1_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data disp_cc_0_parent_data_6[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &mdss_0_disp_cc_pll0.clkr.hw }, + { .hw =3D &mdss_0_disp_cc_pll1.clkr.hw }, + { .hw =3D &mdss_0_disp_cc_pll1.clkr.hw }, +}; + +static const struct parent_map disp_cc_0_parent_map_7[] =3D { + { P_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data disp_cc_0_parent_data_7[] =3D { + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct freq_tbl ftbl_mdss_0_disp_cc_mdss_ahb_clk_src[] =3D { + F(37500000, P_MDSS_0_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0), + F(75000000, P_MDSS_0_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0), + { } +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_ahb_clk_src =3D { + .cmd_rcgr =3D 0x824c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_5, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_ahb_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_ahb_clk_src", + .parent_data =3D disp_cc_0_parent_data_5, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_5), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_mdss_0_disp_cc_mdss_byte0_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_byte0_clk_src =3D { + .cmd_rcgr =3D 0x80ec, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_1, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_byte0_clk_src", + .parent_data =3D disp_cc_0_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_byte1_clk_src =3D { + .cmd_rcgr =3D 0x8108, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_1, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_byte1_clk_src", + .parent_data =3D disp_cc_0_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_aux_clk_src =3D { + .cmd_rcgr =3D 0x81b8, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_2, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_aux_clk_src", + .parent_data =3D disp_cc_0_parent_data_2, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_crypto_clk_src =3D { + .cmd_rcgr =3D 0x8170, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_3, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_crypto_clk_src", + .parent_data =3D disp_cc_0_parent_data_3, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_link_clk_src =3D { + .cmd_rcgr =3D 0x8154, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_3, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_link_clk_src", + .parent_data =3D disp_cc_0_parent_data_3, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_pixel0_clk_src =3D { + .cmd_rcgr =3D 0x8188, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_0, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_pixel0_clk_src", + .parent_data =3D disp_cc_0_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_pixel1_clk_src =3D { + .cmd_rcgr =3D 0x81a0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_0, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_pixel1_clk_src", + .parent_data =3D disp_cc_0_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_pixel2_clk_src =3D { + .cmd_rcgr =3D 0x826c, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_0, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_pixel2_clk_src", + .parent_data =3D disp_cc_0_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_pixel3_clk_src =3D { + .cmd_rcgr =3D 0x8284, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_0, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_pixel3_clk_src", + .parent_data =3D disp_cc_0_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx1_aux_clk_src =3D { + .cmd_rcgr =3D 0x8234, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_2, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx1_aux_clk_src", + .parent_data =3D disp_cc_0_parent_data_2, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx1_crypto_clk_src =3D { + .cmd_rcgr =3D 0x821c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_3, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx1_crypto_clk_src", + .parent_data =3D disp_cc_0_parent_data_3, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx1_link_clk_src =3D { + .cmd_rcgr =3D 0x8200, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_3, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx1_link_clk_src", + .parent_data =3D disp_cc_0_parent_data_3, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx1_pixel0_clk_src =3D { + .cmd_rcgr =3D 0x81d0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_0, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx1_pixel0_clk_src", + .parent_data =3D disp_cc_0_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx1_pixel1_clk_src =3D { + .cmd_rcgr =3D 0x81e8, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_0, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx1_pixel1_clk_src", + .parent_data =3D disp_cc_0_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_esc0_clk_src =3D { + .cmd_rcgr =3D 0x8124, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_4, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_esc0_clk_src", + .parent_data =3D disp_cc_0_parent_data_4, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_4), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_esc1_clk_src =3D { + .cmd_rcgr =3D 0x813c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_4, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_esc1_clk_src", + .parent_data =3D disp_cc_0_parent_data_4, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_4), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_mdss_0_disp_cc_mdss_mdp_clk_src[] =3D { + F(375000000, P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(500000000, P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(575000000, P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(650000000, P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_mdp_clk_src =3D { + .cmd_rcgr =3D 0x80bc, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_6, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_mdp_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_mdp_clk_src", + .parent_data =3D disp_cc_0_parent_data_6, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_6), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_pclk0_clk_src =3D { + .cmd_rcgr =3D 0x808c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_1, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_pclk0_clk_src", + .parent_data =3D disp_cc_0_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_pixel_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_pclk1_clk_src =3D { + .cmd_rcgr =3D 0x80a4, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_1, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_pclk1_clk_src", + .parent_data =3D disp_cc_0_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_pixel_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_vsync_clk_src =3D { + .cmd_rcgr =3D 0x80d4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_2, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_vsync_clk_src", + .parent_data =3D disp_cc_0_parent_data_2, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_mdss_0_disp_cc_sleep_clk_src[] =3D { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 mdss_0_disp_cc_sleep_clk_src =3D { + .cmd_rcgr =3D 0xc058, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_7, + .freq_tbl =3D ftbl_mdss_0_disp_cc_sleep_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_sleep_clk_src", + .parent_data =3D disp_cc_0_parent_data_7, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_7), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_xo_clk_src =3D { + .cmd_rcgr =3D 0xc03c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_2, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_xo_clk_src", + .parent_data =3D disp_cc_0_parent_data_2_ao, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_2_ao), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div mdss_0_disp_cc_mdss_byte0_div_clk_src =3D { + .reg =3D 0x8104, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_byte0_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div mdss_0_disp_cc_mdss_byte1_div_clk_src =3D { + .reg =3D 0x8120, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_byte1_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_byte1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div mdss_0_disp_cc_mdss_dptx0_link_div_clk_src = =3D { + .reg =3D 0x816c, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_link_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx0_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div mdss_0_disp_cc_mdss_dptx1_link_div_clk_src = =3D { + .reg =3D 0x8218, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx1_link_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx1_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_ahb1_clk =3D { + .halt_reg =3D 0x8088, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8088, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_ahb1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_ahb_clk =3D { + .halt_reg =3D 0x8084, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8084, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_byte0_clk =3D { + .halt_reg =3D 0x8034, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_byte0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_byte0_intf_clk =3D { + .halt_reg =3D 0x8038, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8038, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_byte0_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_byte0_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_byte1_clk =3D { + .halt_reg =3D 0x803c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x803c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_byte1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_byte1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_byte1_intf_clk =3D { + .halt_reg =3D 0x8040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_byte1_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_byte1_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx0_aux_clk =3D { + .halt_reg =3D 0x805c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x805c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx0_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx0_crypto_clk =3D { + .halt_reg =3D 0x8058, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8058, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_crypto_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx0_crypto_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx0_link_clk =3D { + .halt_reg =3D 0x804c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x804c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_link_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx0_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx0_link_intf_clk =3D { + .halt_reg =3D 0x8050, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8050, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_link_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx0_pixel0_clk =3D { + .halt_reg =3D 0x8060, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8060, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_pixel0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx0_pixel1_clk =3D { + .halt_reg =3D 0x8064, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8064, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_pixel1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx0_pixel2_clk =3D { + .halt_reg =3D 0x8264, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8264, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_pixel2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx0_pixel2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx0_pixel3_clk =3D { + .halt_reg =3D 0x8268, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8268, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_pixel3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx0_pixel3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx0_usb_router_link_intf_cl= k =3D { + .halt_reg =3D 0x8054, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8054, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_usb_router_link_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx1_aux_clk =3D { + .halt_reg =3D 0x8080, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8080, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx1_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx1_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx1_crypto_clk =3D { + .halt_reg =3D 0x807c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x807c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx1_crypto_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx1_crypto_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx1_link_clk =3D { + .halt_reg =3D 0x8070, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8070, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx1_link_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx1_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx1_link_intf_clk =3D { + .halt_reg =3D 0x8074, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8074, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx1_link_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx1_pixel0_clk =3D { + .halt_reg =3D 0x8068, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx1_pixel0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx1_pixel1_clk =3D { + .halt_reg =3D 0x806c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x806c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx1_pixel1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx1_usb_router_link_intf_cl= k =3D { + .halt_reg =3D 0x8078, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8078, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx1_usb_router_link_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_esc0_clk =3D { + .halt_reg =3D 0x8044, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_esc0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_esc0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_esc1_clk =3D { + .halt_reg =3D 0x8048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_esc1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_esc1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_mdp1_clk =3D { + .halt_reg =3D 0x8014, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8014, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_mdp1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_mdp_clk =3D { + .halt_reg =3D 0x800c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x800c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_mdp_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_mdp_lut1_clk =3D { + .halt_reg =3D 0x8024, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x8024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_mdp_lut1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_mdp_lut_clk =3D { + .halt_reg =3D 0x801c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x801c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_mdp_lut_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_non_gdsc_ahb_clk =3D { + .halt_reg =3D 0xa004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xa004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_non_gdsc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_pclk0_clk =3D { + .halt_reg =3D 0x8004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_pclk0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_pclk0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_pclk1_clk =3D { + .halt_reg =3D 0x8008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_pclk1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_pclk1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_pll_lock_monitor_clk =3D { + .halt_reg =3D 0xe000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xe000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_pll_lock_monitor_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_rscc_ahb_clk =3D { + .halt_reg =3D 0xa00c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa00c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_rscc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_rscc_vsync_clk =3D { + .halt_reg =3D 0xa008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_rscc_vsync_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_vsync1_clk =3D { + .halt_reg =3D 0x8030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_vsync1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_vsync_clk =3D { + .halt_reg =3D 0x802c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x802c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_vsync_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_sm_obs_clk =3D { + .halt_reg =3D 0x11014, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0x11014, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_sm_obs_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc mdss_0_disp_cc_mdss_core_gdsc =3D { + .gdscr =3D 0x9000, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "mdss_0_disp_cc_mdss_core_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL, +}; + +static struct gdsc mdss_0_disp_cc_mdss_core_int2_gdsc =3D { + .gdscr =3D 0xd000, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "mdss_0_disp_cc_mdss_core_int2_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL, +}; + +static struct clk_regmap *disp_cc_0_sa8775p_clocks[] =3D { + [MDSS_DISP_CC_MDSS_AHB1_CLK] =3D &mdss_0_disp_cc_mdss_ahb1_clk.clkr, + [MDSS_DISP_CC_MDSS_AHB_CLK] =3D &mdss_0_disp_cc_mdss_ahb_clk.clkr, + [MDSS_DISP_CC_MDSS_AHB_CLK_SRC] =3D &mdss_0_disp_cc_mdss_ahb_clk_src.clkr, + [MDSS_DISP_CC_MDSS_BYTE0_CLK] =3D &mdss_0_disp_cc_mdss_byte0_clk.clkr, + [MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC] =3D &mdss_0_disp_cc_mdss_byte0_clk_src.= clkr, + [MDSS_DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] =3D &mdss_0_disp_cc_mdss_byte0_div_= clk_src.clkr, + [MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK] =3D &mdss_0_disp_cc_mdss_byte0_intf_cl= k.clkr, + [MDSS_DISP_CC_MDSS_BYTE1_CLK] =3D &mdss_0_disp_cc_mdss_byte1_clk.clkr, + [MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC] =3D &mdss_0_disp_cc_mdss_byte1_clk_src.= clkr, + [MDSS_DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] =3D &mdss_0_disp_cc_mdss_byte1_div_= clk_src.clkr, + [MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK] =3D &mdss_0_disp_cc_mdss_byte1_intf_cl= k.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK] =3D &mdss_0_disp_cc_mdss_dptx0_aux_clk.= clkr, + [MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] =3D &mdss_0_disp_cc_mdss_dptx0_aux_= clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK] =3D &mdss_0_disp_cc_mdss_dptx0_crypt= o_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK_SRC] =3D &mdss_0_disp_cc_mdss_dptx0_c= rypto_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK] =3D &mdss_0_disp_cc_mdss_dptx0_link_cl= k.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] =3D &mdss_0_disp_cc_mdss_dptx0_lin= k_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] =3D + &mdss_0_disp_cc_mdss_dptx0_link_div_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] =3D &mdss_0_disp_cc_mdss_dptx0_li= nk_intf_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK] =3D &mdss_0_disp_cc_mdss_dptx0_pixel= 0_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] =3D &mdss_0_disp_cc_mdss_dptx0_p= ixel0_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK] =3D &mdss_0_disp_cc_mdss_dptx0_pixel= 1_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] =3D &mdss_0_disp_cc_mdss_dptx0_p= ixel1_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK] =3D &mdss_0_disp_cc_mdss_dptx0_pixel= 2_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC] =3D &mdss_0_disp_cc_mdss_dptx0_p= ixel2_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK] =3D &mdss_0_disp_cc_mdss_dptx0_pixel= 3_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC] =3D &mdss_0_disp_cc_mdss_dptx0_p= ixel3_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] =3D + &mdss_0_disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK] =3D &mdss_0_disp_cc_mdss_dptx1_aux_clk.= clkr, + [MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] =3D &mdss_0_disp_cc_mdss_dptx1_aux_= clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK] =3D &mdss_0_disp_cc_mdss_dptx1_crypt= o_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK_SRC] =3D &mdss_0_disp_cc_mdss_dptx1_c= rypto_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK] =3D &mdss_0_disp_cc_mdss_dptx1_link_cl= k.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] =3D &mdss_0_disp_cc_mdss_dptx1_lin= k_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] =3D + &mdss_0_disp_cc_mdss_dptx1_link_div_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] =3D &mdss_0_disp_cc_mdss_dptx1_li= nk_intf_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK] =3D &mdss_0_disp_cc_mdss_dptx1_pixel= 0_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] =3D &mdss_0_disp_cc_mdss_dptx1_p= ixel0_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK] =3D &mdss_0_disp_cc_mdss_dptx1_pixel= 1_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] =3D &mdss_0_disp_cc_mdss_dptx1_p= ixel1_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] =3D + &mdss_0_disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr, + [MDSS_DISP_CC_MDSS_ESC0_CLK] =3D &mdss_0_disp_cc_mdss_esc0_clk.clkr, + [MDSS_DISP_CC_MDSS_ESC0_CLK_SRC] =3D &mdss_0_disp_cc_mdss_esc0_clk_src.cl= kr, + [MDSS_DISP_CC_MDSS_ESC1_CLK] =3D &mdss_0_disp_cc_mdss_esc1_clk.clkr, + [MDSS_DISP_CC_MDSS_ESC1_CLK_SRC] =3D &mdss_0_disp_cc_mdss_esc1_clk_src.cl= kr, + [MDSS_DISP_CC_MDSS_MDP1_CLK] =3D &mdss_0_disp_cc_mdss_mdp1_clk.clkr, + [MDSS_DISP_CC_MDSS_MDP_CLK] =3D &mdss_0_disp_cc_mdss_mdp_clk.clkr, + [MDSS_DISP_CC_MDSS_MDP_CLK_SRC] =3D &mdss_0_disp_cc_mdss_mdp_clk_src.clkr, + [MDSS_DISP_CC_MDSS_MDP_LUT1_CLK] =3D &mdss_0_disp_cc_mdss_mdp_lut1_clk.cl= kr, + [MDSS_DISP_CC_MDSS_MDP_LUT_CLK] =3D &mdss_0_disp_cc_mdss_mdp_lut_clk.clkr, + [MDSS_DISP_CC_MDSS_NON_GDSC_AHB_CLK] =3D &mdss_0_disp_cc_mdss_non_gdsc_ah= b_clk.clkr, + [MDSS_DISP_CC_MDSS_PCLK0_CLK] =3D &mdss_0_disp_cc_mdss_pclk0_clk.clkr, + [MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC] =3D &mdss_0_disp_cc_mdss_pclk0_clk_src.= clkr, + [MDSS_DISP_CC_MDSS_PCLK1_CLK] =3D &mdss_0_disp_cc_mdss_pclk1_clk.clkr, + [MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC] =3D &mdss_0_disp_cc_mdss_pclk1_clk_src.= clkr, + [MDSS_DISP_CC_MDSS_PLL_LOCK_MONITOR_CLK] =3D &mdss_0_disp_cc_mdss_pll_loc= k_monitor_clk.clkr, + [MDSS_DISP_CC_MDSS_RSCC_AHB_CLK] =3D &mdss_0_disp_cc_mdss_rscc_ahb_clk.cl= kr, + [MDSS_DISP_CC_MDSS_RSCC_VSYNC_CLK] =3D &mdss_0_disp_cc_mdss_rscc_vsync_cl= k.clkr, + [MDSS_DISP_CC_MDSS_VSYNC1_CLK] =3D &mdss_0_disp_cc_mdss_vsync1_clk.clkr, + [MDSS_DISP_CC_MDSS_VSYNC_CLK] =3D &mdss_0_disp_cc_mdss_vsync_clk.clkr, + [MDSS_DISP_CC_MDSS_VSYNC_CLK_SRC] =3D &mdss_0_disp_cc_mdss_vsync_clk_src.= clkr, + [MDSS_DISP_CC_PLL0] =3D &mdss_0_disp_cc_pll0.clkr, + [MDSS_DISP_CC_PLL1] =3D &mdss_0_disp_cc_pll1.clkr, + [MDSS_DISP_CC_SLEEP_CLK_SRC] =3D &mdss_0_disp_cc_sleep_clk_src.clkr, + [MDSS_DISP_CC_SM_OBS_CLK] =3D &mdss_0_disp_cc_sm_obs_clk.clkr, + [MDSS_DISP_CC_XO_CLK_SRC] =3D &mdss_0_disp_cc_xo_clk_src.clkr, +}; + +static struct gdsc *disp_cc_0_sa8775p_gdscs[] =3D { + [MDSS_DISP_CC_MDSS_CORE_GDSC] =3D &mdss_0_disp_cc_mdss_core_gdsc, + [MDSS_DISP_CC_MDSS_CORE_INT2_GDSC] =3D &mdss_0_disp_cc_mdss_core_int2_gds= c, +}; + +static const struct qcom_reset_map disp_cc_0_sa8775p_resets[] =3D { + [MDSS_DISP_CC_MDSS_CORE_BCR] =3D { 0x8000 }, + [MDSS_DISP_CC_MDSS_RSCC_BCR] =3D { 0xa000 }, +}; + +static const struct regmap_config disp_cc_0_sa8775p_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x12414, + .fast_io =3D true, +}; + +static struct qcom_cc_desc disp_cc_0_sa8775p_desc =3D { + .config =3D &disp_cc_0_sa8775p_regmap_config, + .clks =3D disp_cc_0_sa8775p_clocks, + .num_clks =3D ARRAY_SIZE(disp_cc_0_sa8775p_clocks), + .resets =3D disp_cc_0_sa8775p_resets, + .num_resets =3D ARRAY_SIZE(disp_cc_0_sa8775p_resets), + .gdscs =3D disp_cc_0_sa8775p_gdscs, + .num_gdscs =3D ARRAY_SIZE(disp_cc_0_sa8775p_gdscs), +}; + +static const struct of_device_id disp_cc_0_sa8775p_match_table[] =3D { + { .compatible =3D "qcom,sa8775p-dispcc0" }, + { } +}; +MODULE_DEVICE_TABLE(of, disp_cc_0_sa8775p_match_table); + +static int disp_cc_0_sa8775p_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + ret =3D devm_pm_runtime_enable(&pdev->dev); + if (ret) + return ret; + + ret =3D pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; + + regmap =3D qcom_cc_map(pdev, &disp_cc_0_sa8775p_desc); + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); + return PTR_ERR(regmap); + } + + clk_lucid_evo_pll_configure(&mdss_0_disp_cc_pll0, regmap, &mdss_0_disp_cc= _pll0_config); + clk_lucid_evo_pll_configure(&mdss_0_disp_cc_pll1, regmap, &mdss_0_disp_cc= _pll1_config); + + /* Keep some clocks always enabled */ + qcom_branch_set_clk_en(regmap, 0xc070); /* MDSS_0_DISP_CC_SLEEP_CLK */ + qcom_branch_set_clk_en(regmap, 0xc054); /* MDSS_0_DISP_CC_XO_CLK */ + + ret =3D qcom_cc_really_probe(&pdev->dev, &disp_cc_0_sa8775p_desc, regmap); + + pm_runtime_put(&pdev->dev); + + return ret; +} + +static struct platform_driver disp_cc_0_sa8775p_driver =3D { + .probe =3D disp_cc_0_sa8775p_probe, + .driver =3D { + .name =3D "dispcc0-sa8775p", + .of_match_table =3D disp_cc_0_sa8775p_match_table, + }, +}; + +module_platform_driver(disp_cc_0_sa8775p_driver); + +MODULE_DESCRIPTION("QTI DISPCC0 SA8775P Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/qcom/dispcc1-sa8775p.c b/drivers/clk/qcom/dispcc1-= sa8775p.c new file mode 100644 index 0000000000000000000000000000000000000000..30ccea59415a4e1df3e6eafcb1a= c37dab0d50be5 --- /dev/null +++ b/drivers/clk/qcom/dispcc1-sa8775p.c @@ -0,0 +1,1481 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_IFACE, + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_SLEEP_CLK, + DT_DP0_PHY_PLL_LINK_CLK, + DT_DP0_PHY_PLL_VCO_DIV_CLK, + DT_DP1_PHY_PLL_LINK_CLK, + DT_DP1_PHY_PLL_VCO_DIV_CLK, + DT_DSI0_PHY_PLL_OUT_BYTECLK, + DT_DSI0_PHY_PLL_OUT_DSICLK, + DT_DSI1_PHY_PLL_OUT_BYTECLK, + DT_DSI1_PHY_PLL_OUT_DSICLK, +}; + +enum { + P_BI_TCXO, + P_DP0_PHY_PLL_LINK_CLK, + P_DP0_PHY_PLL_VCO_DIV_CLK, + P_DP1_PHY_PLL_LINK_CLK, + P_DP1_PHY_PLL_VCO_DIV_CLK, + P_DSI0_PHY_PLL_OUT_BYTECLK, + P_DSI0_PHY_PLL_OUT_DSICLK, + P_DSI1_PHY_PLL_OUT_BYTECLK, + P_DSI1_PHY_PLL_OUT_DSICLK, + P_MDSS_1_DISP_CC_PLL0_OUT_MAIN, + P_MDSS_1_DISP_CC_PLL1_OUT_EVEN, + P_MDSS_1_DISP_CC_PLL1_OUT_MAIN, + P_SLEEP_CLK, +}; + +static const struct pll_vco lucid_evo_vco[] =3D { + { 249600000, 2020000000, 0 }, +}; + +static const struct alpha_pll_config mdss_1_disp_cc_pll0_config =3D { + .l =3D 0x3a, + .alpha =3D 0x9800, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x32aa299c, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00400805, +}; + +static struct clk_alpha_pll mdss_1_disp_cc_pll0 =3D { + .offset =3D 0x0, + .vco_table =3D lucid_evo_vco, + .num_vco =3D ARRAY_SIZE(lucid_evo_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct alpha_pll_config mdss_1_disp_cc_pll1_config =3D { + .l =3D 0x1f, + .alpha =3D 0x4000, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x32aa299c, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00400805, +}; + +static struct clk_alpha_pll mdss_1_disp_cc_pll1 =3D { + .offset =3D 0x1000, + .vco_table =3D lucid_evo_vco, + .num_vco =3D ARRAY_SIZE(lucid_evo_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_pll1", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct parent_map disp_cc_1_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_DP0_PHY_PLL_LINK_CLK, 1 }, + { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 }, + { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, +}; + +static const struct clk_parent_data disp_cc_1_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DP0_PHY_PLL_LINK_CLK }, + { .index =3D DT_DP0_PHY_PLL_VCO_DIV_CLK }, + { .index =3D DT_DP1_PHY_PLL_VCO_DIV_CLK }, +}; + +static const struct parent_map disp_cc_1_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, + { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, + { P_DSI1_PHY_PLL_OUT_DSICLK, 3 }, + { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, +}; + +static const struct clk_parent_data disp_cc_1_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DSI0_PHY_PLL_OUT_DSICLK }, + { .index =3D DT_DSI0_PHY_PLL_OUT_BYTECLK }, + { .index =3D DT_DSI1_PHY_PLL_OUT_DSICLK }, + { .index =3D DT_DSI1_PHY_PLL_OUT_BYTECLK }, +}; + +static const struct parent_map disp_cc_1_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data disp_cc_1_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, +}; + +static const struct clk_parent_data disp_cc_1_parent_data_2_ao[] =3D { + { .index =3D DT_BI_TCXO_AO }, +}; + +static const struct parent_map disp_cc_1_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, + { P_DP0_PHY_PLL_LINK_CLK, 1 }, + { P_DP1_PHY_PLL_LINK_CLK, 2 }, +}; + +static const struct clk_parent_data disp_cc_1_parent_data_3[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DP0_PHY_PLL_LINK_CLK }, + { .index =3D DT_DP1_PHY_PLL_LINK_CLK }, +}; + +static const struct parent_map disp_cc_1_parent_map_4[] =3D { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, + { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, +}; + +static const struct clk_parent_data disp_cc_1_parent_data_4[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DSI0_PHY_PLL_OUT_BYTECLK }, + { .index =3D DT_DSI1_PHY_PLL_OUT_BYTECLK }, +}; + +static const struct parent_map disp_cc_1_parent_map_5[] =3D { + { P_BI_TCXO, 0 }, + { P_MDSS_1_DISP_CC_PLL1_OUT_MAIN, 4 }, + { P_MDSS_1_DISP_CC_PLL1_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data disp_cc_1_parent_data_5[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &mdss_1_disp_cc_pll1.clkr.hw }, + { .hw =3D &mdss_1_disp_cc_pll1.clkr.hw }, +}; + +static const struct parent_map disp_cc_1_parent_map_6[] =3D { + { P_BI_TCXO, 0 }, + { P_MDSS_1_DISP_CC_PLL0_OUT_MAIN, 1 }, + { P_MDSS_1_DISP_CC_PLL1_OUT_MAIN, 4 }, + { P_MDSS_1_DISP_CC_PLL1_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data disp_cc_1_parent_data_6[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &mdss_1_disp_cc_pll0.clkr.hw }, + { .hw =3D &mdss_1_disp_cc_pll1.clkr.hw }, + { .hw =3D &mdss_1_disp_cc_pll1.clkr.hw }, +}; + +static const struct parent_map disp_cc_1_parent_map_7[] =3D { + { P_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data disp_cc_1_parent_data_7_ao[] =3D { + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct freq_tbl ftbl_mdss_1_disp_cc_mdss_ahb_clk_src[] =3D { + F(37500000, P_MDSS_1_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0), + F(75000000, P_MDSS_1_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0), + { } +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_ahb_clk_src =3D { + .cmd_rcgr =3D 0x824c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_5, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_ahb_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_ahb_clk_src", + .parent_data =3D disp_cc_1_parent_data_5, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_5), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_mdss_1_disp_cc_mdss_byte0_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_byte0_clk_src =3D { + .cmd_rcgr =3D 0x80ec, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_1, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_byte0_clk_src", + .parent_data =3D disp_cc_1_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_byte1_clk_src =3D { + .cmd_rcgr =3D 0x8108, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_1, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_byte1_clk_src", + .parent_data =3D disp_cc_1_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx0_aux_clk_src =3D { + .cmd_rcgr =3D 0x81b8, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_2, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_aux_clk_src", + .parent_data =3D disp_cc_1_parent_data_2, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx0_crypto_clk_src =3D { + .cmd_rcgr =3D 0x8170, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_3, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_crypto_clk_src", + .parent_data =3D disp_cc_1_parent_data_3, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx0_link_clk_src =3D { + .cmd_rcgr =3D 0x8154, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_3, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_link_clk_src", + .parent_data =3D disp_cc_1_parent_data_3, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx0_pixel0_clk_src =3D { + .cmd_rcgr =3D 0x8188, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_0, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_pixel0_clk_src", + .parent_data =3D disp_cc_1_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx0_pixel1_clk_src =3D { + .cmd_rcgr =3D 0x81a0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_0, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_pixel1_clk_src", + .parent_data =3D disp_cc_1_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx0_pixel2_clk_src =3D { + .cmd_rcgr =3D 0x826c, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_0, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_pixel2_clk_src", + .parent_data =3D disp_cc_1_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx0_pixel3_clk_src =3D { + .cmd_rcgr =3D 0x8284, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_0, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_pixel3_clk_src", + .parent_data =3D disp_cc_1_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx1_aux_clk_src =3D { + .cmd_rcgr =3D 0x8234, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_2, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx1_aux_clk_src", + .parent_data =3D disp_cc_1_parent_data_2, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx1_crypto_clk_src =3D { + .cmd_rcgr =3D 0x821c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_3, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx1_crypto_clk_src", + .parent_data =3D disp_cc_1_parent_data_3, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx1_link_clk_src =3D { + .cmd_rcgr =3D 0x8200, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_3, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx1_link_clk_src", + .parent_data =3D disp_cc_1_parent_data_3, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx1_pixel0_clk_src =3D { + .cmd_rcgr =3D 0x81d0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_0, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx1_pixel0_clk_src", + .parent_data =3D disp_cc_1_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx1_pixel1_clk_src =3D { + .cmd_rcgr =3D 0x81e8, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_0, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx1_pixel1_clk_src", + .parent_data =3D disp_cc_1_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_esc0_clk_src =3D { + .cmd_rcgr =3D 0x8124, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_4, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_esc0_clk_src", + .parent_data =3D disp_cc_1_parent_data_4, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_4), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_esc1_clk_src =3D { + .cmd_rcgr =3D 0x813c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_4, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_esc1_clk_src", + .parent_data =3D disp_cc_1_parent_data_4, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_4), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_mdss_1_disp_cc_mdss_mdp_clk_src[] =3D { + F(375000000, P_MDSS_1_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(500000000, P_MDSS_1_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(575000000, P_MDSS_1_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(650000000, P_MDSS_1_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_mdp_clk_src =3D { + .cmd_rcgr =3D 0x80bc, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_6, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_mdp_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_mdp_clk_src", + .parent_data =3D disp_cc_1_parent_data_6, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_6), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_pclk0_clk_src =3D { + .cmd_rcgr =3D 0x808c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_1, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_pclk0_clk_src", + .parent_data =3D disp_cc_1_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_pixel_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_pclk1_clk_src =3D { + .cmd_rcgr =3D 0x80a4, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_1, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_pclk1_clk_src", + .parent_data =3D disp_cc_1_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_pixel_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_vsync_clk_src =3D { + .cmd_rcgr =3D 0x80d4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_2, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_vsync_clk_src", + .parent_data =3D disp_cc_1_parent_data_2, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_mdss_1_disp_cc_sleep_clk_src[] =3D { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 mdss_1_disp_cc_sleep_clk_src =3D { + .cmd_rcgr =3D 0xc058, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_7, + .freq_tbl =3D ftbl_mdss_1_disp_cc_sleep_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_sleep_clk_src", + .parent_data =3D disp_cc_1_parent_data_7_ao, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_7_ao), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_xo_clk_src =3D { + .cmd_rcgr =3D 0xc03c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_2, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_xo_clk_src", + .parent_data =3D disp_cc_1_parent_data_2_ao, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_2_ao), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div mdss_1_disp_cc_mdss_byte0_div_clk_src =3D { + .reg =3D 0x8104, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_byte0_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div mdss_1_disp_cc_mdss_byte1_div_clk_src =3D { + .reg =3D 0x8120, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_byte1_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_byte1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div mdss_1_disp_cc_mdss_dptx0_link_div_clk_src = =3D { + .reg =3D 0x816c, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_link_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx0_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div mdss_1_disp_cc_mdss_dptx1_link_div_clk_src = =3D { + .reg =3D 0x8218, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx1_link_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx1_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_ahb1_clk =3D { + .halt_reg =3D 0x8088, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8088, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_ahb1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_ahb_clk =3D { + .halt_reg =3D 0x8084, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8084, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_byte0_clk =3D { + .halt_reg =3D 0x8034, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_byte0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_byte0_intf_clk =3D { + .halt_reg =3D 0x8038, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8038, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_byte0_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_byte0_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_byte1_clk =3D { + .halt_reg =3D 0x803c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x803c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_byte1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_byte1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_byte1_intf_clk =3D { + .halt_reg =3D 0x8040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_byte1_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_byte1_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx0_aux_clk =3D { + .halt_reg =3D 0x805c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x805c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx0_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx0_crypto_clk =3D { + .halt_reg =3D 0x8058, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8058, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_crypto_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx0_crypto_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx0_link_clk =3D { + .halt_reg =3D 0x804c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x804c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_link_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx0_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx0_link_intf_clk =3D { + .halt_reg =3D 0x8050, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8050, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_link_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx0_pixel0_clk =3D { + .halt_reg =3D 0x8060, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8060, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_pixel0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx0_pixel1_clk =3D { + .halt_reg =3D 0x8064, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8064, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_pixel1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx0_pixel2_clk =3D { + .halt_reg =3D 0x8264, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8264, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_pixel2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx0_pixel2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx0_pixel3_clk =3D { + .halt_reg =3D 0x8268, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8268, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_pixel3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx0_pixel3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx0_usb_router_link_intf_cl= k =3D { + .halt_reg =3D 0x8054, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8054, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_usb_router_link_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx1_aux_clk =3D { + .halt_reg =3D 0x8080, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8080, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx1_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx1_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx1_crypto_clk =3D { + .halt_reg =3D 0x807c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x807c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx1_crypto_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx1_crypto_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx1_link_clk =3D { + .halt_reg =3D 0x8070, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8070, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx1_link_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx1_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx1_link_intf_clk =3D { + .halt_reg =3D 0x8074, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8074, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx1_link_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx1_pixel0_clk =3D { + .halt_reg =3D 0x8068, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx1_pixel0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx1_pixel1_clk =3D { + .halt_reg =3D 0x806c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x806c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx1_pixel1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx1_usb_router_link_intf_cl= k =3D { + .halt_reg =3D 0x8078, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8078, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx1_usb_router_link_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_esc0_clk =3D { + .halt_reg =3D 0x8044, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_esc0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_esc0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_esc1_clk =3D { + .halt_reg =3D 0x8048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_esc1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_esc1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_mdp1_clk =3D { + .halt_reg =3D 0x8014, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8014, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_mdp1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_mdp_clk =3D { + .halt_reg =3D 0x800c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x800c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_mdp_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_mdp_lut1_clk =3D { + .halt_reg =3D 0x8024, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x8024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_mdp_lut1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_mdp_lut_clk =3D { + .halt_reg =3D 0x801c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x801c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_mdp_lut_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_non_gdsc_ahb_clk =3D { + .halt_reg =3D 0xa004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xa004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_non_gdsc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_pclk0_clk =3D { + .halt_reg =3D 0x8004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_pclk0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_pclk0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_pclk1_clk =3D { + .halt_reg =3D 0x8008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_pclk1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_pclk1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_pll_lock_monitor_clk =3D { + .halt_reg =3D 0xe000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xe000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_pll_lock_monitor_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_rscc_ahb_clk =3D { + .halt_reg =3D 0xa00c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa00c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_rscc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_rscc_vsync_clk =3D { + .halt_reg =3D 0xa008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_rscc_vsync_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_vsync1_clk =3D { + .halt_reg =3D 0x8030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_vsync1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_vsync_clk =3D { + .halt_reg =3D 0x802c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x802c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_vsync_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_sm_obs_clk =3D { + .halt_reg =3D 0x11014, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0x11014, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_sm_obs_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc mdss_1_disp_cc_mdss_core_gdsc =3D { + .gdscr =3D 0x9000, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "mdss_1_disp_cc_mdss_core_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL, +}; + +static struct gdsc mdss_1_disp_cc_mdss_core_int2_gdsc =3D { + .gdscr =3D 0xd000, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "mdss_1_disp_cc_mdss_core_int2_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL, +}; + +static struct clk_regmap *disp_cc_1_sa8775p_clocks[] =3D { + [MDSS_DISP_CC_MDSS_AHB1_CLK] =3D &mdss_1_disp_cc_mdss_ahb1_clk.clkr, + [MDSS_DISP_CC_MDSS_AHB_CLK] =3D &mdss_1_disp_cc_mdss_ahb_clk.clkr, + [MDSS_DISP_CC_MDSS_AHB_CLK_SRC] =3D &mdss_1_disp_cc_mdss_ahb_clk_src.clkr, + [MDSS_DISP_CC_MDSS_BYTE0_CLK] =3D &mdss_1_disp_cc_mdss_byte0_clk.clkr, + [MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC] =3D &mdss_1_disp_cc_mdss_byte0_clk_src.= clkr, + [MDSS_DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] =3D &mdss_1_disp_cc_mdss_byte0_div_= clk_src.clkr, + [MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK] =3D &mdss_1_disp_cc_mdss_byte0_intf_cl= k.clkr, + [MDSS_DISP_CC_MDSS_BYTE1_CLK] =3D &mdss_1_disp_cc_mdss_byte1_clk.clkr, + [MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC] =3D &mdss_1_disp_cc_mdss_byte1_clk_src.= clkr, + [MDSS_DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] =3D &mdss_1_disp_cc_mdss_byte1_div_= clk_src.clkr, + [MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK] =3D &mdss_1_disp_cc_mdss_byte1_intf_cl= k.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK] =3D &mdss_1_disp_cc_mdss_dptx0_aux_clk.= clkr, + [MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] =3D &mdss_1_disp_cc_mdss_dptx0_aux_= clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK] =3D &mdss_1_disp_cc_mdss_dptx0_crypt= o_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK_SRC] =3D &mdss_1_disp_cc_mdss_dptx0_c= rypto_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK] =3D &mdss_1_disp_cc_mdss_dptx0_link_cl= k.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] =3D &mdss_1_disp_cc_mdss_dptx0_lin= k_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] =3D + &mdss_1_disp_cc_mdss_dptx0_link_div_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] =3D &mdss_1_disp_cc_mdss_dptx0_li= nk_intf_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK] =3D &mdss_1_disp_cc_mdss_dptx0_pixel= 0_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] =3D &mdss_1_disp_cc_mdss_dptx0_p= ixel0_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK] =3D &mdss_1_disp_cc_mdss_dptx0_pixel= 1_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] =3D &mdss_1_disp_cc_mdss_dptx0_p= ixel1_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK] =3D &mdss_1_disp_cc_mdss_dptx0_pixel= 2_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC] =3D &mdss_1_disp_cc_mdss_dptx0_p= ixel2_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK] =3D &mdss_1_disp_cc_mdss_dptx0_pixel= 3_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC] =3D &mdss_1_disp_cc_mdss_dptx0_p= ixel3_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] =3D + &mdss_1_disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK] =3D &mdss_1_disp_cc_mdss_dptx1_aux_clk.= clkr, + [MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] =3D &mdss_1_disp_cc_mdss_dptx1_aux_= clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK] =3D &mdss_1_disp_cc_mdss_dptx1_crypt= o_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK_SRC] =3D &mdss_1_disp_cc_mdss_dptx1_c= rypto_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK] =3D &mdss_1_disp_cc_mdss_dptx1_link_cl= k.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] =3D &mdss_1_disp_cc_mdss_dptx1_lin= k_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] =3D + &mdss_1_disp_cc_mdss_dptx1_link_div_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] =3D &mdss_1_disp_cc_mdss_dptx1_li= nk_intf_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK] =3D &mdss_1_disp_cc_mdss_dptx1_pixel= 0_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] =3D &mdss_1_disp_cc_mdss_dptx1_p= ixel0_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK] =3D &mdss_1_disp_cc_mdss_dptx1_pixel= 1_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] =3D &mdss_1_disp_cc_mdss_dptx1_p= ixel1_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] =3D + &mdss_1_disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr, + [MDSS_DISP_CC_MDSS_ESC0_CLK] =3D &mdss_1_disp_cc_mdss_esc0_clk.clkr, + [MDSS_DISP_CC_MDSS_ESC0_CLK_SRC] =3D &mdss_1_disp_cc_mdss_esc0_clk_src.cl= kr, + [MDSS_DISP_CC_MDSS_ESC1_CLK] =3D &mdss_1_disp_cc_mdss_esc1_clk.clkr, + [MDSS_DISP_CC_MDSS_ESC1_CLK_SRC] =3D &mdss_1_disp_cc_mdss_esc1_clk_src.cl= kr, + [MDSS_DISP_CC_MDSS_MDP1_CLK] =3D &mdss_1_disp_cc_mdss_mdp1_clk.clkr, + [MDSS_DISP_CC_MDSS_MDP_CLK] =3D &mdss_1_disp_cc_mdss_mdp_clk.clkr, + [MDSS_DISP_CC_MDSS_MDP_CLK_SRC] =3D &mdss_1_disp_cc_mdss_mdp_clk_src.clkr, + [MDSS_DISP_CC_MDSS_MDP_LUT1_CLK] =3D &mdss_1_disp_cc_mdss_mdp_lut1_clk.cl= kr, + [MDSS_DISP_CC_MDSS_MDP_LUT_CLK] =3D &mdss_1_disp_cc_mdss_mdp_lut_clk.clkr, + [MDSS_DISP_CC_MDSS_NON_GDSC_AHB_CLK] =3D &mdss_1_disp_cc_mdss_non_gdsc_ah= b_clk.clkr, + [MDSS_DISP_CC_MDSS_PCLK0_CLK] =3D &mdss_1_disp_cc_mdss_pclk0_clk.clkr, + [MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC] =3D &mdss_1_disp_cc_mdss_pclk0_clk_src.= clkr, + [MDSS_DISP_CC_MDSS_PCLK1_CLK] =3D &mdss_1_disp_cc_mdss_pclk1_clk.clkr, + [MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC] =3D &mdss_1_disp_cc_mdss_pclk1_clk_src.= clkr, + [MDSS_DISP_CC_MDSS_PLL_LOCK_MONITOR_CLK] =3D &mdss_1_disp_cc_mdss_pll_loc= k_monitor_clk.clkr, + [MDSS_DISP_CC_MDSS_RSCC_AHB_CLK] =3D &mdss_1_disp_cc_mdss_rscc_ahb_clk.cl= kr, + [MDSS_DISP_CC_MDSS_RSCC_VSYNC_CLK] =3D &mdss_1_disp_cc_mdss_rscc_vsync_cl= k.clkr, + [MDSS_DISP_CC_MDSS_VSYNC1_CLK] =3D &mdss_1_disp_cc_mdss_vsync1_clk.clkr, + [MDSS_DISP_CC_MDSS_VSYNC_CLK] =3D &mdss_1_disp_cc_mdss_vsync_clk.clkr, + [MDSS_DISP_CC_MDSS_VSYNC_CLK_SRC] =3D &mdss_1_disp_cc_mdss_vsync_clk_src.= clkr, + [MDSS_DISP_CC_PLL0] =3D &mdss_1_disp_cc_pll0.clkr, + [MDSS_DISP_CC_PLL1] =3D &mdss_1_disp_cc_pll1.clkr, + [MDSS_DISP_CC_SLEEP_CLK_SRC] =3D &mdss_1_disp_cc_sleep_clk_src.clkr, + [MDSS_DISP_CC_SM_OBS_CLK] =3D &mdss_1_disp_cc_sm_obs_clk.clkr, + [MDSS_DISP_CC_XO_CLK_SRC] =3D &mdss_1_disp_cc_xo_clk_src.clkr, +}; + +static struct gdsc *disp_cc_1_sa8775p_gdscs[] =3D { + [MDSS_DISP_CC_MDSS_CORE_GDSC] =3D &mdss_1_disp_cc_mdss_core_gdsc, + [MDSS_DISP_CC_MDSS_CORE_INT2_GDSC] =3D &mdss_1_disp_cc_mdss_core_int2_gds= c, +}; + +static const struct qcom_reset_map disp_cc_1_sa8775p_resets[] =3D { + [MDSS_DISP_CC_MDSS_CORE_BCR] =3D { 0x8000 }, + [MDSS_DISP_CC_MDSS_RSCC_BCR] =3D { 0xa000 }, +}; + +static const struct regmap_config disp_cc_1_sa8775p_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x12414, + .fast_io =3D true, +}; + +static struct qcom_cc_desc disp_cc_1_sa8775p_desc =3D { + .config =3D &disp_cc_1_sa8775p_regmap_config, + .clks =3D disp_cc_1_sa8775p_clocks, + .num_clks =3D ARRAY_SIZE(disp_cc_1_sa8775p_clocks), + .resets =3D disp_cc_1_sa8775p_resets, + .num_resets =3D ARRAY_SIZE(disp_cc_1_sa8775p_resets), + .gdscs =3D disp_cc_1_sa8775p_gdscs, + .num_gdscs =3D ARRAY_SIZE(disp_cc_1_sa8775p_gdscs), +}; + +static const struct of_device_id disp_cc_1_sa8775p_match_table[] =3D { + { .compatible =3D "qcom,sa8775p-dispcc1" }, + { } +}; +MODULE_DEVICE_TABLE(of, disp_cc_1_sa8775p_match_table); + +static int disp_cc_1_sa8775p_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + ret =3D devm_pm_runtime_enable(&pdev->dev); + if (ret) + return ret; + + ret =3D pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; + + regmap =3D qcom_cc_map(pdev, &disp_cc_1_sa8775p_desc); + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); + return PTR_ERR(regmap); + } + + clk_lucid_evo_pll_configure(&mdss_1_disp_cc_pll0, regmap, &mdss_1_disp_cc= _pll0_config); + clk_lucid_evo_pll_configure(&mdss_1_disp_cc_pll1, regmap, &mdss_1_disp_cc= _pll1_config); + + /* Keep some clocks always enabled */ + qcom_branch_set_clk_en(regmap, 0xc070); /* MDSS_1_DISP_CC_SLEEP_CLK */ + qcom_branch_set_clk_en(regmap, 0xc054); /* MDSS_1_DISP_CC_XO_CLK */ + + ret =3D qcom_cc_really_probe(&pdev->dev, &disp_cc_1_sa8775p_desc, regmap); + + pm_runtime_put(&pdev->dev); + + return ret; +} + +static struct platform_driver disp_cc_1_sa8775p_driver =3D { + .probe =3D disp_cc_1_sa8775p_probe, + .driver =3D { + .name =3D "dispcc1-sa8775p", + .of_match_table =3D disp_cc_1_sa8775p_match_table, + }, +}; + +module_platform_driver(disp_cc_1_sa8775p_driver); + +MODULE_DESCRIPTION("QTI DISPCC1 SA8775P Driver"); +MODULE_LICENSE("GPL"); --=20 2.45.2 From nobody Wed Nov 27 08:41:06 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 995741EF086; Thu, 10 Oct 2024 18:59:32 +0000 (UTC) Authentication-Results: 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qcom: Update sleep_clk frequency to 32000 on SA8775P Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241011-sa8775p-mm-v4-resend-patches-v5-7-4a9f17dc683a@quicinc.com> References: <20241011-sa8775p-mm-v4-resend-patches-v5-0-4a9f17dc683a@quicinc.com> In-Reply-To: <20241011-sa8775p-mm-v4-resend-patches-v5-0-4a9f17dc683a@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , , , Bartosz Golaszewski CC: , , , , Taniya Das , Konrad Dybcio X-Mailer: b4 0.15-dev-aa3f6 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: TEeV404CtAu70fxxI6rWdHswrfWRe2wj X-Proofpoint-GUID: TEeV404CtAu70fxxI6rWdHswrfWRe2wj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 suspectscore=0 spamscore=0 mlxscore=0 bulkscore=0 phishscore=0 mlxlogscore=919 lowpriorityscore=0 clxscore=1015 impostorscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410100125 The HW supported sleep_clk frequency on SA8775P is 32000, hence update the sleep_clk frequency with the correct value on SA8775P. Fixes: 603f96d4c9d0 ("arm64: dts: qcom: add initial support for qcom sa8775= p-ride") Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das --- arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/d= ts/qcom/sa8775p-ride.dtsi index 0c1b21def4b62cc65a693552983ec0bc7eec697d..adb71aeff339b564eb3acc42a38= bba2f03507508 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi @@ -517,7 +517,7 @@ &serdes1 { }; =20 &sleep_clk { - clock-frequency =3D <32764>; + clock-frequency =3D <32000>; }; =20 &spi16 { --=20 2.45.2 From nobody Wed Nov 27 08:41:06 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C83BA1EF0B8; Thu, 10 Oct 2024 18:59:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Reviewed-by: Jagadeesh Kona Signed-off-by: Taniya Das --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 57 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/sa8775p.dtsi index e8dbc8d820a64f45c62edebca7ce4583a5c716e0..e56a725128e5ec228133a1b008a= c2114a4682bef 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -3254,6 +3254,47 @@ llcc: system-cache-controller@9200000 { interrupts =3D ; }; =20 + videocc: clock-controller@abf0000 { + compatible =3D "qcom,sa8775p-videocc"; + reg =3D <0x0 0x0abf0000 0x0 0x10000>; + clocks =3D <&gcc GCC_VIDEO_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains =3D <&rpmhpd SA8775P_MMCX>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + camcc: clock-controller@ade0000 { + compatible =3D "qcom,sa8775p-camcc"; + reg =3D <0x0 0x0ade0000 0x0 0x20000>; + clocks =3D <&gcc GCC_CAMERA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains =3D <&rpmhpd SA8775P_MMCX>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + dispcc0: clock-controller@af00000 { + compatible =3D "qcom,sa8775p-dispcc0"; + reg =3D <0x0 0x0af00000 0x0 0x20000>; + clocks =3D <&gcc GCC_DISP_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <0>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>; + power-domains =3D <&rpmhpd SA8775P_MMCX>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + pdc: interrupt-controller@b220000 { compatible =3D "qcom,sa8775p-pdc", "qcom,pdc"; reg =3D <0x0 0x0b220000 0x0 0x30000>, @@ -3876,6 +3917,22 @@ IPCC_MPROC_SIGNAL_GLINK_QMP }; }; =20 + dispcc1: clock-controller@22100000 { + compatible =3D "qcom,sa8775p-dispcc1"; + reg =3D <0x0 0x22100000 0x0 0x20000>; + clocks =3D <&gcc GCC_DISP_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <0>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>; + power-domains =3D <&rpmhpd SA8775P_MMCX>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + status =3D "disabled"; + }; + ethernet1: ethernet@23000000 { compatible =3D "qcom,sa8775p-ethqos"; reg =3D <0x0 0x23000000 0x0 0x10000>, --=20 2.45.2