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Shenoy" , "Mario Limonciello" , Perry Yuan , , , , , "Shyam Sundar S K" , Perry Yuan Subject: [PATCH v2 01/13] Documentation: x86: Add AMD Hardware Feedback Interface documentation Date: Thu, 10 Oct 2024 14:36:53 -0500 Message-ID: <20241010193705.10362-2-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241010193705.10362-1-mario.limonciello@amd.com> References: <20241010193705.10362-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C7:EE_|MW4PR12MB7432:EE_ X-MS-Office365-Filtering-Correlation-Id: 8fb3a611-7dd1-4b7b-3f06-08dce9630115 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?WpuNFDpOawt8jRBgGNAyw7LMiERFRn5OAEyDUUF3NtPbLN/YAqIsFCEYamez?= =?us-ascii?Q?SIbHzJhwEIAsf5vHv0VU7gBUrMhfKu9wuP7vRV9FFNWBhXgLFjMktAnQewVy?= =?us-ascii?Q?WV0js+yWbwboX9Hnxv1PDPO+7UL0TRJV69iLiUz2aGjDgcoTWM50kWlfgaUl?= =?us-ascii?Q?QXVfF3MkqTxifdAyS8RBjbtAXf83kGldmzZkKFiBTqQNfler9j2vpSCRi4Pq?= =?us-ascii?Q?7ykW/mBzTvAVguPdhTceqowmFRmDPFv5CMHtBPLgWQ/iU5ysYo1dGgevbtNy?= =?us-ascii?Q?9dE8zENtoC4qIH/1jRggECSqtNxoIMG1RIxtw8gsJsXF5pUdMG9nutpkHWEH?= =?us-ascii?Q?z5fSE/27upxGR2CPCq5l4SrmgBxRyjcx+x549ol9cZx8cOs9M5G/0rrtEekl?= =?us-ascii?Q?oDiazaVkMC5JqDPJyrJgdJGh8V8JjgK+pgmKFB8A4lMdJFfAYqnVKnnFAqqH?= =?us-ascii?Q?InqIylzMC4Nw8QYTRYKDvyXGn/KTr8pVeDmSGlWXbAiHSaVN6ndoBC82Oa7z?= =?us-ascii?Q?wBBIjdVFJsfsrsH1xZ1YyBCZIgjSOuozSRhgL/9aaSZ+IntIrIGqGCmdsCSs?= =?us-ascii?Q?DmNg+g4e7Y1ZB3+YVX3yeEOBZ5ea8BNLy9MeHDCSMMB9R7fNOFKGsRVCJGLJ?= =?us-ascii?Q?llBvG9adi3iute8QrPDmCNSgW/4rB24/h9icT60drxk7kySPacUI/Vn4WK38?= =?us-ascii?Q?Iol0mZygIWoMB30eioDXCOR2ZUoxS6pyvwicDdqKlxwkqL13ZMzgxFDZUEdk?= =?us-ascii?Q?aSBaEVRFgGCo2HxpEq1MabsazijRgixFA7BrmvQdnBG4ucDV9kxNybHoWODo?= =?us-ascii?Q?PRgPtUE8acILY1dtXV0JBGamN2CEYkiGOdKNh9fq4e0noKB8bwaVSC6Gj1NV?= =?us-ascii?Q?WIRXoEP7/kgFmQUx/ELL7zLYpXUaa6TMP/9GtqZQic9YyVKl4L7VKfEXxTiH?= =?us-ascii?Q?aqb8gttVvij6ZvAd+xV2olfao8LRxJZYf8ple4A/TRPneFRvE6tUIAhB1xXC?= =?us-ascii?Q?q/SGZ4dJsZYfjyDKblLfaIwe34ipjgI52rJgZ+Sn3M6+KaphOEkkvR+mYq04?= =?us-ascii?Q?hmWcQ5ykPprL6tcB8wXCyEH+JxWFfdLivCLnjWHzf/BiAT12Ksg4UDk2JJP6?= =?us-ascii?Q?a8V0oW5g7BYJyO//jWNKrBcShyF8aXQiEAOhsL1vdC3h9dsKzEdZVYpgmonR?= =?us-ascii?Q?ViO+uo5hcpgUf6AcUHE2pnotZSfqh6NudQk9HsxR86Lx48Z6poIPpLLo8J80?= =?us-ascii?Q?Xn2mEMJa8Elicb9EkAngCkT4FLnTqhpvFCdgDtOhu5/EX3oWnUSlRHVBWTl5?= =?us-ascii?Q?3pOc62YOgU0XuwXKcOL8PkH5W6gGFjEWFG5EKqZOGFUJh4Vl8hgxw35A1bf4?= =?us-ascii?Q?3KjFMy8MyfwN3Bn1Vyf5VTk3vt4x?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2024 19:37:40.8190 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8fb3a611-7dd1-4b7b-3f06-08dce9630115 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7432 Content-Type: text/plain; charset="utf-8" From: Perry Yuan Introduce a new documentation file, `amd_hfi.rst`, which delves into the implementation details of the AMD Hardware Feedback Interface and its associated driver, `amd_hfi`. This documentation describes how the driver provides hint to the OS scheduling which depends on the capability of core performance and efficiency ranking data. This documentation describes * The design of the driver * How the driver provides hints to the OS scheduling * How the driver interfaces with the kernel for efficiency ranking data. Signed-off-by: Perry Yuan Reviewed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- Documentation/arch/x86/amd-hfi.rst | 116 +++++++++++++++++++++++++++++ Documentation/arch/x86/index.rst | 1 + 2 files changed, 117 insertions(+) create mode 100644 Documentation/arch/x86/amd-hfi.rst diff --git a/Documentation/arch/x86/amd-hfi.rst b/Documentation/arch/x86/am= d-hfi.rst new file mode 100644 index 000000000000..351641ce2821 --- /dev/null +++ b/Documentation/arch/x86/amd-hfi.rst @@ -0,0 +1,116 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Hardware Feedback Interface For Hetero Core Scheduling On AMD Platform +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +:Copyright (C) 2024 Advanced Micro Devices, Inc. All Rights Reserved. + +:Author: Perry Yuan + +Overview +-------- + +AMD Heterogeneous Core implementations are comprised of more than one +architectural class and CPUs are comprised of cores of various efficiency +and power capabilities. Power management strategies must be designed to ac= commodate +the complexities introduced by incorporating different core types. +Heterogeneous systems can also extend to more than two architectural class= es as well. +The purpose of the scheduling feedback mechanism is to provide information= to +the operating system scheduler in real time such that the scheduler can di= rect +threads to the optimal core. + +``Classic cores`` are generally more performant and ``Dense cores`` are ge= nerally more +efficient. +The goal of AMD's heterogeneous architecture is to attain power benefit by= sending +background thread to the dense cores while sending high priority threads t= o the classic +cores. From a performance perspective, sending background threads to dense= cores can free +up power headroom and allow the classic cores to optimally service demandi= ng threads. +Furthermore, the area optimized nature of the dense cores allows for an in= creasing +number of physical cores. This improved core density will have positive mu= ltithreaded +performance impact. + +AMD Heterogeneous Core Driver +----------------------------- + +The ``amd_hfi`` driver delivers the operating system a performance and ene= rgy efficiency +capability data for each CPU in the system. The scheduler can use the rank= ing data +from the HFI driver to make task placement decisions. + +Thread Classification and Ranking Table Interaction +---------------------------------------------------- + +The thread classification is used to select into a ranking table that desc= ribes +an efficiency and performance ranking for each classification. + +Threads are classified during runtime into enumerated classes. The classes= represent +thread performance/power characteristics that may benefit from special sch= eduling behaviors. +The below table depicts an example of thread classification and a preferen= ce where a given thread +should be scheduled based on its thread class. The real time thread classi= fication is consumed +by the operating system and is used to inform the scheduler of where the t= hread should be placed. + +Thread Classification Example Table +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ++----------+----------------+-------------------------------+-------------= --------+---------+ +| class ID | Classification | Preferred scheduling behavior | Preemption p= riority | Counter | ++----------+----------------+-------------------------------+-------------= --------+---------+ +| 0 | Default | Performant | Highest = | | ++----------+----------------+-------------------------------+-------------= --------+---------+ +| 1 | Non-scalable | Efficient | Lowest = | PMCx1A1 | ++----------+----------------+-------------------------------+-------------= --------+---------+ +| 2 | I/O bound | Efficient | Lowest = | PMCx044 | ++----------+----------------+-------------------------------+-------------= --------+---------+ + + +AMD Hardware Feedback Interface +-------------------------------- + +The Hardware Feedback Interface provides to the operating system informati= on +about the performance and energy efficiency of each CPU in the system. Each +capability is given as a unit-less quantity in the range [0-255]. A higher +performance value indicates higher performance capability, and a higher +efficiency value indicates more efficiency. Energy efficiency and performa= nce +are reported in separate capabilities in the shared memory based ranking t= able. + +These capabilities may change at runtime as a result of changes in the +operating conditions of the system or the action of external factors. +Power Management FW is responsible for detecting events that would require +a reordering of the performance and efficiency ranking. Table updates would +happen relatively infrequently and occur on the time scale of seconds or m= ore. + +The mechanism used to trigger a table update like below events: + * Thermal Stress Events + * Silent Compute + * Extreme Low Battery Scenarios + +The kernel or a userspace policy daemon can use these capabilities to modi= fy +task placement decisions. For instance, if either the performance or energy +capabilities of a given logical processor becomes zero, it is an indicatio= n that +the hardware recommends to the operating system to not schedule any tasks = on +that processor for performance or energy efficiency reasons, respectively. + +Implementation details for Linux +-------------------------------- + +The implementation of threads scheduling consists of the following steps: + +1. A thread is spawned and scheduled to the ideal core using the default + heterogeneous scheduling policy. +2. The processor profiles thread execution and assigns an enumerated class= ification ID. + This classification is communicated to the OS via logical processor sco= pe MSR. +3. During the thread context switch out the operating system consumes the = workload(WL) + classification which resides in a logical processor scope MSR. +4. The OS triggers the hardware to clear its history by writing to an MSR, + after consuming the WL classification and before switching in the new t= hread. +5. If due to the classification, ranking table, and processor availability, + the thread is not on its ideal processor, the OS will then consider sch= eduling + the thread on its ideal processor (if available). + +Ranking Table update +--------------------------- +The power management firmware issues an platform interrupt after updating = the ranking +table and is ready for the operating system to consume it. CPUs receive su= ch interrupt +and read new ranking table from shared memory which PCCT table has provide= d, then +``amd_hfi`` driver parse the new table to provide new consume data for sch= eduling decisions. + + diff --git a/Documentation/arch/x86/index.rst b/Documentation/arch/x86/inde= x.rst index 8ac64d7de4dc..7f47229f3104 100644 --- a/Documentation/arch/x86/index.rst +++ b/Documentation/arch/x86/index.rst @@ -43,3 +43,4 @@ x86-specific Documentation features elf_auxvec xstate + amd_hfi --=20 2.43.0