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[130.111.218.24]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7b11497d7a4sm52529885a.118.2024.10.10.08.04.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Oct 2024 08:04:41 -0700 (PDT) From: Willow Cunningham X-Google-Original-From: Willow Cunningham To: Cc: willow.e.cunningham@maine.edu, Willow Cunningham , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Stefan Wahren , Andrea della Porta , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] arm64: dts: broadcom: Fix L2 linesize for Raspberry Pi 5 Date: Thu, 10 Oct 2024 11:04:07 -0400 Message-Id: <20241010150409.262087-1-willow.e.cunningham@maine.edu> X-Mailer: git-send-email 2.39.2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Willow Cunningham Fixes: faa3381267d0 ("arm64: dts: broadcom: Add minimal support for Raspberry Pi 5") Set the cache-line-size parameter of the L2 cache for each core to the correct value of 64 bytes. Previously, the L2 cache line size was incorrectly set to 128 bytes for the Broadcom BCM2712. This causes validation tests for the Performance Application Programming Interface (PAPI) tool to fail as they depend on sysfs accurately reporting cache line sizes. The correct value of 64 bytes is stated in the official documentation of the ARM Cortex A-72, which is linked in the comments of arm64/boot/dts/broadcom/bcm2712.dtsi as the source for cache-line-size. Signed-off-by: Willow Cunningham --- arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dt= s/broadcom/bcm2712.dtsi index 6e5a984c1d4e..26a29e5e5078 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -67,7 +67,7 @@ cpu0: cpu@0 { l2_cache_l0: l2-cache-l0 { compatible =3D "cache"; cache-size =3D <0x80000>; - cache-line-size =3D <128>; + cache-line-size =3D <64>; cache-sets =3D <1024>; //512KiB(size)/64(line-size)=3D8192ways/8-way s= et cache-level =3D <2>; cache-unified; @@ -91,7 +91,7 @@ cpu1: cpu@1 { l2_cache_l1: l2-cache-l1 { compatible =3D "cache"; cache-size =3D <0x80000>; - cache-line-size =3D <128>; + cache-line-size =3D <64>; cache-sets =3D <1024>; //512KiB(size)/64(line-size)=3D8192ways/8-way s= et cache-level =3D <2>; cache-unified; @@ -115,7 +115,7 @@ cpu2: cpu@2 { l2_cache_l2: l2-cache-l2 { compatible =3D "cache"; cache-size =3D <0x80000>; - cache-line-size =3D <128>; + cache-line-size =3D <64>; cache-sets =3D <1024>; //512KiB(size)/64(line-size)=3D8192ways/8-way s= et cache-level =3D <2>; cache-unified; @@ -139,7 +139,7 @@ cpu3: cpu@3 { l2_cache_l3: l2-cache-l3 { compatible =3D "cache"; cache-size =3D <0x80000>; - cache-line-size =3D <128>; + cache-line-size =3D <64>; cache-sets =3D <1024>; //512KiB(size)/64(line-size)=3D8192ways/8-way s= et cache-level =3D <2>; cache-unified; --=20 2.39.2