From nobody Wed Nov 27 10:45:41 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54E5618FDBE; Thu, 10 Oct 2024 12:04:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728561847; cv=none; b=N1H1w6O+Lxp6mooG06AM+ZEjn5Lvv4YOgS9xrXFISfRKgUxkzFXWPrpJDK99uMBQJyhMn+0A8wDOxeBUKW9ZczDNkqPQa1i8/POk0Jc9R0k94Eb/n7sKPFFCQVu437O5WnZr5G61N2xp0oZpCk01pBgnZgvxd1D+VTEL912X624= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728561847; c=relaxed/simple; bh=xw6HVneEx8JYTYqdGhN1CmrkEfyjnYCH2FyHmFQQEfw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=j9+xKAf0hoQ3QsoYygHJWxmz8M8Dx+XvDY8FGqdiyZx1m7gWfsh3JVE+rCdu83lbuvRe6djzvB48EUt7T3ENAAm9beZB6LBpomruW0ryn449seSrkhfmr5Xgps56+YPuKLnJTQBeN06HAUqdoIunEMo/BxtAWymnjP9N+NfNbo4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=uMDXRfsc; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="uMDXRfsc" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1728561846; x=1760097846; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xw6HVneEx8JYTYqdGhN1CmrkEfyjnYCH2FyHmFQQEfw=; b=uMDXRfscYaT84ekfDoLwECWy7Gwkpgr82z53afgpdSzTfOsGSGtLn5Rt Cu/XV7aDysxj15mRBiiaj2Xp4enRloLbtCz9d/lfwyRJDlz0tgI62UGLW 71oGfMU83mSxzBfLmOLw3ZoTg2M6t+MgbxWZH6v+Dcys+WHAvCflEvXRJ VfkGMBfKHZ1cxy4DNp2NCLRqeGy31AvWkUgzvlvk2XkB2rKCLKt8orn2H Ooc0Tp5ri2v3r8XmJ+GTdpcdxxGZC0e2K3uQZa4uWIS5oyFAN5fJd3DdU 4OQbfhYtMgM7YcKfM0UeLjRib5jx9aw5RSVl/N8TeOG2TvkByXsQenGqv A==; X-CSE-ConnectionGUID: HppzaJTNQM6+vzf/dzZ9Bg== X-CSE-MsgGUID: UsldGa71SgqHL7oRvEeteQ== X-IronPort-AV: E=Sophos;i="6.11,192,1725346800"; d="scan'208";a="263902567" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Oct 2024 05:04:05 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 10 Oct 2024 05:04:03 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 10 Oct 2024 05:03:59 -0700 From: Varshini Rajendran To: , , , , , , , , CC: , Krzysztof Kozlowski Subject: [PATCH v8 1/9] dt-bindings: atmel-ssc: add microchip,sam9x7-ssc Date: Thu, 10 Oct 2024 17:33:45 +0530 Message-ID: <20241010120345.92844-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241010120142.92057-1-varshini.rajendran@microchip.com> References: <20241010120142.92057-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add microchip,sam9x7-ssc to DT bindings documentation. Signed-off-by: Varshini Rajendran Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/misc/atmel-ssc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/misc/atmel-ssc.txt b/Documen= tation/devicetree/bindings/misc/atmel-ssc.txt index f9fb412642fe..894875826de9 100644 --- a/Documentation/devicetree/bindings/misc/atmel-ssc.txt +++ b/Documentation/devicetree/bindings/misc/atmel-ssc.txt @@ -2,6 +2,7 @@ =20 Required properties: - compatible: "atmel,at91rm9200-ssc" or "atmel,at91sam9g45-ssc" + or "microchip,sam9x7-ssc", "atmel,at91sam9g45-ssc" - atmel,at91rm9200-ssc: support pdc transfer - atmel,at91sam9g45-ssc: support dma transfer - reg: Should contain SSC registers location and length --=20 2.25.1 From nobody Wed Nov 27 10:45:41 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C56F71C32E1; Thu, 10 Oct 2024 12:04:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728561892; cv=none; b=aCsNTGV8VamME0zgKr9sZI1PmEvdWfKo39tRpkFc0gQlW7plyvh1mNCT0M5y6uzL/yDSpl1aDla2/DgVp7tOwzOVoG/ae7/Yfwkp2U8LpnzPfTxaQI7frT2xs5ig9ppqj+N5zkCOBvK/dOT35EmBzqp68v4WwRKsPMPZrMZ1vTs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728561892; c=relaxed/simple; bh=yUcQ0ZEyongp+UxISXeLzvhZd4sbwkjQc1piPm4hlnw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=GVCegw9OGAjb9XoerkceXXesVJh/1GRm04SKtzdO74Dsvg1zEptW/aCRcgOdaECLGudYgsfsL28FHpGPrNb+ql4/bq6T9DaWv3CThN2u+LzRJJreOsnxwFYtCMZUxYYUxUnp02d/S0e5K80wRlyDMkApyMVynq3otUpfkgqZ2Ko= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=GkEh6PcB; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="GkEh6PcB" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1728561890; x=1760097890; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yUcQ0ZEyongp+UxISXeLzvhZd4sbwkjQc1piPm4hlnw=; b=GkEh6PcBi9x71wFUIkTlB5ONOzpguZ5FzvwxEBj3jBEFcc0DsEyIYZA9 RFJtRsFIXdqQxh2446zO/xlgrgcIO83kCMESQ/e7mmadqoRusU8oaOlhD D0djJ4/4irRHtWQ6m1y90fYgQ8kIiAylct9xLgFA5UEg9MVjuG9rAv9xW Ct/VefemdqeOrhBhfy08oPnd4J1LkgN6ItVJr+13UAyfQOfnHE1pF8JEo DEwEwMurmoJlGYnFplQScWH5gzbGnsLRHbi7wy6udzak9Ao64Yj0cm1i3 ybDAUxsD3zjcAivzWh/yKwC1HYQdOz3qZ4t22sR0vDBTB++BlbrVtg1wN w==; X-CSE-ConnectionGUID: ZxWAeWSCQ2SoQSSTOPbs1w== X-CSE-MsgGUID: WomuFcCBQmyriIPh3L7eiQ== X-IronPort-AV: E=Sophos;i="6.11,192,1725346800"; d="scan'208";a="36169761" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Oct 2024 05:04:49 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 10 Oct 2024 05:04:09 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 10 Oct 2024 05:04:06 -0700 From: Varshini Rajendran To: , , , , , , CC: , Sebastian Reichel Subject: [PATCH v8 2/9] power: reset: at91-poweroff: lookup for proper pmc dt node for sam9x7 Date: Thu, 10 Oct 2024 17:34:04 +0530 Message-ID: <20241010120404.92893-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241010120142.92057-1-varshini.rajendran@microchip.com> References: <20241010120142.92057-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use sam9x7 pmc's compatible to lookup for in the SHDWC driver. Signed-off-by: Varshini Rajendran Acked-by: Sebastian Reichel Reviewed-by: Claudiu Beznea --- drivers/power/reset/at91-sama5d2_shdwc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c b/drivers/power/reset= /at91-sama5d2_shdwc.c index 959ce0dbe91d..2121d7e74e12 100644 --- a/drivers/power/reset/at91-sama5d2_shdwc.c +++ b/drivers/power/reset/at91-sama5d2_shdwc.c @@ -326,6 +326,7 @@ static const struct of_device_id at91_pmc_ids[] =3D { { .compatible =3D "atmel,sama5d2-pmc" }, { .compatible =3D "microchip,sam9x60-pmc" }, { .compatible =3D "microchip,sama7g5-pmc" }, + { .compatible =3D "microchip,sam9x7-pmc" }, { /* Sentinel. */ } }; =20 --=20 2.25.1 From nobody Wed Nov 27 10:45:41 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1FBD1C3F0F; Thu, 10 Oct 2024 12:04:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728561872; cv=none; b=hhYi5Th74cAkbVLBeQfPrR/3GrNexmKtUwdhkbElIje/T//VnRpzfCP4oZC04dXEzlcTOBOw5QcUANY4EcMyZhr0cZ2e+gaMBLhDW1jj0F8QtD+4lCCEsJtxlBJoLiSNLBjSHurRgdxLLRzgIcU7zqg+2rOV11cxG34W4VZWnAs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728561872; c=relaxed/simple; bh=O3y/VShkGNXjaRfTtcgUBvxcy3xSfxDmKATQfOBF9AA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=eVKijbgeD19L3T3P8xer0cbslw9g2o5B5r8TAhCg9zEGHhl3N0zPCNl1twM5+z9RFw3l+lB3rl5tlDlizU4A4jJhPGhMz/kDqVrande/0RYD6u6p6bUo0mxtPwW0M/ggNxwGGat+H3lQjh0UeIl4vTkMnvuwanw5CsnjnB2D9BU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=mv6MYRH7; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="mv6MYRH7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1728561870; x=1760097870; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=O3y/VShkGNXjaRfTtcgUBvxcy3xSfxDmKATQfOBF9AA=; b=mv6MYRH7up16rMyB8DiWoVaa8R4eNOGD0GcKj2U+GrPifb9f4xdHSxHQ FcxvQRO9F5FxGIuCx08YrIrS8/vNEuqxN5sX2o5nmWMUgpNxt4x73e9qj GfKiZ9ixefBCyrXYwFxvOHF60QPhAsPPCrDgr3d6PWZvPDFBO479bk97S RJM9rNtWuyurws/vbAiWLIdiRR2SNwp+lfO0C9IeRy1rAnID+SZJnfMda bsdy989DbNHFKy+jf1ct+HhWh6KR8XL6VIsFThkXZmRke04UGxPg+3PsE BsV9KQzKP1lnnsZF9z85wp0lRkCZtDfIn0CRdIGYrLqBp0Z5RcknlOz+I w==; X-CSE-ConnectionGUID: 1lIUCaNSTNeoxNzg3+OyyQ== X-CSE-MsgGUID: GBaSCdNwT6CMAZlFbWmEpw== X-IronPort-AV: E=Sophos;i="6.11,192,1725346800"; d="scan'208";a="263902594" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Oct 2024 05:04:30 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 10 Oct 2024 05:04:13 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 10 Oct 2024 05:04:11 -0700 From: Varshini Rajendran To: , , CC: , Sebastian Reichel , Claudiu Beznea Subject: [PATCH v8 3/9] power: reset: at91-reset: add reset support for sam9x7 SoC Date: Thu, 10 Oct 2024 17:34:10 +0530 Message-ID: <20241010120410.92942-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241010120142.92057-1-varshini.rajendran@microchip.com> References: <20241010120142.92057-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add power reset support for SAM9X7 SoC. Signed-off-by: Varshini Rajendran Acked-by: Sebastian Reichel Reviewed-by: Claudiu Beznea --- drivers/power/reset/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig index 389d5a193e5d..0c7cf3ef64b4 100644 --- a/drivers/power/reset/Kconfig +++ b/drivers/power/reset/Kconfig @@ -26,7 +26,7 @@ config POWER_RESET_AT91_POWEROFF config POWER_RESET_AT91_RESET tristate "Atmel AT91 reset driver" depends on ARCH_AT91 - default SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5 + default SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5 help This driver supports restart for Atmel AT91SAM9 and SAMA5 SoCs --=20 2.25.1 From nobody Wed Nov 27 10:45:41 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B9B531C3F3C; Thu, 10 Oct 2024 12:04:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728561901; cv=none; b=LXvWyszRct0xYGLmcwyvlLyni0h8zxaQr/n4D0IMPuOGY1BrkxILTgauZ0oSFwzGIm3znVikucNYxCsH+ufgL6U2+3PLAXk5+VEzg1sGWt0tAjTABGY6pkGBToopy0yH162riz7I9apFr/t4Y+ntzGZ2OM8whm5T1+RAuAKAHyg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728561901; c=relaxed/simple; bh=PYY7HbWS2/iy344q/VmYu01+VTW/EtBapdxiFaa8M/o=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=k4D/UIm47nJWwt9YEoOuBRmTa8HAlYg3SHNWBqYc3Bdeqac7dybfZ+ddwizHzRTm6lMnqu4WZt/HZg9XVoPTzG6YEAwpKa2/d0i7wt0iRVoy4JxEWoirhjXRTDo6QVEqMoV/B19f6xqUzCpbvijhqYJjXCCIXpodskPUlDzVt8Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=tPHQSt0W; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="tPHQSt0W" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1728561899; x=1760097899; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PYY7HbWS2/iy344q/VmYu01+VTW/EtBapdxiFaa8M/o=; b=tPHQSt0W7f9jrdcZzyf/oxD/MJ9IC/GF7+7VFE9ny5MgdEXFKvu1Vvce OpghJPRdpnBirv37wjuW5dGfxbrqkrdjLD2rHG0Xxefbec/TLuNCQw7cV sxVYEizJKNUIYnuHou8fnryJhVGaqkTt2MancJICQdJLd5nXcJt01eDY8 KHVm63cadzfAMX6UGxQ5fiBIAQ06cn7IvBzkWg5CKxLDnhVZPxiNmOtcj QuesevXpqDpViEsI8nn6plWoBQrZJs8j2NDR/TY3UE76nxE1bvj36FG5X UJbo25Mhflop4UEaGAdf6/FuzrnxNnqXhPfUX+lVneiz4NI+KImNxDVnc g==; X-CSE-ConnectionGUID: gR3ImswTTSW4aIPxRveY+Q== X-CSE-MsgGUID: wqqq0m9TRPyaqBPo0W+7PA== X-IronPort-AV: E=Sophos;i="6.11,192,1725346800"; d="scan'208";a="32664372" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Oct 2024 05:04:59 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 10 Oct 2024 05:04:18 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 10 Oct 2024 05:04:16 -0700 From: Varshini Rajendran To: , , CC: , Sebastian Reichel , Claudiu Beznea Subject: [PATCH v8 4/9] power: reset: at91-reset: add sdhwc support for sam9x7 SoC Date: Thu, 10 Oct 2024 17:34:14 +0530 Message-ID: <20241010120414.92993-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241010120142.92057-1-varshini.rajendran@microchip.com> References: <20241010120142.92057-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add shutdown controller support for SAM9X7 SoC. Signed-off-by: Varshini Rajendran Acked-by: Sebastian Reichel Reviewed-by: Claudiu Beznea --- drivers/power/reset/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig index 0c7cf3ef64b4..960717eed17e 100644 --- a/drivers/power/reset/Kconfig +++ b/drivers/power/reset/Kconfig @@ -34,7 +34,7 @@ config POWER_RESET_AT91_RESET config POWER_RESET_AT91_SAMA5D2_SHDWC tristate "Atmel AT91 SAMA5D2-Compatible shutdown controller driver" depends on ARCH_AT91 - default SOC_SAM9X60 || SOC_SAMA5 + default SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5 help This driver supports the alternate shutdown controller for some Atmel SAMA5 SoCs. It is present for example on SAMA5D2 SoC. --=20 2.25.1 From nobody Wed Nov 27 10:45:41 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C30F31C3F38; Thu, 10 Oct 2024 12:05:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728561932; cv=none; b=Bl04bNs1v205DhhhlxSur5OwvCMEVDHZVs0JcArA32fDaknTUJt70EcmYysT/8NZkw74qYbZaaKNYKiOKilROWbw+a1OqMcOfhTcCurowEVYEcWUxBKvzTM5ctC6iPL7VbU2Du13XFaVK2A0tPuZHiEHPpUHwq6uiNxuLpL/CyM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728561932; c=relaxed/simple; bh=8i5Z2KfBYTZAJwGXyHoxcKMWI4cBoFSSa/Wp6ippfD0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=B/bNYQ67tFDePrM4o2RpMGzIr/FuDFRSYd0ZeHujclr3INcd6c+3Akm/amGS0hNoJM+dzswnfvBCRgt5rAGA8AFDbwxExjy4DobkBf/6Eqvi6LG2g1B2sP8Asu32I2HONZ6lJ4zMRWETbLBVcegU8BUEiR0HN9+/rIJqQLIqmu4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=P9owJyML; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="P9owJyML" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1728561930; x=1760097930; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8i5Z2KfBYTZAJwGXyHoxcKMWI4cBoFSSa/Wp6ippfD0=; b=P9owJyMLBE+e9z311f4VAXm8Kgy3QjBpvrrZbfxMC5vNor4FnzkWQ1WW e18TN6n6GikAjeYSN82opmigdCMZZ/xb6svm5ykS7qhyu1iIoz63an0fS /JvYX7ioAX7kHP3CiP4z82dNk8VoXfn5brpyrH9jDdalWiuW7VvX6F0DI GERo/f2o6sxgjYikIZnhvfQyNLUmYx9gQ6LGFkNnXh6ZLw3JjMnjZ6UZl WLatrHWIowk33+grC2SxD/0lSsZJAdgHctiZXS1x2VFpeLpz0rAMWm/7v O/FUzPQ3GVh9eYVMiO+c9jHgoEn2OFrFjizyom0BBM/SOKTSziyoNIw1h g==; X-CSE-ConnectionGUID: cCb3ViA+RauNt3gRhi7X4Q== X-CSE-MsgGUID: GkBvXm0zSECJD9+cUnCpsQ== X-IronPort-AV: E=Sophos;i="6.11,192,1725346800"; d="scan'208";a="263902636" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Oct 2024 05:05:30 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 10 Oct 2024 05:04:24 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 10 Oct 2024 05:04:20 -0700 From: Varshini Rajendran To: , , , , , , , , , CC: , Krzysztof Kozlowski Subject: [PATCH v8 5/9] dt-bindings: reset: atmel,at91sam9260-reset: add sam9x7 Date: Thu, 10 Oct 2024 17:34:19 +0530 Message-ID: <20241010120419.93043-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241010120142.92057-1-varshini.rajendran@microchip.com> References: <20241010120142.92057-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add documentation for SAM9X7 reset controller. Signed-off-by: Varshini Rajendran Reviewed-by: Krzysztof Kozlowski Acked-by: Philipp Zabel --- .../devicetree/bindings/reset/atmel,at91sam9260-reset.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-rese= t.yaml b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.ya= ml index 98465d26949e..c3b33bbc7319 100644 --- a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml +++ b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml @@ -26,6 +26,10 @@ properties: - items: - const: atmel,sama5d3-rstc - const: atmel,at91sam9g45-rstc + - items: + - enum: + - microchip,sam9x7-rstc + - const: microchip,sam9x60-rstc =20 reg: minItems: 1 --=20 2.25.1 From nobody Wed Nov 27 10:45:41 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B63451C6F7A; Thu, 10 Oct 2024 12:05:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728561912; cv=none; b=YJeTHQA2COMFFoyuI2eErEdZRbYfzXqeL1AXv6yoaovn0fw27sMmxqi3fTqj7bAtBSuL0iuCZJKtxv++dnCHXViPTaYzerEPJUdf7yFJFlS80SI2pmA9FYu8joEV3hmt0w2/js340x1KLs9qbmCrhRZL+S4Jg64gl9AQUb7haD4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728561912; c=relaxed/simple; bh=flQEluk5hLljQfPymWhZA5C4pdYlqlYSYYtSaCbnjQ8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ftembV5LG80FQCfosmN5Tb2Bp5dvg1wwcA9tHv0ifxSn/gSa6NrUBFQGukXdvzsXrGnMec5+gwzVR92utTHAyzTlIilNImfY88U7E5dWzmBcu1BoRi4rdq0JMeolBx+/O+1GFrjXylSqu+yjAyLeTl29t4n5SrlcW7FiYVDZnEQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=t2uBbRyy; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="t2uBbRyy" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1728561910; x=1760097910; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=flQEluk5hLljQfPymWhZA5C4pdYlqlYSYYtSaCbnjQ8=; b=t2uBbRyyRLePpoVF8WTd4itS2En3N+sBvWzgevUrrq/71Swm2IY1VJ9B Z//lBpBZX/0tfaq45REGOfEfHo5wIWjz1jMvhs++Q4NpCCpD51dXRQXKY 1epFAOfQqdYF/GPfCZ84BZxAZmFoO5TMxSMMTwO2fyMmX+lecEXdeO7zb eqLh/dxOvL/bC0R34DKo3oc1udj6iozRlqDcWAaK3M+g/Dvvfrkb7hoEh KtEFek+Pa2BcgL/PBizfgRQRncNLWOjWmv57BUq42utyfXbpvOei50Cpt wFXqtSoWQGraM/LC5jzKlWVFrwnPGqPJ1d2yoHsxhqKyuF6o8yyE+gpej g==; X-CSE-ConnectionGUID: 6vPdQ8NYTmWaYmDn0yd8Nw== X-CSE-MsgGUID: 1WdRkE9yRD6MFDyWMKXKuw== X-IronPort-AV: E=Sophos;i="6.11,192,1725346800"; d="scan'208";a="263902615" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Oct 2024 05:05:10 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 10 Oct 2024 05:04:31 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 10 Oct 2024 05:04:27 -0700 From: Varshini Rajendran To: , , , , , , , , , , CC: , Krzysztof Kozlowski , Sebastian Reichel Subject: [PATCH v8 6/9] dt-bindings: power: reset: atmel,sama5d2-shdwc: add sam9x7 Date: Thu, 10 Oct 2024 17:34:25 +0530 Message-ID: <20241010120425.93102-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241010120142.92057-1-varshini.rajendran@microchip.com> References: <20241010120142.92057-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add shutdown controller DT bindings. Signed-off-by: Varshini Rajendran Reviewed-by: Krzysztof Kozlowski Acked-by: Sebastian Reichel --- .../devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-sh= dwc.yaml b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdw= c.yaml index 8c58e12cdb60..0735ceb7c103 100644 --- a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml +++ b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml @@ -22,6 +22,9 @@ properties: - enum: - atmel,sama5d2-shdwc - microchip,sam9x60-shdwc + - items: + - const: microchip,sam9x7-shdwc + - const: microchip,sam9x60-shdwc =20 reg: maxItems: 1 --=20 2.25.1 From nobody Wed Nov 27 10:45:41 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 549D91C460A; Thu, 10 Oct 2024 12:05:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728561903; cv=none; b=e+7l26/2zlq7w8KkB6LKwkfv9YuN4611ot+oAcuRb4aWXuwQ6QhxHowJ1igLA59hl+XKB7BqNti0cArPy3eydDfqla6oPRhTWriBaQk8MfC41yr0RhDRkI+0sZ3vnDWu30rPYxEN9p1azbPRlUnFrY0Nw5jVJZlEyPdzmDMGEbo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728561903; c=relaxed/simple; bh=BQ9b0jL/BQ/CW0zAYCLRRYvb+pK8BYqjHmAhlMSTERg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ESakF89IN3Ao9x5BVe6WS9XipEX3DkY5plfPjp0MTLTWcYOis+2Zn422hg27p+Oebi5Qb9vIxspPNAsmC9SB/0wxk2EC+aXhjtabqN8SnVGk6WgK31bK0XLo4Mb2G7XMgWA4jblznjz4bG0Yp/4R+i15shEuFT7mUbQq+9N1WJA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=GkF2o2N3; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="GkF2o2N3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1728561901; x=1760097901; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BQ9b0jL/BQ/CW0zAYCLRRYvb+pK8BYqjHmAhlMSTERg=; b=GkF2o2N3VGYhneqUFzJGjl0sWhaAdBwxxTuCKkqG50hOfcyAh3Z6PI7Q nhp7Ddnd1jj5we1KZlKdyyChWsoHxbB5FT1wUsJTXqrZ1WujZbe2jmcX/ 85tWVhPb3wMwML5zSFEVvr12qB5mremqR5buFpNevzhYVJ92xDy6FjT5H 3dYbJAdphi/8F0Hk3JLHTa/gYTs/jiE6sSmp2pFIMZPsX0Aa7+UkI43fW /smavIAKrpTXBtuF/eUcE5k0xTdO75XRdUf2ZjSIPxIhBinFGxIM0iemX R52wU+xvTJgdgvvK52iQCwwHgwUvIWCcXnAU/Kla76EVABxg5ZiQPexVO w==; X-CSE-ConnectionGUID: gR3ImswTTSW4aIPxRveY+Q== X-CSE-MsgGUID: DMDC3kGcR0C2sapSskDXBA== X-IronPort-AV: E=Sophos;i="6.11,192,1725346800"; d="scan'208";a="32664374" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Oct 2024 05:04:59 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 10 Oct 2024 05:04:36 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 10 Oct 2024 05:04:33 -0700 From: Varshini Rajendran To: , , , , , , , , CC: Subject: [PATCH v8 7/9] ARM: dts: at91: sam9x7: add device tree for SoC Date: Thu, 10 Oct 2024 17:34:32 +0530 Message-ID: <20241010120432.93151-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241010120142.92057-1-varshini.rajendran@microchip.com> References: <20241010120142.92057-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree file for SAM9X7 SoC family. Co-developed-by: Nicolas Ferre Signed-off-by: Nicolas Ferre Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/sam9x7.dtsi | 1220 +++++++++++++++++++++++ 1 file changed, 1220 insertions(+) create mode 100644 arch/arm/boot/dts/microchip/sam9x7.dtsi diff --git a/arch/arm/boot/dts/microchip/sam9x7.dtsi b/arch/arm/boot/dts/mi= crochip/sam9x7.dtsi new file mode 100644 index 000000000000..beb1f34b38d3 --- /dev/null +++ b/arch/arm/boot/dts/microchip/sam9x7.dtsi @@ -0,0 +1,1220 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sam9x7.dtsi - Device Tree Include file for Microchip SAM9X7 SoC family + * + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries + * + * Author: Varshini Rajendran + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + model =3D "Microchip SAM9X7 SoC"; + compatible =3D "microchip,sam9x7"; + #address-cells =3D <1>; + #size-cells =3D <1>; + interrupt-parent =3D <&aic>; + + aliases { + serial0 =3D &dbgu; + gpio0 =3D &pioA; + gpio1 =3D &pioB; + gpio2 =3D &pioC; + gpio3 =3D &pioD; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu@0 { + compatible =3D "arm,arm926ej-s"; + reg =3D <0>; + device_type =3D "cpu"; + }; + }; + + clocks { + slow_xtal: clock-slowxtal { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + main_xtal: clock-mainxtal { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + }; + + sram: sram@300000 { + compatible =3D "mmio-sram"; + reg =3D <0x300000 0x10000>; + ranges =3D <0 0x300000 0x10000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; + + ahb { + compatible =3D "simple-bus"; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + + sdmmc0: mmc@80000000 { + compatible =3D "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci"; + reg =3D <0x80000000 0x300>; + interrupts =3D <12 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>; + clock-names =3D "hclock", "multclk"; + assigned-clocks =3D <&pmc PMC_TYPE_GCK 12>; + assigned-clock-rates =3D <100000000>; + status =3D "disabled"; + }; + + sdmmc1: mmc@90000000 { + compatible =3D "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci"; + reg =3D <0x90000000 0x300>; + interrupts =3D <26 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>; + clock-names =3D "hclock", "multclk"; + assigned-clocks =3D <&pmc PMC_TYPE_GCK 26>; + assigned-clock-rates =3D <100000000>; + status =3D "disabled"; + }; + }; + + apb { + compatible =3D "simple-bus"; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + + flx4: flexcom@f0000000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf0000000 0x200>; + ranges =3D <0x0 0xf0000000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 13>; + status =3D "disabled"; + + uart4: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <13 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 13>; + clock-names =3D "usart"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + spi4: spi@400 { + compatible =3D "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <13 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 13>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c4: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <13 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 13>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx5: flexcom@f0004000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf0004000 0x200>; + ranges =3D <0x0 0xf0004000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 14>; + status =3D "disabled"; + + uart5: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <14 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names =3D "usart"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + spi5: spi@400 { + compatible =3D "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <14 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c5: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <14 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 14>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + dma0: dma-controller@f0008000 { + compatible =3D "microchip,sam9x7-dma", "atmel,sama5d4-dma"; + reg =3D <0xf0008000 0x1000>; + interrupts =3D <20 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 20>; + clock-names =3D "dma_clk"; + status =3D "disabled"; + }; + + ssc: ssc@f0010000 { + compatible =3D "microchip,sam9x7-ssc", "atmel,at91sam9g45-ssc"; + reg =3D <0xf0010000 0x4000>; + interrupts =3D <28 IRQ_TYPE_LEVEL_HIGH 5>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 28>; + clock-names =3D "pclk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(38))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(39))>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + i2s: i2s@f001c000 { + compatible =3D "microchip,sam9x7-i2smcc", "microchip,sam9x60-i2smcc"; + reg =3D <0xf001c000 0x100>; + interrupts =3D <34 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>; + clock-names =3D "pclk", "gclk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(36))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(37))>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + flx11: flexcom@f0020000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf0020000 0x200>; + ranges =3D <0x0 0xf0020000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 32>; + status =3D "disabled"; + + uart11: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <32 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 32>; + clock-names =3D "usart"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(22))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(23))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + i2c11: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <32 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 32>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(22))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(23))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx12: flexcom@f0024000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf0024000 0x200>; + ranges =3D <0x0 0xf0024000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 33>; + status =3D "disabled"; + + uart12: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <33 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 33>; + clock-names =3D "usart"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(24))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(25))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + i2c12: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <33 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 33>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(24))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(25))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + pit64b0: timer@f0028000 { + compatible =3D "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"; + reg =3D <0xf0028000 0x100>; + interrupts =3D <37 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>; + clock-names =3D "pclk", "gclk"; + }; + + sha: crypto@f002c000 { + compatible =3D "microchip,sam9x7-sha", "atmel,at91sam9g46-sha"; + reg =3D <0xf002c000 0x100>; + interrupts =3D <41 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 41>; + clock-names =3D "sha_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(34))>; + dma-names =3D "tx"; + }; + + trng: rng@f0030000 { + compatible =3D "microchip,sam9x7-trng", "microchip,sam9x60-trng"; + reg =3D <0xf0030000 0x100>; + interrupts =3D <38 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 38>; + status =3D "disabled"; + }; + + aes: crypto@f0034000 { + compatible =3D "microchip,sam9x7-aes", "atmel,at91sam9g46-aes"; + reg =3D <0xf0034000 0x100>; + interrupts =3D <39 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 39>; + clock-names =3D "aes_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(32))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(33))>; + dma-names =3D "tx", "rx"; + }; + + tdes: crypto@f0038000 { + compatible =3D "microchip,sam9x7-tdes", "atmel,at91sam9g46-tdes"; + reg =3D <0xf0038000 0x100>; + interrupts =3D <40 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 40>; + clock-names =3D "tdes_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(31))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(30))>; + dma-names =3D "tx", "rx"; + }; + + classd: sound@f003c000 { + compatible =3D "microchip,sam9x7-classd", "atmel,sama5d2-classd"; + reg =3D <0xf003c000 0x100>; + interrupts =3D <42 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>; + clock-names =3D "pclk", "gclk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(35))>; + dma-names =3D "tx"; + status =3D "disabled"; + }; + + pit64b1: timer@f0040000 { + compatible =3D "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"; + reg =3D <0xf0040000 0x100>; + interrupts =3D <58 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; + clock-names =3D "pclk", "gclk"; + }; + + can0: can@f8000000 { + compatible =3D "bosch,m_can"; + reg =3D <0xf8000000 0x100>, <0x300000 0x7800>; + reg-names =3D "m_can", "message_ram"; + interrupts =3D <29 IRQ_TYPE_LEVEL_HIGH 0>, + <68 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names =3D "int0", "int1"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_GCK 29>; + clock-names =3D "hclk", "cclk"; + assigned-clocks =3D <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 2= 9>; + assigned-clock-rates =3D <480000000>, <40000000>; + assigned-clock-parents =3D <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYP= E_CORE PMC_UTMI>; + bosch,mram-cfg =3D <0x3400 0 0 64 0 0 32 32>; + status =3D "disabled"; + }; + + can1: can@f8004000 { + compatible =3D "bosch,m_can"; + reg =3D <0xf8004000 0x100>, <0x300000 0xbc00>; + reg-names =3D "m_can", "message_ram"; + interrupts =3D <30 IRQ_TYPE_LEVEL_HIGH 0>, + <69 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names =3D "int0", "int1"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 30>, <&pmc PMC_TYPE_GCK 30>; + clock-names =3D "hclk", "cclk"; + assigned-clocks =3D <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 3= 0>; + assigned-clock-rates =3D <480000000>, <40000000>; + assigned-clock-parents =3D <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYP= E_CORE PMC_UTMI>; + bosch,mram-cfg =3D <0x7800 0 0 64 0 0 32 32>; + status =3D "disabled"; + }; + + tcb: timer@f8008000 { + compatible =3D "microchip,sam9x7-tcb","atmel,sama5d2-tcb", "simple-mfd"= , "syscon"; + reg =3D <0xf8008000 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D <17 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_GCK 17>, <&clk= 32k 0>; + clock-names =3D "t0_clk", "gclk", "slow_clk"; + }; + + flx6: flexcom@f8010000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf8010000 0x200>; + ranges =3D <0x0 0xf8010000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 9>; + status =3D "disabled"; + + uart6: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <9 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 9>; + clock-names =3D "usart"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + i2c6: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <9 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 9>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx7: flexcom@f8014000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf8014000 0x200>; + ranges =3D <0x0 0xf8014000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 10>; + status =3D "disabled"; + + uart7: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <10 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 10>; + clock-names =3D "usart"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + i2c7: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <10 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 10>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx8: flexcom@f8018000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf8018000 0x200>; + ranges =3D <0x0 0xf8018000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 11>; + status =3D "disabled"; + + uart8: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <11 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 11>; + clock-names =3D "usart"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + i2c8: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <11 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 11>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx0: flexcom@f801c000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf801c000 0x200>; + ranges =3D <0x0 0xf801c000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 5>; + status =3D "disabled"; + + uart0: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <5 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 5>; + clock-names =3D "usart"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + spi0: spi@400 { + compatible =3D "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <5 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 5>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c0: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <5 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 5>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx1: flexcom@f8020000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf8020000 0x200>; + ranges =3D <0x0 0xf8020000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 6>; + status =3D "disabled"; + + uart1: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <6 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 6>; + clock-names =3D "usart"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + spi1: spi@400 { + compatible =3D "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <6 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 6>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c1: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <6 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 6>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx2: flexcom@f8024000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf8024000 0x200>; + ranges =3D <0x0 0xf8024000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 7>; + status =3D "disabled"; + + uart2: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <7 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names =3D "usart"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + spi2: spi@400 { + compatible =3D "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <7 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c2: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <7 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx3: flexcom@f8028000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf8028000 0x200>; + ranges =3D <0x0 0xf8028000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 8>; + status =3D "disabled"; + + uart3: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <8 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names =3D "usart"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + spi3: spi@400 { + compatible =3D "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <8 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c3: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <8 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 8>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + gmac: ethernet@f802c000 { + compatible =3D "microchip,sam9x7-gem", "microchip,sama7g5-gem"; + reg =3D <0xf802c000 0x1000>; + interrupts =3D <24 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 0 */ + <60 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 1 */ + <61 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 2 */ + <62 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 3 */ + <63 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 4 */ + <64 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 5 */ + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>= , <&pmc PMC_TYPE_GCK 24>, <&pmc PMC_TYPE_GCK 67>; + clock-names =3D "hclk", "pclk", "tx_clk", "tsu_clk"; + assigned-clocks =3D <&pmc PMC_TYPE_GCK 67>; + assigned-clock-rates =3D <266666666>; + status =3D "disabled"; + }; + + pwm0: pwm@f8034000 { + compatible =3D "microchip,sam9x7-pwm", "microchip,sam9x60-pwm"; + reg =3D <0xf8034000 0x300>; + interrupts =3D <18 IRQ_TYPE_LEVEL_HIGH 4>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 18>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + flx9: flexcom@f8040000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf8040000 0x200>; + ranges =3D <0x0 0xf8040000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 15>; + status =3D "disabled"; + + uart9: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <15 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 15>; + clock-names =3D "usart"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + i2c9: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <15 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 15>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx10: flexcom@f8044000 { + compatible =3D "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xf8044000 0x200>; + ranges =3D <0x0 0xf8044000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 16>; + status =3D "disabled"; + + uart10: serial@200 { + compatible =3D "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <16 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 16>; + clock-names =3D "usart"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(21))>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + i2c10: i2c@600 { + compatible =3D "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <16 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 16>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(21))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + matrix: matrix@ffffde00 { + compatible =3D "microchip,sam9x7-matrix", "atmel,at91sam9x5-matrix", "s= yscon"; + reg =3D <0xffffde00 0x200>; + }; + + pmecc: ecc-engine@ffffe000 { + compatible =3D "microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc"; + reg =3D <0xffffe000 0x300>, <0xffffe600 0x100>; + }; + + mpddrc: mpddrc@ffffe800 { + compatible =3D "microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc"; + reg =3D <0xffffe800 0x200>; + clocks =3D <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>; + clock-names =3D "ddrck", "mpddr"; + }; + + smc: smc@ffffea00 { + compatible =3D "microchip,sam9x7-smc", "atmel,at91sam9260-smc", "syscon= "; + reg =3D <0xffffea00 0x100>; + }; + + aic: interrupt-controller@fffff100 { + compatible =3D "microchip,sam9x7-aic"; + reg =3D <0xfffff100 0x100>; + #interrupt-cells =3D <3>; + interrupt-controller; + atmel,external-irqs =3D <31>; + }; + + dbgu: serial@fffff200 { + compatible =3D "microchip,sam9x7-dbgu", "atmel,at91sam9260-dbgu", "micr= ochip,sam9x7-usart", "atmel,at91sam9260-usart"; + reg =3D <0xfffff200 0x200>; + interrupts =3D <47 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 47>; + clock-names =3D "usart"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(28))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(29))>; + dma-names =3D "tx", "rx"; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + pinctrl: pinctrl@fffff400 { + compatible =3D "microchip,sam9x7-pinctrl", "microchip,sam9x60-pinctrl",= "simple-mfd"; + ranges =3D <0xfffff400 0xfffff400 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + /* mux-mask corresponding to sam9x7 SoC in TFBGA228L package */ + atmel,mux-mask =3D < + /* A B C D */ + 0xffffffff 0xffffefc0 0xc0ffd000 0x00000000 /* pioA */ + 0x07ffffff 0x0805fe7f 0x01ff9f81 0x06078000 /* pioB */ + 0xffffffff 0x07dfffff 0xfa3fffff 0x00000000 /* pioC */ + 0x00003fff 0x00003fe0 0x0000003f 0x00000000 /* pioD */ + >; + + pioA: gpio@fffff400 { + compatible =3D "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atm= el,at91rm9200-gpio"; + reg =3D <0xfffff400 0x200>; + interrupts =3D <2 IRQ_TYPE_LEVEL_HIGH 1>; + #interrupt-cells =3D <2>; + interrupt-controller; + #gpio-cells =3D <2>; + gpio-controller; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 2>; + }; + + pioB: gpio@fffff600 { + compatible =3D "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atm= el,at91rm9200-gpio"; + reg =3D <0xfffff600 0x200>; + interrupts =3D <3 IRQ_TYPE_LEVEL_HIGH 1>; + #interrupt-cells =3D <2>; + interrupt-controller; + #gpio-cells =3D <2>; + gpio-controller; + #gpio-lines =3D <26>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 3>; + }; + + pioC: gpio@fffff800 { + compatible =3D "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atm= el,at91rm9200-gpio"; + reg =3D <0xfffff800 0x200>; + interrupts =3D <4 IRQ_TYPE_LEVEL_HIGH 1>; + #interrupt-cells =3D <2>; + interrupt-controller; + #gpio-cells =3D <2>; + gpio-controller; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 4>; + }; + + pioD: gpio@fffffa00 { + compatible =3D "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atm= el,at91rm9200-gpio"; + reg =3D <0xfffffa00 0x200>; + interrupts =3D <44 IRQ_TYPE_LEVEL_HIGH 1>; + #interrupt-cells =3D <2>; + interrupt-controller; + #gpio-cells =3D <2>; + gpio-controller; + #gpio-lines =3D <22>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 44>; + }; + }; + + pmc: clock-controller@fffffc00 { + compatible =3D "microchip,sam9x7-pmc", "syscon"; + reg =3D <0xfffffc00 0x200>; + interrupts =3D <1 IRQ_TYPE_LEVEL_HIGH 7>; + #clock-cells =3D <2>; + clocks =3D <&clk32k 1>, <&clk32k 0>, <&main_xtal>; + clock-names =3D "td_slck", "md_slck", "main_xtal"; + }; + + reset_controller: reset-controller@fffffe00 { + compatible =3D "microchip,sam9x7-rstc", "microchip,sam9x60-rstc"; + reg =3D <0xfffffe00 0x10>; + clocks =3D <&clk32k 0>; + }; + + poweroff: poweroff@fffffe10 { + compatible =3D "microchip,sam9x7-shdwc", "microchip,sam9x60-shdwc"; + reg =3D <0xfffffe10 0x10>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk32k 0>; + atmel,wakeup-rtc-timer; + atmel,wakeup-rtt-timer; + status =3D "disabled"; + }; + + rtt: rtc@fffffe20 { + compatible =3D "microchip,sam9x7-rtt", "atmel,at91sam9260-rtt"; + reg =3D <0xfffffe20 0x20>; + interrupts =3D <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&clk32k 0>; + }; + + clk32k: clock-controller@fffffe50 { + compatible =3D "microchip,sam9x7-sckc", "microchip,sam9x60-sckc"; + reg =3D <0xfffffe50 0x4>; + clocks =3D <&slow_xtal>; + #clock-cells =3D <1>; + }; + + gpbr: syscon@fffffe60 { + compatible =3D "microchip,sam9x7-gpbr", "atmel,at91sam9260-gpbr", "sysc= on"; + reg =3D <0xfffffe60 0x10>; + }; + + rtc: rtc@fffffea8 { + compatible =3D "microchip,sam9x7-rtc", "microchip,sam9x60-rtc"; + reg =3D <0xfffffea8 0x100>; + interrupts =3D <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&clk32k 0>; + }; + + watchdog: watchdog@ffffff80 { + compatible =3D "microchip,sam9x7-wdt", "microchip,sam9x60-wdt"; + reg =3D <0xffffff80 0x24>; + interrupts =3D <1 IRQ_TYPE_LEVEL_HIGH 7>; + status =3D "disabled"; + }; + }; +}; --=20 2.25.1 From nobody Wed Nov 27 10:45:41 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0E621C4635; Thu, 10 Oct 2024 12:05:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728561903; cv=none; b=bUKsi1gT+LJ6/ILHbbY4Cxx6uO/+mm4zpPVY6+UAFB2NmeK/Fm+zU4ILRgysm9gqAouD+5TzUd5os1IURGDx/Iz/QMCoNpHoByiirRUlS+KAjcRaSCJ8cXqHoHS5jXsw3xFLHR5hVOLnuKy2vr1HtzjNwBSn3zk+oFsIx2XSigY= ARC-Message-Signature: i=1; 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Thu, 10 Oct 2024 05:04:43 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 10 Oct 2024 05:04:40 -0700 From: Varshini Rajendran To: , , , , , , , , , , Subject: [PATCH v8 8/9] dt-bindings: arm: add sam9x75 curiosity board Date: Thu, 10 Oct 2024 17:34:38 +0530 Message-ID: <20241010120438.93201-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241010120142.92057-1-varshini.rajendran@microchip.com> References: <20241010120142.92057-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add documentation for SAM9X75 Curiosity board. Signed-off-by: Varshini Rajendran Acked-by: Rob Herring Reviewed-by: Claudiu Beznea --- Documentation/devicetree/bindings/arm/atmel-at91.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Docume= ntation/devicetree/bindings/arm/atmel-at91.yaml index 82f37328cc69..7160ec80ac1b 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml @@ -106,6 +106,12 @@ properties: - const: microchip,sam9x60 - const: atmel,at91sam9 =20 + - description: Microchip SAM9X7 Evaluation Boards + items: + - const: microchip,sam9x75-curiosity + - const: microchip,sam9x7 + - const: atmel,at91sam9 + - description: Nattis v2 board with Natte v2 power board items: - const: axentia,nattis-2 --=20 2.25.1 From nobody Wed Nov 27 10:45:41 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 551D31C5797; Thu, 10 Oct 2024 12:05:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728561905; cv=none; b=SV6SNHl7CkR+IJx1daq4KwFXZ6mWLTutFLSR40IT+jFGwZ6lebTqPqggeofCauOZQSJLDUGevHtVnTbHNm385Q9U33oY/ifMnjVn16+vMDXjdCIxlqSzjj9Vz8c5Po7Xn/+Dw+GmMiwLLPgU44XO42CUK/6uKzoP8KKEmoPNp9g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728561905; c=relaxed/simple; bh=pYm4Ktj0NXe7FFYDY1eyQ05P1eA1AobGAFOqQuCmjsQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MNP+Gk11Nsod0DkxozXwQpZ/Zmhvhz1+y4Wte561J08LmuQKPzmJqBM4fU8o+eqiRpluWJ/kO491BcZI8j0UBhUsqsx9gk6LSFCrP4p51f4vBRfyq5MV0hMf76eqOBvt9+NHByKAZoeEa5izHN3nJsU+K/URMo5KRKkBj6RmGN8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=HqeA2Knb; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="HqeA2Knb" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1728561903; x=1760097903; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pYm4Ktj0NXe7FFYDY1eyQ05P1eA1AobGAFOqQuCmjsQ=; b=HqeA2KnbghxY8JXP1zEmbREixgQAfO3X4pf4DR3S1UT79KB/3vAYE0cJ m6Qz5kmfo84SXCU+pwO2otCDf4m3PWHyB6ZFqxAP34011plXlCUK721Cc ImGI95slFjKYRXT0EjdkwSPSa5dOGxX6bxpRWiQSnxxG16ZAH4Ufayrbo Sm2UrmfIm58OPIfOA8LTNIkkdGAbDt1lV3EziA5s2vJmzBtk1bH2u1MJi aozNj2PVXLRhIiWc1sg4vkBZ1MWKEUasIhSPoJmLW6e9u8w5PaUIaSkZH C71kqhNWfFIQJIs0zEZ7XnXKHYCj+fUW3ERHwZER7NZlx1dq0jbH29Iho w==; X-CSE-ConnectionGUID: gR3ImswTTSW4aIPxRveY+Q== X-CSE-MsgGUID: UJzz08PlTje5SVOVUSXOwA== X-IronPort-AV: E=Sophos;i="6.11,192,1725346800"; d="scan'208";a="32664377" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Oct 2024 05:04:59 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 10 Oct 2024 05:04:50 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 10 Oct 2024 05:04:47 -0700 From: Varshini Rajendran To: , , , , , , , , CC: , Hari Prasath Gujulan Elango Subject: [PATCH v8 9/9] ARM: dts: microchip: sam9x75_curiosity: add sam9x75 curiosity board Date: Thu, 10 Oct 2024 17:34:44 +0530 Message-ID: <20241010120444.93252-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241010120142.92057-1-varshini.rajendran@microchip.com> References: <20241010120142.92057-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree file for sam9x75 curiosity board. Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea Reviewed-by: Hari Prasath Gujulan Elango --- arch/arm/boot/dts/microchip/Makefile | 3 + .../dts/microchip/at91-sam9x75_curiosity.dts | 324 ++++++++++++++++++ 2 files changed, 327 insertions(+) create mode 100644 arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts diff --git a/arch/arm/boot/dts/microchip/Makefile b/arch/arm/boot/dts/micro= chip/Makefile index 0c45c8d17468..470fe46433a9 100644 --- a/arch/arm/boot/dts/microchip/Makefile +++ b/arch/arm/boot/dts/microchip/Makefile @@ -2,6 +2,7 @@ # Enables support for device-tree overlays DTC_FLAGS_at91-sam9x60_curiosity :=3D -@ DTC_FLAGS_at91-sam9x60ek :=3D -@ +DTC_FLAGS_at91-sam9x75_curiosity :=3D -@ DTC_FLAGS_at91-sama5d27_som1_ek :=3D -@ DTC_FLAGS_at91-sama5d27_wlsom1_ek :=3D -@ DTC_FLAGS_at91-sama5d29_curiosity :=3D -@ @@ -60,6 +61,8 @@ dtb-$(CONFIG_SOC_AT91SAM9) +=3D \ dtb-$(CONFIG_SOC_SAM9X60) +=3D \ at91-sam9x60_curiosity.dtb \ at91-sam9x60ek.dtb +dtb-$(CONFIG_SOC_SAM9X7) +=3D \ + at91-sam9x75_curiosity.dtb dtb-$(CONFIG_SOC_SAM_V7) +=3D \ at91-kizbox2-2.dtb \ at91-kizbox3-hs.dtb \ diff --git a/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts b/arch/= arm/boot/dts/microchip/at91-sam9x75_curiosity.dts new file mode 100644 index 000000000000..87b6ea97590b --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts @@ -0,0 +1,324 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sam9x75_curiosity.dts - Device Tree file for Microchip SAM9X75 Cur= iosity board + * + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries + * + * Author: Varshini Rajendran + */ +/dts-v1/; +#include "sam9x7.dtsi" +#include + +/ { + model =3D "Microchip SAM9X75 Curiosity"; + compatible =3D "microchip,sam9x75-curiosity", "microchip,sam9x7", "atmel,= at91sam9"; + + aliases { + i2c0 =3D &i2c6; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_key_gpio_default>; + + button-user { + label =3D "USER"; + gpios =3D <&pioC 9 GPIO_ACTIVE_LOW>; + linux,code =3D ; + wakeup-source; + }; + }; + + led-controller { + compatible =3D "gpio-leds"; + + led_red: led-red { + label =3D "red"; + gpios =3D <&pioC 14 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&pinctrl_red_led_gpio_default>; + }; + + led_green: led-green { + label =3D "green"; + gpios =3D <&pioC 21 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&pinctrl_green_led_gpio_default>; + }; + + led_blue: led-blue { + label =3D "blue"; + gpios =3D <&pioC 20 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&pinctrl_blue_led_gpio_default>; + linux,default-trigger =3D "heartbeat"; + }; + }; + + memory@20000000 { + reg =3D <0x20000000 0x10000000>; + device_type =3D "memory"; + }; +}; + +&classd { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_classd_default>; + atmel,pwm-type =3D "diff"; + atmel,non-overlap-time =3D <10>; + status =3D "okay"; +}; + +&dbgu { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_dbgu_default>; + status =3D "okay"; +}; + +&dma0 { + status =3D "okay"; +}; + +&flx6 { + atmel,flexcom-mode =3D ; + status =3D "okay"; +}; + +&i2c6 { + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flx6_default>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns =3D <35>; + status =3D "okay"; + + pmic@5b { + compatible =3D "microchip,mcp16502"; + reg =3D <0x5b>; + + regulators { + vdd_3v3: VDD_IO { + regulator-name =3D "VDD_IO"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-initial-mode =3D <2>; + regulator-allowed-modes =3D <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode =3D <4>; + }; + + regulator-state-mem { + regulator-mode =3D <4>; + }; + }; + + vddioddr: VDD_DDR { + regulator-name =3D "VDD_DDR"; + regulator-min-microvolt =3D <1350000>; + regulator-max-microvolt =3D <1350000>; + regulator-initial-mode =3D <2>; + regulator-allowed-modes =3D <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode =3D <4>; + }; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-mode =3D <4>; + }; + }; + + vddcore: VDD_CORE { + regulator-name =3D "VDD_CORE"; + regulator-min-microvolt =3D <1150000>; + regulator-max-microvolt =3D <1150000>; + regulator-initial-mode =3D <2>; + regulator-allowed-modes =3D <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode =3D <4>; + }; + + regulator-state-mem { + regulator-mode =3D <4>; + }; + }; + + dcdc4: VDD_OTHER { + regulator-name =3D "VDD_OTHER"; + regulator-min-microvolt =3D <1150000>; + regulator-max-microvolt =3D <1150000>; + regulator-initial-mode =3D <2>; + regulator-allowed-modes =3D <2>, <4>; + regulator-ramp-delay =3D <3125>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode =3D <4>; + }; + + regulator-state-mem { + regulator-mode =3D <4>; + }; + }; + + vldo1: LDO1 { + regulator-name =3D "LDO1"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + }; + }; + + vldo2: LDO2 { + regulator-name =3D "LDO2"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-standby { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&i2s { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2s_default>; + #sound-dai-cells =3D <0>; + status =3D "okay"; +}; + +&main_xtal { + clock-frequency =3D <24000000>; +}; + +&pinctrl { + classd { + pinctrl_classd_default: classd-default { + atmel,pins =3D + , + ; + }; + }; + + dbgu { + pinctrl_dbgu_default: dbgu-default { + atmel,pins =3D , + ; + }; + }; + + flexcom { + pinctrl_flx6_default: flx6-default { + atmel,pins =3D + , + ; + }; + }; + + gpio-keys { + pinctrl_key_gpio_default: key-gpio-default { + atmel,pins =3D ; + }; + }; + + i2s { + pinctrl_i2s_default: i2s-default { + atmel,pins =3D + , /* I2SCK */ + , /* I2SWS */ + , /* I2SDIN */ + , /* I2SDOUT */ + ; /* I2SMCK */ + }; + }; + + led-controller { + pinctrl_red_led_gpio_default: red-led-gpio-default { + atmel,pins =3D ; + }; + pinctrl_green_led_gpio_default: green-led-gpio-default { + atmel,pins =3D ; + }; + pinctrl_blue_led_gpio_default: blue-led-gpio-default { + atmel,pins =3D ; + }; + }; + + sdmmc0 { + pinctrl_sdmmc0_default: sdmmc0-default { + atmel,pins =3D + , /* PA2 CK periph A with pullup */ + , /* PA1 CMD periph A with pullup = */ + , /* PA0 DAT0 periph A */ + , /* PA3 DAT1 periph A with pullup= */ + , /* PA4 DAT2 periph A with pullup= */ + ; /* PA5 DAT3 periph A with pullup= */ + }; + }; +}; /* pinctrl */ + +&poweroff { + debounce-delay-us =3D <976>; + status =3D "okay"; + + input@0 { + reg =3D <0>; + }; +}; + +&rtt { + atmel,rtt-rtc-time-reg =3D <&gpbr 0x0>; +}; + +&sdmmc0 { + bus-width =3D <4>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_sdmmc0_default>; + cd-gpios =3D <&pioA 23 GPIO_ACTIVE_LOW>; + disable-wp; + status =3D "okay"; +}; + +&slow_xtal { + clock-frequency =3D <32768>; +}; + +&tcb { + timer0: timer@0 { + compatible =3D "atmel,tcb-timer"; + reg =3D <0>; + }; + + timer1: timer@1 { + compatible =3D "atmel,tcb-timer"; + reg =3D <1>; + }; +}; + +&trng { + status =3D "okay"; +}; + +&watchdog { + status =3D "okay"; +}; --=20 2.25.1