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Thu, 10 Oct 2024 10:32:15 +0000 From: =?UTF-8?q?Micha=C5=82=20Winiarski?= To: , , , , "Bjorn Helgaas" , =?UTF-8?q?Christian=20K=C3=B6nig?= , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= CC: Rodrigo Vivi , Michal Wajdeczko , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Matt Roper , =?UTF-8?q?Micha=C5=82=20Winiarski?= Subject: [PATCH v3 1/5] PCI/IOV: Restore VF resizable BAR state after reset Date: Thu, 10 Oct 2024 12:31:59 +0200 Message-ID: <20241010103203.382898-2-michal.winiarski@intel.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241010103203.382898-1-michal.winiarski@intel.com> References: <20241010103203.382898-1-michal.winiarski@intel.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: WA2P291CA0029.POLP291.PROD.OUTLOOK.COM (2603:10a6:1d0:1f::29) To DM4PR11MB5373.namprd11.prod.outlook.com (2603:10b6:5:394::7) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM4PR11MB5373:EE_|MN6PR11MB8103:EE_ X-MS-Office365-Filtering-Correlation-Id: 727fef6c-a28e-44ca-f976-08dce916ced5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|7416014|1800799024|376014; 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Add the capability ID and restore it as a part of IOV state. See PCIe r4.0, sec 9.3.7.4. Signed-off-by: Micha=C5=82 Winiarski Reviewed-by: Ilpo J=C3=A4rvinen --- drivers/pci/iov.c | 29 ++++++++++++++++++++++++++++- include/uapi/linux/pci_regs.h | 1 + 2 files changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index aaa33e8dc4c97..fd5c059b29c13 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -7,6 +7,7 @@ * Copyright (C) 2009 Intel Corporation, Yu Zhao */ =20 +#include #include #include #include @@ -862,6 +863,30 @@ static void sriov_release(struct pci_dev *dev) dev->sriov =3D NULL; } =20 +static void sriov_restore_vf_rebar_state(struct pci_dev *dev) +{ + unsigned int pos, nbars, i; + u32 ctrl; + + pos =3D pci_find_ext_capability(dev, PCI_EXT_CAP_ID_VF_REBAR); + if (!pos) + return; + + pci_read_config_dword(dev, pos + PCI_REBAR_CTRL, &ctrl); + nbars =3D FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, ctrl); + + for (i =3D 0; i < nbars; i++, pos +=3D 8) { + int bar_idx, size; + + pci_read_config_dword(dev, pos + PCI_REBAR_CTRL, &ctrl); + bar_idx =3D ctrl & PCI_REBAR_CTRL_BAR_IDX; + size =3D pci_rebar_bytes_to_size(dev->sriov->barsz[bar_idx]); + ctrl &=3D ~PCI_REBAR_CTRL_BAR_SIZE; + ctrl |=3D FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size); + pci_write_config_dword(dev, pos + PCI_REBAR_CTRL, ctrl); + } +} + static void sriov_restore_state(struct pci_dev *dev) { int i; @@ -1021,8 +1046,10 @@ resource_size_t pci_sriov_resource_alignment(struct = pci_dev *dev, int resno) */ void pci_restore_iov_state(struct pci_dev *dev) { - if (dev->is_physfn) + if (dev->is_physfn) { + sriov_restore_vf_rebar_state(dev); sriov_restore_state(dev); + } } =20 /** diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 12323b3334a9c..a0cf701c4c3af 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -740,6 +740,7 @@ #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ #define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */ +#define PCI_EXT_CAP_ID_VF_REBAR 0x24 /* VF Resizable BAR */ #define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ #define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */ #define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */ --=20 2.47.0 From nobody Wed Nov 27 13:04:17 2024 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7FA971C231C; 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Thu, 10 Oct 2024 10:32:19 +0000 Received: from DM4PR11MB5373.namprd11.prod.outlook.com ([fe80::927a:9c08:26f7:5b39]) by DM4PR11MB5373.namprd11.prod.outlook.com ([fe80::927a:9c08:26f7:5b39%5]) with mapi id 15.20.8048.013; Thu, 10 Oct 2024 10:32:19 +0000 From: =?UTF-8?q?Micha=C5=82=20Winiarski?= To: , , , , "Bjorn Helgaas" , =?UTF-8?q?Christian=20K=C3=B6nig?= , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= CC: Rodrigo Vivi , Michal Wajdeczko , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Matt Roper , =?UTF-8?q?Micha=C5=82=20Winiarski?= Subject: [PATCH v3 2/5] PCI: Add a helper to identify IOV resources Date: Thu, 10 Oct 2024 12:32:00 +0200 Message-ID: <20241010103203.382898-3-michal.winiarski@intel.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241010103203.382898-1-michal.winiarski@intel.com> References: <20241010103203.382898-1-michal.winiarski@intel.com> Content-Type: text/plain; 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Extract it to a helper and drop a few ifdefs. Signed-off-by: Micha=C5=82 Winiarski Reviewed-by: Ilpo J=C3=A4rvinen --- drivers/pci/pci.h | 18 ++++++++++++++---- drivers/pci/setup-bus.c | 5 +---- drivers/pci/setup-res.c | 4 +--- 3 files changed, 16 insertions(+), 11 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 14d00ce45bfa9..c55f2d7a4f37e 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -580,6 +580,10 @@ void pci_iov_update_resource(struct pci_dev *dev, int = resno); resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resn= o); void pci_restore_iov_state(struct pci_dev *dev); int pci_iov_bus_range(struct pci_bus *bus); +static inline bool pci_resource_is_iov(int resno) +{ + return resno >=3D PCI_IOV_RESOURCES && resno <=3D PCI_IOV_RESOURCE_END; +} extern const struct attribute_group sriov_pf_dev_attr_group; extern const struct attribute_group sriov_vf_dev_attr_group; #else @@ -589,12 +593,20 @@ static inline int pci_iov_init(struct pci_dev *dev) } static inline void pci_iov_release(struct pci_dev *dev) { } static inline void pci_iov_remove(struct pci_dev *dev) { } +static inline void pci_iov_update_resource(struct pci_dev *dev, int resno)= { } +static inline resource_size_t pci_sriov_resource_alignment(struct pci_dev = *dev, int resno) +{ + return 0; +} static inline void pci_restore_iov_state(struct pci_dev *dev) { } static inline int pci_iov_bus_range(struct pci_bus *bus) { return 0; } - +static inline bool pci_resource_is_iov(int resno) +{ + return false; +} #endif /* CONFIG_PCI_IOV */ =20 #ifdef CONFIG_PCIE_PTM @@ -616,12 +628,10 @@ unsigned long pci_cardbus_resource_alignment(struct r= esource *); static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, struct resource *res) { -#ifdef CONFIG_PCI_IOV int resno =3D res - dev->resource; =20 - if (resno >=3D PCI_IOV_RESOURCES && resno <=3D PCI_IOV_RESOURCE_END) + if (pci_resource_is_iov(resno)) return pci_sriov_resource_alignment(dev, resno); -#endif if (dev->class >> 8 =3D=3D PCI_CLASS_BRIDGE_CARDBUS) return pci_cardbus_resource_alignment(res); return resource_alignment(res); diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 23082bc0ca37a..8909948bc9a9f 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -1093,17 +1093,14 @@ static int pbus_size_mem(struct pci_bus *bus, unsig= ned long mask, (r->flags & mask) !=3D type3)) continue; r_size =3D resource_size(r); -#ifdef CONFIG_PCI_IOV /* Put SRIOV requested res to the optional list */ - if (realloc_head && i >=3D PCI_IOV_RESOURCES && - i <=3D PCI_IOV_RESOURCE_END) { + if (realloc_head && pci_resource_is_iov(i)) { add_align =3D max(pci_resource_alignment(dev, r), add_align); r->end =3D r->start - 1; add_to_list(realloc_head, dev, r, r_size, 0 /* Don't care */); children_add_size +=3D r_size; continue; } -#endif /* * aligns[0] is for 1MB (since bridge memory * windows are always at least 1MB aligned), so diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index c6d933ddfd464..e2cf79253ebda 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -127,10 +127,8 @@ void pci_update_resource(struct pci_dev *dev, int resn= o) { if (resno <=3D PCI_ROM_RESOURCE) pci_std_update_resource(dev, resno); -#ifdef CONFIG_PCI_IOV - else if (resno >=3D PCI_IOV_RESOURCES && resno <=3D PCI_IOV_RESOURCE_END) + else if (pci_resource_is_iov(resno)) pci_iov_update_resource(dev, resno); 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The structures are very similar, which means we can reuse most of the implementation. See PCIe r4.0, sec 9.3.7.4. Signed-off-by: Micha=C5=82 Winiarski --- drivers/pci/iov.c | 20 ++++++++++++++++++++ drivers/pci/pci.c | 9 ++++++++- drivers/pci/pci.h | 8 ++++++++ drivers/pci/setup-res.c | 33 ++++++++++++++++++++++++++++----- 4 files changed, 64 insertions(+), 6 deletions(-) diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index fd5c059b29c13..591a3eae1618a 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -154,6 +154,26 @@ resource_size_t pci_iov_resource_size(struct pci_dev *= dev, int resno) return dev->sriov->barsz[resno - PCI_IOV_RESOURCES]; } =20 +void pci_iov_resource_set_size(struct pci_dev *dev, int resno, resource_si= ze_t size) +{ + if (!pci_resource_is_iov(resno)) { + pci_warn(dev, "%s is not an IOV resource\n", + pci_resource_name(dev, resno)); + return; + } + + dev->sriov->barsz[resno - PCI_IOV_RESOURCES] =3D size; +} + +bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev) +{ + u16 cmd; + + pci_read_config_word(dev, dev->sriov->pos + PCI_SRIOV_CTRL, &cmd); + + return cmd & PCI_SRIOV_CTRL_MSE; +} + static void pci_read_vf_config_common(struct pci_dev *virtfn) { struct pci_dev *physfn =3D virtfn->physfn; diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 7d85c04fbba2a..788ae61731213 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -3718,10 +3718,17 @@ void pci_acs_init(struct pci_dev *dev) */ static int pci_rebar_find_pos(struct pci_dev *pdev, int bar) { + int cap =3D PCI_EXT_CAP_ID_REBAR; unsigned int pos, nbars, i; u32 ctrl; =20 - pos =3D pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); +#ifdef CONFIG_PCI_IOV + if (pci_resource_is_iov(bar)) { + cap =3D PCI_EXT_CAP_ID_VF_REBAR; + bar -=3D PCI_IOV_RESOURCES; + } +#endif + pos =3D pci_find_ext_capability(pdev, cap); if (!pos) return -ENOTSUPP; =20 diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index c55f2d7a4f37e..e15fd8fe0f81f 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -584,6 +584,8 @@ static inline bool pci_resource_is_iov(int resno) { return resno >=3D PCI_IOV_RESOURCES && resno <=3D PCI_IOV_RESOURCE_END; } +void pci_iov_resource_set_size(struct pci_dev *dev, int resno, resource_si= ze_t size); +bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev); extern const struct attribute_group sriov_pf_dev_attr_group; extern const struct attribute_group sriov_vf_dev_attr_group; #else @@ -607,6 +609,12 @@ static inline bool pci_resource_is_iov(int resno) { return false; } +static inline void pci_iov_resource_set_size(struct pci_dev *dev, int resn= o, + resource_size_t size) { } +static inline bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev) +{ + return false; +} #endif /* CONFIG_PCI_IOV */ =20 #ifdef CONFIG_PCIE_PTM diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index e2cf79253ebda..95a13a5fa379c 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -425,13 +425,37 @@ void pci_release_resource(struct pci_dev *dev, int re= sno) } EXPORT_SYMBOL(pci_release_resource); =20 +static bool pci_resize_is_memory_decoding_enabled(struct pci_dev *dev, int= resno) +{ + u16 cmd; + + if (pci_resource_is_iov(resno)) + return pci_iov_is_memory_decoding_enabled(dev); + + pci_read_config_word(dev, PCI_COMMAND, &cmd); + + return cmd & PCI_COMMAND_MEMORY; +} + +static void pci_resize_resource_set_size(struct pci_dev *dev, int resno, i= nt size) +{ + resource_size_t res_size =3D pci_rebar_size_to_bytes(size); + struct resource *res =3D dev->resource + resno; + + if (!pci_resource_is_iov(resno)) { + res->end =3D res->start + res_size - 1; + } else { + res->end =3D res->start + res_size * pci_sriov_get_totalvfs(dev) - 1; + pci_iov_resource_set_size(dev, resno, res_size); + } +} + int pci_resize_resource(struct pci_dev *dev, int resno, int size) { struct resource *res =3D dev->resource + resno; struct pci_host_bridge *host; int old, ret; u32 sizes; - u16 cmd; =20 /* Check if we must preserve the firmware's resource assignment */ host =3D pci_find_host_bridge(dev->bus); @@ -442,8 +466,7 @@ int pci_resize_resource(struct pci_dev *dev, int resno,= int size) if (!(res->flags & IORESOURCE_UNSET)) return -EBUSY; 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Thu, 10 Oct 2024 10:32:27 +0000 Received: from DM4PR11MB5373.namprd11.prod.outlook.com ([fe80::927a:9c08:26f7:5b39]) by DM4PR11MB5373.namprd11.prod.outlook.com ([fe80::927a:9c08:26f7:5b39%5]) with mapi id 15.20.8048.013; Thu, 10 Oct 2024 10:32:27 +0000 From: =?UTF-8?q?Micha=C5=82=20Winiarski?= To: , , , , "Bjorn Helgaas" , =?UTF-8?q?Christian=20K=C3=B6nig?= , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= CC: Rodrigo Vivi , Michal Wajdeczko , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Matt Roper , =?UTF-8?q?Micha=C5=82=20Winiarski?= Subject: [PATCH v3 4/5] PCI/IOV: Allow extending VF BAR within original resource boundary Date: Thu, 10 Oct 2024 12:32:02 +0200 Message-ID: <20241010103203.382898-5-michal.winiarski@intel.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241010103203.382898-1-michal.winiarski@intel.com> References: <20241010103203.382898-1-michal.winiarski@intel.com> Content-Type: text/plain; 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This can be leveraged when the device is exposing lower than optimal BAR size as a default, allowing access to the entire resource when lower number of VFs are created. It is achieved by dynamically resizing the BAR to largest possible value that allows to fit all newly created VFs within the original resource boundary. Signed-off-by: Micha=C5=82 Winiarski --- drivers/pci/iov.c | 92 ++++++++++++++++++++++++++++++++++++++++++++- drivers/pci/pci.h | 1 + include/linux/pci.h | 3 ++ 3 files changed, 95 insertions(+), 1 deletion(-) diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index 591a3eae1618a..f9071c1cfe9ee 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -174,6 +174,86 @@ bool pci_iov_is_memory_decoding_enabled(struct pci_dev= *dev) return cmd & PCI_SRIOV_CTRL_MSE; } =20 +static void pci_iov_resource_do_extend(struct pci_dev *dev, int resno, u16= num_vfs) +{ + resource_size_t size; + int ret, old, i; + u32 sizes; + + pci_config_pm_runtime_get(dev); + + if (pci_iov_is_memory_decoding_enabled(dev)) { + ret =3D -EBUSY; + goto err; + } + + sizes =3D pci_rebar_get_possible_sizes(dev, resno); + if (!sizes) { + ret =3D -ENOTSUPP; + goto err; + } + + old =3D pci_rebar_get_current_size(dev, resno); + if (old < 0) { + ret =3D old; + goto err; + } + + while (sizes > 0) { + i =3D __fls(sizes); + size =3D pci_rebar_size_to_bytes(i); + if (size * num_vfs <=3D pci_resource_len(dev, resno)) { + if (i !=3D old) { + ret =3D pci_rebar_set_size(dev, resno, size); + if (ret) + goto err; + + pci_iov_resource_set_size(dev, resno, size); + pci_iov_update_resource(dev, resno); + } + break; + } + sizes &=3D ~BIT(i); + } + + pci_config_pm_runtime_put(dev); + + return; + +err: + pci_warn(dev, "Failed to extend %s: %d\n", + pci_resource_name(dev, resno), ret); + + pci_config_pm_runtime_put(dev); +} + +static void pci_iov_resource_do_restore(struct pci_dev *dev, int resno) +{ + if (dev->sriov->rebar_extend[resno - PCI_IOV_RESOURCES]) + pci_iov_resource_do_extend(dev, resno, dev->sriov->total_VFs); +} + +int pci_iov_resource_extend(struct pci_dev *dev, int resno, bool enable) +{ + if (!pci_resource_is_iov(resno)) { + pci_warn(dev, "%s is not an IOV resource\n", + pci_resource_name(dev, resno)); + + return -ENODEV; + } + + if (!pci_rebar_get_possible_sizes(dev, resno)) + return -ENOTSUPP; + + if (!enable) + pci_iov_resource_do_restore(dev, resno); + + dev->sriov->rebar_extend[resno - PCI_IOV_RESOURCES] =3D enable; + + return 0; +} +EXPORT_SYMBOL_GPL(pci_iov_resource_extend); + static void pci_read_vf_config_common(struct pci_dev *virtfn) { struct pci_dev *physfn =3D virtfn->physfn; @@ -438,7 +518,7 @@ static ssize_t sriov_numvfs_store(struct device *dev, const char *buf, size_t count) { struct pci_dev *pdev =3D to_pci_dev(dev); - int ret =3D 0; + int i, ret =3D 0; u16 num_vfs; =20 if (kstrtou16(buf, 0, &num_vfs) < 0) @@ -480,6 +560,11 @@ static ssize_t sriov_numvfs_store(struct device *dev, goto exit; } =20 + for (i =3D 0; i < PCI_SRIOV_NUM_BARS; i++) { + if (pdev->sriov->rebar_extend[i]) + pci_iov_resource_do_extend(pdev, i + PCI_IOV_RESOURCES, num_vfs); + } + ret =3D pdev->driver->sriov_configure(pdev, num_vfs); if (ret < 0) goto exit; @@ -874,8 +959,13 @@ static int sriov_init(struct pci_dev *dev, int pos) =20 static void sriov_release(struct pci_dev *dev) { + int i; + BUG_ON(dev->sriov->num_VFs); =20 + for (i =3D 0; i < PCI_SRIOV_NUM_BARS; i++) + pci_iov_resource_do_restore(dev, i + PCI_IOV_RESOURCES); + if (dev !=3D dev->sriov->dev) pci_dev_put(dev->sriov->dev); =20 diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index e15fd8fe0f81f..57e79f75e4c8f 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -403,6 +403,7 @@ struct pci_sriov { u16 subsystem_vendor; /* VF subsystem vendor */ u16 subsystem_device; /* VF subsystem device */ resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ + bool rebar_extend[PCI_SRIOV_NUM_BARS]; /* Resize VF BAR */ bool drivers_autoprobe; /* Auto probing of VFs by driver */ }; =20 diff --git a/include/linux/pci.h b/include/linux/pci.h index 573b4c4c2be61..023c0fa1dd9f2 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -2371,6 +2371,7 @@ int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 n= umvfs); int pci_sriov_get_totalvfs(struct pci_dev *dev); int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); 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LMEM is partitioned between multiple VFs, and we expect that the more VFs we have, the less LMEM is assigned to each VF. This means that we can achieve full LMEM BAR access without the need to attempt full VF LMEM BAR resize via pci_resize_resource(). Signed-off-by: Micha=C5=82 Winiarski --- drivers/gpu/drm/xe/regs/xe_bars.h | 1 + drivers/gpu/drm/xe/xe_sriov_pf.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/xe/regs/xe_bars.h b/drivers/gpu/drm/xe/regs/xe= _bars.h index ce05b6ae832f1..880140d6ccdca 100644 --- a/drivers/gpu/drm/xe/regs/xe_bars.h +++ b/drivers/gpu/drm/xe/regs/xe_bars.h @@ -7,5 +7,6 @@ =20 #define GTTMMADR_BAR 0 /* MMIO + GTT */ #define LMEM_BAR 2 /* VRAM */ +#define VF_LMEM_BAR 9 /* VF VRAM */ =20 #endif diff --git a/drivers/gpu/drm/xe/xe_sriov_pf.c b/drivers/gpu/drm/xe/xe_sriov= _pf.c index 0f721ae17b266..a26719b87ac1e 100644 --- a/drivers/gpu/drm/xe/xe_sriov_pf.c +++ b/drivers/gpu/drm/xe/xe_sriov_pf.c @@ -4,7 +4,9 @@ */ =20 #include +#include =20 +#include "regs/xe_bars.h" #include "xe_assert.h" #include "xe_device.h" #include "xe_module.h" @@ -80,8 +82,14 @@ bool xe_sriov_pf_readiness(struct xe_device *xe) */ int xe_sriov_pf_init_early(struct xe_device *xe) { + int err; + xe_assert(xe, IS_SRIOV_PF(xe)); =20 + err =3D pci_iov_resource_extend(to_pci_dev(xe->drm.dev), VF_LMEM_BAR, tru= e); + if (err) + xe_sriov_info(xe, "Failed to extend VF LMEM BAR: %d", err); + return drmm_mutex_init(&xe->drm, &xe->sriov.pf.master_lock); } =20 --=20 2.47.0