From nobody Wed Nov 27 11:47:00 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9103E192B78; Thu, 10 Oct 2024 08:22:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728548564; cv=none; b=bBXqKff/Fj0ZUdSyrXEeRQkBQHsxEQ6sBrINDmLvpIr1ijvps86VRGvrm/m/Wwg/JRao/3ZEqQxXoIPllrxttO1y5B6cCYmpGgUon8/8JxsK2nT8z05h4IbTZwLD83BGoLJzTEYtTYN54SLElGhmimRfLq8REs84azU3NthhFtc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728548564; c=relaxed/simple; bh=j0vLyCJPFlst34XH3yVWN9TjDQ7Y3e3Ov6+1OgCePC4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=WCrrvjIeozmqJ+YUq7GSctnQa6y9KdfSG2Kx6Sp12DjdI0yqI07OOB5RIjAYoE1VGQB6cRT0gZ1tKw3WNYtpT3vduATC/z/LnOPwimgswpRmGNY1AWScJkj8bDFIqzuzB1mQACJYXMdPnUJV34bs3NLzaKKVMLCoyrGU7QXkXpM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=OFWcrvZb; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="OFWcrvZb" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1728548562; x=1760084562; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=j0vLyCJPFlst34XH3yVWN9TjDQ7Y3e3Ov6+1OgCePC4=; b=OFWcrvZbnpipwkt0kR+vE3nWMURI1Jo9FKaImM2UBvAycYqoPNyFrbOM 0WWNJICI0s01D1/o9tuRh/NKLoOzBRZcNh0EC+6OR0ymfCOvfcjBHXDjJ brnl78a/z19SszYrnqlFbkIFnMpjSHOwrRfQVl4pVDRK0g6/EgQq37Aic 18CEsHTOz3CS+nhdHKOj06FviuQ+hqzBQOeFKsM1ZS0q5BmpOpqmU04at NYMqBdRet0huqG0jcfYEE2kJyBjIgngSjIA1hAT+3wBYWIozeVbcAsmHP xxxiWYW/+n1farMS2rtBW2DFKTnLZFVaSv4/TxIfCeSCCnqUxn64BlWTb A==; X-CSE-ConnectionGUID: guzCieAiRJ+z8jrS4dvLsQ== X-CSE-MsgGUID: 6D/vm6A/SGue7z3Z89Lrzg== X-IronPort-AV: E=Sophos;i="6.11,192,1725346800"; d="scan'208";a="33418975" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Oct 2024 01:22:36 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 10 Oct 2024 01:22:30 -0700 Received: from che-ll-i17164.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 10 Oct 2024 01:22:26 -0700 From: Parthiban Veerasooran To: , , , , , , , CC: , , , , Subject: [PATCH net-next v4 1/7] net: phy: microchip_t1s: restructure cfg read/write functions arguments Date: Thu, 10 Oct 2024 13:51:59 +0530 Message-ID: <20241010082205.221493-2-parthiban.veerasooran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241010082205.221493-1-parthiban.veerasooran@microchip.com> References: <20241010082205.221493-1-parthiban.veerasooran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Restructure lan865x_write_cfg_params() and lan865x_read_cfg_params() functions arguments to more generic which will be useful for the next patch which updates the improved initial configuration for LAN8650/1 Rev.B0 published in the Configuration Note. Signed-off-by: Parthiban Veerasooran --- drivers/net/phy/microchip_t1s.c | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/drivers/net/phy/microchip_t1s.c b/drivers/net/phy/microchip_t1= s.c index 3614839a8e51..24f992aba7d7 100644 --- a/drivers/net/phy/microchip_t1s.c +++ b/drivers/net/phy/microchip_t1s.c @@ -112,7 +112,7 @@ static int lan865x_revb0_indirect_read(struct phy_devic= e *phydev, u16 addr) /* This is pulled straight from AN1760 from 'calculation of offset 1' & * 'calculation of offset 2' */ -static int lan865x_generate_cfg_offsets(struct phy_device *phydev, s8 offs= ets[2]) +static int lan865x_generate_cfg_offsets(struct phy_device *phydev, s8 offs= ets[]) { const u16 fixup_regs[2] =3D {0x0004, 0x0008}; int ret; @@ -130,13 +130,15 @@ static int lan865x_generate_cfg_offsets(struct phy_de= vice *phydev, s8 offsets[2] return 0; } =20 -static int lan865x_read_cfg_params(struct phy_device *phydev, u16 cfg_para= ms[]) +static int lan865x_read_cfg_params(struct phy_device *phydev, + const u16 cfg_regs[], u16 cfg_params[], + u8 count) { int ret; =20 - for (int i =3D 0; i < ARRAY_SIZE(lan865x_revb0_fixup_cfg_regs); i++) { + for (int i =3D 0; i < count; i++) { ret =3D phy_read_mmd(phydev, MDIO_MMD_VEND2, - lan865x_revb0_fixup_cfg_regs[i]); + cfg_regs[i]); if (ret < 0) return ret; cfg_params[i] =3D (u16)ret; @@ -145,13 +147,14 @@ static int lan865x_read_cfg_params(struct phy_device = *phydev, u16 cfg_params[]) return 0; } =20 -static int lan865x_write_cfg_params(struct phy_device *phydev, u16 cfg_par= ams[]) +static int lan865x_write_cfg_params(struct phy_device *phydev, + const u16 cfg_regs[], u16 cfg_params[], + u8 count) { int ret; =20 - for (int i =3D 0; i < ARRAY_SIZE(lan865x_revb0_fixup_cfg_regs); i++) { - ret =3D phy_write_mmd(phydev, MDIO_MMD_VEND2, - lan865x_revb0_fixup_cfg_regs[i], + for (int i =3D 0; i < count; i++) { + ret =3D phy_write_mmd(phydev, MDIO_MMD_VEND2, cfg_regs[i], cfg_params[i]); if (ret) return ret; @@ -162,8 +165,8 @@ static int lan865x_write_cfg_params(struct phy_device *= phydev, u16 cfg_params[]) =20 static int lan865x_setup_cfgparam(struct phy_device *phydev) { + u16 cfg_results[ARRAY_SIZE(lan865x_revb0_fixup_cfg_regs)]; u16 cfg_params[ARRAY_SIZE(lan865x_revb0_fixup_cfg_regs)]; - u16 cfg_results[5]; s8 offsets[2]; int ret; =20 @@ -171,7 +174,8 @@ static int lan865x_setup_cfgparam(struct phy_device *ph= ydev) if (ret) return ret; =20 - ret =3D lan865x_read_cfg_params(phydev, cfg_params); + ret =3D lan865x_read_cfg_params(phydev, lan865x_revb0_fixup_cfg_regs, + cfg_params, ARRAY_SIZE(cfg_params)); if (ret) return ret; =20 @@ -190,7 +194,8 @@ static int lan865x_setup_cfgparam(struct phy_device *ph= ydev) FIELD_PREP(GENMASK(15, 8), 17 + offsets[0]) | (22 + offsets[0]); =20 - return lan865x_write_cfg_params(phydev, cfg_results); + return lan865x_write_cfg_params(phydev, lan865x_revb0_fixup_cfg_regs, + cfg_results, ARRAY_SIZE(cfg_results)); } =20 static int lan865x_revb0_config_init(struct phy_device *phydev) --=20 2.34.1 From nobody Wed Nov 27 11:47:00 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 53B4E1C3F1F; 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charset="utf-8" Update the new/improved initial settings from the latest configuration application note AN1760 released for LAN8650/1 Rev.B0 Revision F (DS60001760G - June 2024). https://www.microchip.com/en-us/application-notes/an1760 Signed-off-by: Parthiban Veerasooran --- drivers/net/phy/microchip_t1s.c | 120 ++++++++++++++++++++++---------- 1 file changed, 84 insertions(+), 36 deletions(-) diff --git a/drivers/net/phy/microchip_t1s.c b/drivers/net/phy/microchip_t1= s.c index 24f992aba7d7..12f6678e3188 100644 --- a/drivers/net/phy/microchip_t1s.c +++ b/drivers/net/phy/microchip_t1s.c @@ -59,29 +59,45 @@ static const u16 lan867x_revb1_fixup_masks[12] =3D { 0x0600, 0x7F00, 0x2000, 0xFFFF, }; =20 -/* LAN865x Rev.B0 configuration parameters from AN1760 */ -static const u32 lan865x_revb0_fixup_registers[28] =3D { - 0x0091, 0x0081, 0x0043, 0x0044, - 0x0045, 0x0053, 0x0054, 0x0055, - 0x0040, 0x0050, 0x00D0, 0x00E9, - 0x00F5, 0x00F4, 0x00F8, 0x00F9, +/* LAN865x Rev.B0 configuration parameters from AN1760 + * As per the Configuration Application Note AN1760 published in the below= link, + * https://www.microchip.com/en-us/application-notes/an1760 + * Revision F (DS60001760G - June 2024) + */ +static const u32 lan865x_revb0_fixup_registers[17] =3D { + 0x00D0, 0x00E0, 0x00E9, 0x00F5, + 0x00F4, 0x00F8, 0x00F9, 0x0081, + 0x0091, 0x0043, 0x0044, 0x0045, + 0x0053, 0x0054, 0x0055, 0x0040, + 0x0050, +}; + +static const u16 lan865x_revb0_fixup_values[17] =3D { + 0x3F31, 0xC000, 0x9E50, 0x1CF8, + 0xC020, 0xB900, 0x4E53, 0x0080, + 0x9660, 0x00FF, 0xFFFF, 0x0000, + 0x00FF, 0xFFFF, 0x0000, 0x0002, + 0x0002, +}; + +static const u16 lan865x_revb0_fixup_cfg_regs[2] =3D { + 0x0084, 0x008A, +}; + +static const u32 lan865x_revb0_sqi_fixup_regs[12] =3D { 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, 0x00B8, 0x00B9, 0x00BA, 0x00BB, }; =20 -static const u16 lan865x_revb0_fixup_values[28] =3D { - 0x9660, 0x00C0, 0x00FF, 0xFFFF, - 0x0000, 0x00FF, 0xFFFF, 0x0000, - 0x0002, 0x0002, 0x5F21, 0x9E50, - 0x1CF8, 0xC020, 0x9B00, 0x4E53, +static const u16 lan865x_revb0_sqi_fixup_values[12] =3D { 0x0103, 0x0910, 0x1D26, 0x002A, 0x0103, 0x070D, 0x1720, 0x0027, 0x0509, 0x0E13, 0x1C25, 0x002B, }; =20 -static const u16 lan865x_revb0_fixup_cfg_regs[5] =3D { - 0x0084, 0x008A, 0x00AD, 0x00AE, 0x00AF +static const u16 lan865x_revb0_sqi_fixup_cfg_regs[3] =3D { + 0x00AD, 0x00AE, 0x00AF, }; =20 /* Pulled from AN1760 describing 'indirect read' @@ -121,6 +137,9 @@ static int lan865x_generate_cfg_offsets(struct phy_devi= ce *phydev, s8 offsets[]) ret =3D lan865x_revb0_indirect_read(phydev, fixup_regs[i]); if (ret < 0) return ret; + + /* 5-bit signed value, sign extend */ + ret &=3D GENMASK(4, 0); if (ret & BIT(4)) offsets[i] =3D ret | 0xE0; else @@ -163,59 +182,88 @@ static int lan865x_write_cfg_params(struct phy_device= *phydev, return 0; } =20 -static int lan865x_setup_cfgparam(struct phy_device *phydev) +static int lan865x_setup_cfgparam(struct phy_device *phydev, s8 offsets[]) { u16 cfg_results[ARRAY_SIZE(lan865x_revb0_fixup_cfg_regs)]; u16 cfg_params[ARRAY_SIZE(lan865x_revb0_fixup_cfg_regs)]; - s8 offsets[2]; int ret; =20 - ret =3D lan865x_generate_cfg_offsets(phydev, offsets); + ret =3D lan865x_read_cfg_params(phydev, lan865x_revb0_fixup_cfg_regs, + cfg_params, ARRAY_SIZE(cfg_params)); if (ret) return ret; =20 - ret =3D lan865x_read_cfg_params(phydev, lan865x_revb0_fixup_cfg_regs, + cfg_results[0] =3D FIELD_PREP(GENMASK(15, 10), 9 + offsets[0]) | + FIELD_PREP(GENMASK(9, 4), 14 + offsets[0]) | + 0x03; + cfg_results[1] =3D FIELD_PREP(GENMASK(15, 10), 40 + offsets[1]); + + return lan865x_write_cfg_params(phydev, lan865x_revb0_fixup_cfg_regs, + cfg_results, ARRAY_SIZE(cfg_results)); +} + +static int lan865x_setup_sqi_cfgparam(struct phy_device *phydev, s8 offset= s[]) +{ + u16 cfg_results[ARRAY_SIZE(lan865x_revb0_sqi_fixup_cfg_regs)]; + u16 cfg_params[ARRAY_SIZE(lan865x_revb0_sqi_fixup_cfg_regs)]; + int ret; + + ret =3D lan865x_read_cfg_params(phydev, lan865x_revb0_sqi_fixup_cfg_regs, cfg_params, ARRAY_SIZE(cfg_params)); if (ret) return ret; =20 - cfg_results[0] =3D (cfg_params[0] & 0x000F) | - FIELD_PREP(GENMASK(15, 10), 9 + offsets[0]) | - FIELD_PREP(GENMASK(15, 4), 14 + offsets[0]); - cfg_results[1] =3D (cfg_params[1] & 0x03FF) | - FIELD_PREP(GENMASK(15, 10), 40 + offsets[1]); - cfg_results[2] =3D (cfg_params[2] & 0xC0C0) | - FIELD_PREP(GENMASK(15, 8), 5 + offsets[0]) | - (9 + offsets[0]); - cfg_results[3] =3D (cfg_params[3] & 0xC0C0) | - FIELD_PREP(GENMASK(15, 8), 9 + offsets[0]) | - (14 + offsets[0]); - cfg_results[4] =3D (cfg_params[4] & 0xC0C0) | - FIELD_PREP(GENMASK(15, 8), 17 + offsets[0]) | - (22 + offsets[0]); + cfg_results[0] =3D FIELD_PREP(GENMASK(13, 8), 5 + offsets[0]) | + (9 + offsets[0]); + cfg_results[1] =3D FIELD_PREP(GENMASK(13, 8), 9 + offsets[0]) | + (14 + offsets[0]); + cfg_results[2] =3D FIELD_PREP(GENMASK(13, 8), 17 + offsets[0]) | + (22 + offsets[0]); =20 - return lan865x_write_cfg_params(phydev, lan865x_revb0_fixup_cfg_regs, + return lan865x_write_cfg_params(phydev, + lan865x_revb0_sqi_fixup_cfg_regs, cfg_results, ARRAY_SIZE(cfg_results)); } =20 static int lan865x_revb0_config_init(struct phy_device *phydev) { + s8 offsets[2]; int ret; =20 /* Reference to AN1760 * https://ww1.microchip.com/downloads/aemDocuments/documents/AIS/Product= Documents/SupportingCollateral/AN-LAN8650-1-Configuration-60001760.pdf */ + ret =3D lan865x_generate_cfg_offsets(phydev, offsets); + if (ret) + return ret; + for (int i =3D 0; i < ARRAY_SIZE(lan865x_revb0_fixup_registers); i++) { ret =3D phy_write_mmd(phydev, MDIO_MMD_VEND2, lan865x_revb0_fixup_registers[i], lan865x_revb0_fixup_values[i]); if (ret) return ret; + + if (i =3D=3D 1) { + ret =3D lan865x_setup_cfgparam(phydev, offsets); + if (ret) + return ret; + } } - /* Function to calculate and write the configuration parameters in the - * 0x0084, 0x008A, 0x00AD, 0x00AE and 0x00AF registers (from AN1760) - */ - return lan865x_setup_cfgparam(phydev); + + ret =3D lan865x_setup_sqi_cfgparam(phydev, offsets); + if (ret) + return ret; + + for (int i =3D 0; i < ARRAY_SIZE(lan865x_revb0_sqi_fixup_regs); i++) { + ret =3D phy_write_mmd(phydev, MDIO_MMD_VEND2, + lan865x_revb0_sqi_fixup_regs[i], + lan865x_revb0_sqi_fixup_values[i]); + if (ret) + return ret; + } + + return 0; } =20 static int lan867x_revb1_config_init(struct phy_device *phydev) --=20 2.34.1 From nobody Wed Nov 27 11:47:00 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6BD6B1CB53C; Thu, 10 Oct 2024 08:23:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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d="scan'208";a="36163256" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Oct 2024 01:23:09 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 10 Oct 2024 01:22:39 -0700 Received: from che-ll-i17164.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 10 Oct 2024 01:22:35 -0700 From: Parthiban Veerasooran To: , , , , , , , CC: , , , , Subject: [PATCH net-next v4 3/7] net: phy: microchip_t1s: add support for Microchip's LAN865X Rev.B1 Date: Thu, 10 Oct 2024 13:52:01 +0530 Message-ID: <20241010082205.221493-4-parthiban.veerasooran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241010082205.221493-1-parthiban.veerasooran@microchip.com> References: <20241010082205.221493-1-parthiban.veerasooran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for LAN8650/1 Rev.B1. As per the latest configuration note AN1760 released (Revision F (DS60001760G - June 2024)) for Rev.B0 is also applicable for Rev.B1. Refer hardware revisions list in the latest AN1760 Revision F (DS60001760G - June 2024). https://www.microchip.com/en-us/application-notes/an1760 Signed-off-by: Parthiban Veerasooran --- drivers/net/phy/Kconfig | 4 +-- drivers/net/phy/microchip_t1s.c | 62 ++++++++++++++++----------------- 2 files changed, 33 insertions(+), 33 deletions(-) diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 01b235b3bb7e..f18defab70cf 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -292,8 +292,8 @@ config MICREL_PHY config MICROCHIP_T1S_PHY tristate "Microchip 10BASE-T1S Ethernet PHYs" help - Currently supports the LAN8670/1/2 Rev.B1 and LAN8650/1 Rev.B0 Internal - PHYs. + Currently supports the LAN8670/1/2 Rev.B1 and LAN8650/1 Rev.B0/B1 + Internal PHYs. =20 config MICROCHIP_PHY tristate "Microchip PHYs" diff --git a/drivers/net/phy/microchip_t1s.c b/drivers/net/phy/microchip_t1= s.c index 12f6678e3188..b21f5acb4468 100644 --- a/drivers/net/phy/microchip_t1s.c +++ b/drivers/net/phy/microchip_t1s.c @@ -4,7 +4,7 @@ * * Support: Microchip Phys: * lan8670/1/2 Rev.B1 - * lan8650/1 Rev.B0 Internal PHYs + * lan8650/1 Rev.B0/B1 Internal PHYs */ =20 #include @@ -12,7 +12,8 @@ #include =20 #define PHY_ID_LAN867X_REVB1 0x0007C162 -#define PHY_ID_LAN865X_REVB0 0x0007C1B3 +/* Both Rev.B0 and B1 clause 22 PHYID's are same due to B1 chip limitation= */ +#define PHY_ID_LAN865X_REVB 0x0007C1B3 =20 #define LAN867X_REG_STS2 0x0019 =20 @@ -59,12 +60,12 @@ static const u16 lan867x_revb1_fixup_masks[12] =3D { 0x0600, 0x7F00, 0x2000, 0xFFFF, }; =20 -/* LAN865x Rev.B0 configuration parameters from AN1760 +/* LAN865x Rev.B0/B1 configuration parameters from AN1760 * As per the Configuration Application Note AN1760 published in the below= link, * https://www.microchip.com/en-us/application-notes/an1760 * Revision F (DS60001760G - June 2024) */ -static const u32 lan865x_revb0_fixup_registers[17] =3D { +static const u32 lan865x_revb_fixup_registers[17] =3D { 0x00D0, 0x00E0, 0x00E9, 0x00F5, 0x00F4, 0x00F8, 0x00F9, 0x0081, 0x0091, 0x0043, 0x0044, 0x0045, @@ -72,7 +73,7 @@ static const u32 lan865x_revb0_fixup_registers[17] =3D { 0x0050, }; =20 -static const u16 lan865x_revb0_fixup_values[17] =3D { +static const u16 lan865x_revb_fixup_values[17] =3D { 0x3F31, 0xC000, 0x9E50, 0x1CF8, 0xC020, 0xB900, 0x4E53, 0x0080, 0x9660, 0x00FF, 0xFFFF, 0x0000, @@ -80,23 +81,23 @@ static const u16 lan865x_revb0_fixup_values[17] =3D { 0x0002, }; =20 -static const u16 lan865x_revb0_fixup_cfg_regs[2] =3D { +static const u16 lan865x_revb_fixup_cfg_regs[2] =3D { 0x0084, 0x008A, }; =20 -static const u32 lan865x_revb0_sqi_fixup_regs[12] =3D { +static const u32 lan865x_revb_sqi_fixup_regs[12] =3D { 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, 0x00B8, 0x00B9, 0x00BA, 0x00BB, }; =20 -static const u16 lan865x_revb0_sqi_fixup_values[12] =3D { +static const u16 lan865x_revb_sqi_fixup_values[12] =3D { 0x0103, 0x0910, 0x1D26, 0x002A, 0x0103, 0x070D, 0x1720, 0x0027, 0x0509, 0x0E13, 0x1C25, 0x002B, }; =20 -static const u16 lan865x_revb0_sqi_fixup_cfg_regs[3] =3D { +static const u16 lan865x_revb_sqi_fixup_cfg_regs[3] =3D { 0x00AD, 0x00AE, 0x00AF, }; =20 @@ -108,7 +109,7 @@ static const u16 lan865x_revb0_sqi_fixup_cfg_regs[3] = =3D { * * 0x4 refers to memory map selector 4, which maps to MDIO_MMD_VEND2 */ -static int lan865x_revb0_indirect_read(struct phy_device *phydev, u16 addr) +static int lan865x_revb_indirect_read(struct phy_device *phydev, u16 addr) { int ret; =20 @@ -134,7 +135,7 @@ static int lan865x_generate_cfg_offsets(struct phy_devi= ce *phydev, s8 offsets[]) int ret; =20 for (int i =3D 0; i < ARRAY_SIZE(fixup_regs); i++) { - ret =3D lan865x_revb0_indirect_read(phydev, fixup_regs[i]); + ret =3D lan865x_revb_indirect_read(phydev, fixup_regs[i]); if (ret < 0) return ret; =20 @@ -184,11 +185,11 @@ static int lan865x_write_cfg_params(struct phy_device= *phydev, =20 static int lan865x_setup_cfgparam(struct phy_device *phydev, s8 offsets[]) { - u16 cfg_results[ARRAY_SIZE(lan865x_revb0_fixup_cfg_regs)]; - u16 cfg_params[ARRAY_SIZE(lan865x_revb0_fixup_cfg_regs)]; + u16 cfg_results[ARRAY_SIZE(lan865x_revb_fixup_cfg_regs)]; + u16 cfg_params[ARRAY_SIZE(lan865x_revb_fixup_cfg_regs)]; int ret; =20 - ret =3D lan865x_read_cfg_params(phydev, lan865x_revb0_fixup_cfg_regs, + ret =3D lan865x_read_cfg_params(phydev, lan865x_revb_fixup_cfg_regs, cfg_params, ARRAY_SIZE(cfg_params)); if (ret) return ret; @@ -198,17 +199,17 @@ static int lan865x_setup_cfgparam(struct phy_device *= phydev, s8 offsets[]) 0x03; cfg_results[1] =3D FIELD_PREP(GENMASK(15, 10), 40 + offsets[1]); =20 - return lan865x_write_cfg_params(phydev, lan865x_revb0_fixup_cfg_regs, + return lan865x_write_cfg_params(phydev, lan865x_revb_fixup_cfg_regs, cfg_results, ARRAY_SIZE(cfg_results)); } =20 static int lan865x_setup_sqi_cfgparam(struct phy_device *phydev, s8 offset= s[]) { - u16 cfg_results[ARRAY_SIZE(lan865x_revb0_sqi_fixup_cfg_regs)]; - u16 cfg_params[ARRAY_SIZE(lan865x_revb0_sqi_fixup_cfg_regs)]; + u16 cfg_results[ARRAY_SIZE(lan865x_revb_sqi_fixup_cfg_regs)]; + u16 cfg_params[ARRAY_SIZE(lan865x_revb_sqi_fixup_cfg_regs)]; int ret; =20 - ret =3D lan865x_read_cfg_params(phydev, lan865x_revb0_sqi_fixup_cfg_regs, + ret =3D lan865x_read_cfg_params(phydev, lan865x_revb_sqi_fixup_cfg_regs, cfg_params, ARRAY_SIZE(cfg_params)); if (ret) return ret; @@ -220,12 +221,11 @@ static int lan865x_setup_sqi_cfgparam(struct phy_devi= ce *phydev, s8 offsets[]) cfg_results[2] =3D FIELD_PREP(GENMASK(13, 8), 17 + offsets[0]) | (22 + offsets[0]); =20 - return lan865x_write_cfg_params(phydev, - lan865x_revb0_sqi_fixup_cfg_regs, + return lan865x_write_cfg_params(phydev, lan865x_revb_sqi_fixup_cfg_regs, cfg_results, ARRAY_SIZE(cfg_results)); } =20 -static int lan865x_revb0_config_init(struct phy_device *phydev) +static int lan865x_revb_config_init(struct phy_device *phydev) { s8 offsets[2]; int ret; @@ -237,10 +237,10 @@ static int lan865x_revb0_config_init(struct phy_devic= e *phydev) if (ret) return ret; =20 - for (int i =3D 0; i < ARRAY_SIZE(lan865x_revb0_fixup_registers); i++) { + for (int i =3D 0; i < ARRAY_SIZE(lan865x_revb_fixup_registers); i++) { ret =3D phy_write_mmd(phydev, MDIO_MMD_VEND2, - lan865x_revb0_fixup_registers[i], - lan865x_revb0_fixup_values[i]); + lan865x_revb_fixup_registers[i], + lan865x_revb_fixup_values[i]); if (ret) return ret; =20 @@ -255,10 +255,10 @@ static int lan865x_revb0_config_init(struct phy_devic= e *phydev) if (ret) return ret; =20 - for (int i =3D 0; i < ARRAY_SIZE(lan865x_revb0_sqi_fixup_regs); i++) { + for (int i =3D 0; i < ARRAY_SIZE(lan865x_revb_sqi_fixup_regs); i++) { ret =3D phy_write_mmd(phydev, MDIO_MMD_VEND2, - lan865x_revb0_sqi_fixup_regs[i], - lan865x_revb0_sqi_fixup_values[i]); + lan865x_revb_sqi_fixup_regs[i], + lan865x_revb_sqi_fixup_values[i]); if (ret) return ret; } @@ -361,10 +361,10 @@ static struct phy_driver microchip_t1s_driver[] =3D { .get_plca_status =3D genphy_c45_plca_get_status, }, { - PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB0), - .name =3D "LAN865X Rev.B0 Internal Phy", + PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB), + .name =3D "LAN865X Rev.B0/B1 Internal Phy", .features =3D PHY_BASIC_T1S_P2MP_FEATURES, - .config_init =3D lan865x_revb0_config_init, + .config_init =3D lan865x_revb_config_init, .read_status =3D lan86xx_read_status, .read_mmd =3D lan865x_phy_read_mmd, .write_mmd =3D lan865x_phy_write_mmd, @@ -378,7 +378,7 @@ module_phy_driver(microchip_t1s_driver); =20 static struct mdio_device_id __maybe_unused tbl[] =3D { { PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVB1) }, - { PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB0) }, + { PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB) }, { } }; =20 --=20 2.34.1 From nobody Wed Nov 27 11:47:00 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37F701CBE92; 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charset="utf-8" Move LAN867X reset handling code to a new function called lan867x_check_reset_complete() which will be useful for the next patch which also uses the same code to handle the reset functionality. Signed-off-by: Parthiban Veerasooran --- drivers/net/phy/microchip_t1s.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/microchip_t1s.c b/drivers/net/phy/microchip_t1= s.c index b21f5acb4468..d9814a09a026 100644 --- a/drivers/net/phy/microchip_t1s.c +++ b/drivers/net/phy/microchip_t1s.c @@ -266,7 +266,7 @@ static int lan865x_revb_config_init(struct phy_device *= phydev) return 0; } =20 -static int lan867x_revb1_config_init(struct phy_device *phydev) +static int lan867x_check_reset_complete(struct phy_device *phydev) { int err; =20 @@ -288,6 +288,17 @@ static int lan867x_revb1_config_init(struct phy_device= *phydev) } } =20 + return 0; +} + +static int lan867x_revb1_config_init(struct phy_device *phydev) +{ + int err; + + err =3D lan867x_check_reset_complete(phydev); + if (err) + return err; + /* Reference to AN1699 * https://ww1.microchip.com/downloads/aemDocuments/documents/AIS/Product= Documents/SupportingCollateral/AN-LAN8670-1-2-config-60001699.pdf * AN1699 says Read, Modify, Write, but the Write is not required if the --=20 2.34.1 From nobody Wed Nov 27 11:47:00 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE4B31CBEA2; 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charset="utf-8" Add support for LAN8670/1/2 Rev.C1 as per the latest configuration note AN1699 released (Revision E (DS60001699F - June 2024)). https://www.microchip.com/en-us/application-notes/an1699 Signed-off-by: Parthiban Veerasooran --- drivers/net/phy/Kconfig | 2 +- drivers/net/phy/microchip_t1s.c | 66 ++++++++++++++++++++++++++++++++- 2 files changed, 66 insertions(+), 2 deletions(-) diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index f18defab70cf..04f605606a8a 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -292,7 +292,7 @@ config MICREL_PHY config MICROCHIP_T1S_PHY tristate "Microchip 10BASE-T1S Ethernet PHYs" help - Currently supports the LAN8670/1/2 Rev.B1 and LAN8650/1 Rev.B0/B1 + Currently supports the LAN8670/1/2 Rev.B1/C1 and LAN8650/1 Rev.B0/B1 Internal PHYs. =20 config MICROCHIP_PHY diff --git a/drivers/net/phy/microchip_t1s.c b/drivers/net/phy/microchip_t1= s.c index d9814a09a026..f4081886ac1e 100644 --- a/drivers/net/phy/microchip_t1s.c +++ b/drivers/net/phy/microchip_t1s.c @@ -3,7 +3,7 @@ * Driver for Microchip 10BASE-T1S PHYs * * Support: Microchip Phys: - * lan8670/1/2 Rev.B1 + * lan8670/1/2 Rev.B1/C1 * lan8650/1 Rev.B0/B1 Internal PHYs */ =20 @@ -12,6 +12,7 @@ #include =20 #define PHY_ID_LAN867X_REVB1 0x0007C162 +#define PHY_ID_LAN867X_REVC1 0x0007C164 /* Both Rev.B0 and B1 clause 22 PHYID's are same due to B1 chip limitation= */ #define PHY_ID_LAN865X_REVB 0x0007C1B3 =20 @@ -291,6 +292,58 @@ static int lan867x_check_reset_complete(struct phy_dev= ice *phydev) return 0; } =20 +static int lan867x_revc1_config_init(struct phy_device *phydev) +{ + s8 offsets[2]; + int ret; + + ret =3D lan867x_check_reset_complete(phydev); + if (ret) + return ret; + + ret =3D lan865x_generate_cfg_offsets(phydev, offsets); + if (ret) + return ret; + + /* LAN867x Rev.C1 configuration settings are equal to the first 9 + * configuration settings and all the sqi fixup settings from LAN865x + * Rev.B0/B1. So the same fixup registers and values from LAN865x + * Rev.B0/B1 are used for LAN867x Rev.C1 to avoid duplication. + * Refer the below links for the comparison. + * https://www.microchip.com/en-us/application-notes/an1760 + * Revision F (DS60001760G - June 2024) + * https://www.microchip.com/en-us/application-notes/an1699 + * Revision E (DS60001699F - June 2024) + */ + for (int i =3D 0; i < 9; i++) { + ret =3D phy_write_mmd(phydev, MDIO_MMD_VEND2, + lan865x_revb_fixup_registers[i], + lan865x_revb_fixup_values[i]); + if (ret) + return ret; + + if (i =3D=3D 1) { + ret =3D lan865x_setup_cfgparam(phydev, offsets); + if (ret) + return ret; + } + } + + ret =3D lan865x_setup_sqi_cfgparam(phydev, offsets); + if (ret) + return ret; + + for (int i =3D 0; i < ARRAY_SIZE(lan865x_revb_sqi_fixup_regs); i++) { + ret =3D phy_write_mmd(phydev, MDIO_MMD_VEND2, + lan865x_revb_sqi_fixup_regs[i], + lan865x_revb_sqi_fixup_values[i]); + if (ret) + return ret; + } + + return 0; +} + static int lan867x_revb1_config_init(struct phy_device *phydev) { int err; @@ -371,6 +424,16 @@ static struct phy_driver microchip_t1s_driver[] =3D { .set_plca_cfg =3D genphy_c45_plca_set_cfg, .get_plca_status =3D genphy_c45_plca_get_status, }, + { + PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVC1), + .name =3D "LAN867X Rev.C1", + .features =3D PHY_BASIC_T1S_P2MP_FEATURES, + .config_init =3D lan867x_revc1_config_init, + .read_status =3D lan86xx_read_status, + .get_plca_cfg =3D genphy_c45_plca_get_cfg, + .set_plca_cfg =3D genphy_c45_plca_set_cfg, + .get_plca_status =3D genphy_c45_plca_get_status, + }, { PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB), .name =3D "LAN865X Rev.B0/B1 Internal Phy", @@ -389,6 +452,7 @@ module_phy_driver(microchip_t1s_driver); =20 static struct mdio_device_id __maybe_unused tbl[] =3D { { PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVB1) }, + { PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVC1) }, { PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB) }, { } }; --=20 2.34.1 From nobody Wed Nov 27 11:47:00 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EBA521CBE80; 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charset="utf-8" Add support for LAN8670/1/2 Rev.C2 as per the latest configuration note AN1699 released (Revision E (DS60001699F - June 2024)) for Rev.C1 is also applicable for Rev.C2. Refer hardware revisions list in the latest AN1699 Revision E (DS60001699F - June 2024). https://www.microchip.com/en-us/application-notes/an1699 Signed-off-by: Parthiban Veerasooran --- drivers/net/phy/Kconfig | 4 ++-- drivers/net/phy/microchip_t1s.c | 22 +++++++++++++++++----- 2 files changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 04f605606a8a..ee3ea0b56d48 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -292,8 +292,8 @@ config MICREL_PHY config MICROCHIP_T1S_PHY tristate "Microchip 10BASE-T1S Ethernet PHYs" help - Currently supports the LAN8670/1/2 Rev.B1/C1 and LAN8650/1 Rev.B0/B1 - Internal PHYs. + Currently supports the LAN8670/1/2 Rev.B1/C1/C2 and + LAN8650/1 Rev.B0/B1 Internal PHYs. =20 config MICROCHIP_PHY tristate "Microchip PHYs" diff --git a/drivers/net/phy/microchip_t1s.c b/drivers/net/phy/microchip_t1= s.c index f4081886ac1e..d305c2b1fcd0 100644 --- a/drivers/net/phy/microchip_t1s.c +++ b/drivers/net/phy/microchip_t1s.c @@ -3,7 +3,7 @@ * Driver for Microchip 10BASE-T1S PHYs * * Support: Microchip Phys: - * lan8670/1/2 Rev.B1/C1 + * lan8670/1/2 Rev.B1/C1/C2 * lan8650/1 Rev.B0/B1 Internal PHYs */ =20 @@ -13,6 +13,7 @@ =20 #define PHY_ID_LAN867X_REVB1 0x0007C162 #define PHY_ID_LAN867X_REVC1 0x0007C164 +#define PHY_ID_LAN867X_REVC2 0x0007C165 /* Both Rev.B0 and B1 clause 22 PHYID's are same due to B1 chip limitation= */ #define PHY_ID_LAN865X_REVB 0x0007C1B3 =20 @@ -292,7 +293,7 @@ static int lan867x_check_reset_complete(struct phy_devi= ce *phydev) return 0; } =20 -static int lan867x_revc1_config_init(struct phy_device *phydev) +static int lan867x_revc_config_init(struct phy_device *phydev) { s8 offsets[2]; int ret; @@ -305,10 +306,10 @@ static int lan867x_revc1_config_init(struct phy_devic= e *phydev) if (ret) return ret; =20 - /* LAN867x Rev.C1 configuration settings are equal to the first 9 + /* LAN867x Rev.C1/C2 configuration settings are equal to the first 9 * configuration settings and all the sqi fixup settings from LAN865x * Rev.B0/B1. So the same fixup registers and values from LAN865x - * Rev.B0/B1 are used for LAN867x Rev.C1 to avoid duplication. + * Rev.B0/B1 are used for LAN867x Rev.C1/C2 to avoid duplication. * Refer the below links for the comparison. * https://www.microchip.com/en-us/application-notes/an1760 * Revision F (DS60001760G - June 2024) @@ -428,7 +429,17 @@ static struct phy_driver microchip_t1s_driver[] =3D { PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVC1), .name =3D "LAN867X Rev.C1", .features =3D PHY_BASIC_T1S_P2MP_FEATURES, - .config_init =3D lan867x_revc1_config_init, + .config_init =3D lan867x_revc_config_init, + .read_status =3D lan86xx_read_status, + .get_plca_cfg =3D genphy_c45_plca_get_cfg, + .set_plca_cfg =3D genphy_c45_plca_set_cfg, + .get_plca_status =3D genphy_c45_plca_get_status, + }, + { + PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVC2), + .name =3D "LAN867X Rev.C2", + .features =3D PHY_BASIC_T1S_P2MP_FEATURES, + .config_init =3D lan867x_revc_config_init, .read_status =3D lan86xx_read_status, .get_plca_cfg =3D genphy_c45_plca_get_cfg, .set_plca_cfg =3D genphy_c45_plca_set_cfg, @@ -453,6 +464,7 @@ module_phy_driver(microchip_t1s_driver); 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Thu, 10 Oct 2024 01:22:57 -0700 Received: from che-ll-i17164.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 10 Oct 2024 01:22:53 -0700 From: Parthiban Veerasooran To: , , , , , , , CC: , , , , Subject: [PATCH net-next v4 7/7] net: phy: microchip_t1s: configure collision detection based on PLCA mode Date: Thu, 10 Oct 2024 13:52:05 +0530 Message-ID: <20241010082205.221493-8-parthiban.veerasooran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241010082205.221493-1-parthiban.veerasooran@microchip.com> References: <20241010082205.221493-1-parthiban.veerasooran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As per LAN8650/1 Rev.B0/B1 AN1760 (Revision F (DS60001760G - June 2024)) and LAN8670/1/2 Rev.C1/C2 AN1699 (Revision E (DS60001699F - June 2024)), under normal operation, the device should be operated in PLCA mode. Disabling collision detection is recommended to allow the device to operate in noisy environments or when reflections and other inherent transmission line distortion cause poor signal quality. Collision detection must be re-enabled if the device is configured to operate in CSMA/CD mode. Signed-off-by: Parthiban Veerasooran --- drivers/net/phy/microchip_t1s.c | 42 ++++++++++++++++++++++++++++++--- 1 file changed, 39 insertions(+), 3 deletions(-) diff --git a/drivers/net/phy/microchip_t1s.c b/drivers/net/phy/microchip_t1= s.c index d305c2b1fcd0..75d291154b4c 100644 --- a/drivers/net/phy/microchip_t1s.c +++ b/drivers/net/phy/microchip_t1s.c @@ -26,6 +26,12 @@ #define LAN865X_REG_CFGPARAM_CTRL 0x00DA #define LAN865X_REG_STS2 0x0019 =20 +/* Collision Detector Control 0 Register */ +#define LAN86XX_REG_COL_DET_CTRL0 0x0087 +#define COL_DET_CTRL0_ENABLE_BIT_MASK BIT(15) +#define COL_DET_ENABLE BIT(15) +#define COL_DET_DISABLE 0x0000 + #define LAN865X_CFGPARAM_READ_ENABLE BIT(1) =20 /* The arrays below are pulled from the following table from AN1699 @@ -371,6 +377,36 @@ static int lan867x_revb1_config_init(struct phy_device= *phydev) return 0; } =20 +/* As per LAN8650/1 Rev.B0/B1 AN1760 (Revision F (DS60001760G - June 2024)= ) and + * LAN8670/1/2 Rev.C1/C2 AN1699 (Revision E (DS60001699F - June 2024)), un= der + * normal operation, the device should be operated in PLCA mode. Disabling + * collision detection is recommended to allow the device to operate in no= isy + * environments or when reflections and other inherent transmission line + * distortion cause poor signal quality. Collision detection must be re-en= abled + * if the device is configured to operate in CSMA/CD mode. + * + * AN1760: https://www.microchip.com/en-us/application-notes/an1760 + * AN1699: https://www.microchip.com/en-us/application-notes/an1699 + */ +static int lan86xx_plca_set_cfg(struct phy_device *phydev, + const struct phy_plca_cfg *plca_cfg) +{ + int ret; + + ret =3D genphy_c45_plca_set_cfg(phydev, plca_cfg); + if (ret) + return ret; + + if (plca_cfg->enabled) + return phy_modify_mmd(phydev, MDIO_MMD_VEND2, + LAN86XX_REG_COL_DET_CTRL0, + COL_DET_CTRL0_ENABLE_BIT_MASK, + COL_DET_DISABLE); + + return phy_modify_mmd(phydev, MDIO_MMD_VEND2, LAN86XX_REG_COL_DET_CTRL0, + COL_DET_CTRL0_ENABLE_BIT_MASK, COL_DET_ENABLE); +} + static int lan86xx_read_status(struct phy_device *phydev) { /* The phy has some limitations, namely: @@ -432,7 +468,7 @@ static struct phy_driver microchip_t1s_driver[] =3D { .config_init =3D lan867x_revc_config_init, .read_status =3D lan86xx_read_status, .get_plca_cfg =3D genphy_c45_plca_get_cfg, - .set_plca_cfg =3D genphy_c45_plca_set_cfg, + .set_plca_cfg =3D lan86xx_plca_set_cfg, .get_plca_status =3D genphy_c45_plca_get_status, }, { @@ -442,7 +478,7 @@ static struct phy_driver microchip_t1s_driver[] =3D { .config_init =3D lan867x_revc_config_init, .read_status =3D lan86xx_read_status, .get_plca_cfg =3D genphy_c45_plca_get_cfg, - .set_plca_cfg =3D genphy_c45_plca_set_cfg, + .set_plca_cfg =3D lan86xx_plca_set_cfg, .get_plca_status =3D genphy_c45_plca_get_status, }, { @@ -454,7 +490,7 @@ static struct phy_driver microchip_t1s_driver[] =3D { .read_mmd =3D lan865x_phy_read_mmd, .write_mmd =3D lan865x_phy_write_mmd, .get_plca_cfg =3D genphy_c45_plca_get_cfg, - .set_plca_cfg =3D genphy_c45_plca_set_cfg, + .set_plca_cfg =3D lan86xx_plca_set_cfg, .get_plca_status =3D genphy_c45_plca_get_status, }, }; --=20 2.34.1