From nobody Wed Nov 27 15:55:13 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 781B31F12F5; Thu, 10 Oct 2024 07:39:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728545987; cv=none; b=mxYi6Dfd3EjB6zHjGZE9Ub/h/M/K9svQbPw6mS5ZkwKszg0+w6Du89mDHfnjrermDnUnDI87LZ7UlE/dmZQPnstjAkH/fipXlvKl68HjTRL30l0y5Tk4haToZPaIoon+d6/hHST+oqPnFUimmqEGBBiMN9YiFXoRvfZJ/ToUb4Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728545987; c=relaxed/simple; bh=Mt4aNbf1+4fxCklM/m+VUWDLR8iLJXyT+ug9ZxNv9BQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qPgOiG+LtgxDMfVxCwZQivoDuVq0rtu4n6SF2g+CtHpJMOVTCI+Nkz9pd5kO6uViXuqVW98G/2MlOP6LUQnp7BFTh8E8xSeZBU+xTfWvhrZs4A9ejgQc3M5mpzYkL76ppb10konOfWEjqgpIySuu3Rj/MaaN5ZKiQDeeniEYCIg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=XSf3HzN4; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="XSf3HzN4" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49A1bFHg011324; Thu, 10 Oct 2024 07:39:32 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= WpeitJS+px0Z40hrSszBDSbAZOUw1cJfritt+C+uHQw=; b=XSf3HzN4p7I7APY8 uAA2dqSh+JZqbd/LPQUV3J7Ud0hYDRyk/HahJBhD2sFGLeIaPLVlUAyEnPUhGe1f OJ/9lWScYgC/2/SRuf2+3vekgLPPjDPBsyn/U1sTKwpBnJt1mxB9UpL6HtbOaLdJ jgBiQU5Fhivdl2PSAksw3vMZNsNdPNXx+lCmLxwnpD2rg6sM09IAoopGogP6X4ts 7OHL636MKFVhptXe8iW4YjvYpfd/9ROEjvZse3Oy/m4ubeD4K9L/TE/gY1EGq+V0 G3ba0t5dCqB4514Xymnpvst/1cWB7utYcjCsqdwjaCqiz+8qoXVEf6Y6BSx/JTnb 4uIkMA== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 425xthsmbc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 10 Oct 2024 07:39:32 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49A7dV5R028254 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 10 Oct 2024 07:39:31 GMT Received: from 3b5b8f7e4007.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 10 Oct 2024 00:39:30 -0700 From: Songwei Chai To: Suzuki K Poulose , Mike Leach , James Clark , "Alexander Shishkin" , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Songwei Chai , , , , , Subject: [PATCH v2 1/7] dt-bindings: arm: Add support for Coresight TGU trace Date: Thu, 10 Oct 2024 15:39:09 +0800 Message-ID: <20241010073917.16023-2-quic_songchai@quicinc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241010073917.16023-1-quic_songchai@quicinc.com> References: <20241010073917.16023-1-quic_songchai@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: GBtLtVwBHqoIcpkAxfNrICRUHTUEdcYE X-Proofpoint-GUID: GBtLtVwBHqoIcpkAxfNrICRUHTUEdcYE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 spamscore=0 priorityscore=1501 bulkscore=0 phishscore=0 clxscore=1015 mlxlogscore=999 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410100048 Content-Type: text/plain; charset="utf-8" The Trigger Generation Unit (TGU) is designed to detect patterns or sequences within a specific region of the System on Chip (SoC). Once configured and activated, it monitors sense inputs and can detect a pre-programmed state or sequence across clock cycles, subsequently producing a trigger. TGU configuration space offset table x-------------------------x | | | | | | Step configuration | | space layout | coresight management | x-------------x | registers | |---> | | | | | | reserve | | | | | | |-------------------------| | |-------------| | | | | priority[3] | | step[7] |<-- | |-------------| |-------------------------| | | | priority[2] | | | | | |-------------| | ... | |Steps region | | priority[1] | | | | | |-------------| |-------------------------| | | | priority[0] | | |<-- | |-------------| | step[0] |--------------------> | | |-------------------------| | condition | | | | | | control and status | x-------------x | space | | | x-------------------------x |Timer/Counter| | | x-------------x TGU Configuration in Hardware The TGU provides a step region for user configuration, similar to a flow chart. Each step region consists of three register clusters: 1.Priority Region: Sets the required signals with priority. 2.Condition Region: Defines specific requirements (e.g., signal A reaches three times) and the subsequent action once the requirement is met. 3.Timer/Counter (Optional): Provides timing or counting functionality. Add a new coresight-tgu.yaml file to describe the bindings required to define the TGU in the device trees. Signed-off-by: Songwei Chai --- .../bindings/arm/qcom,coresight-tgu.yaml | 133 ++++++++++++++++++ 1 file changed, 133 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-tg= u.yaml diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tgu.yaml = b/Documentation/devicetree/bindings/arm/qcom,coresight-tgu.yaml new file mode 100644 index 000000000000..25b464486fe2 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tgu.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +# Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/qcom,coresight-tgu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Trigger Generation Unit - TGU + +description: | + The Trigger Generation Unit (TGU) is a Data Engine which can be utilized + to sense a plurality of signals and create a trigger into the CTI or + generate interrupts to processors. The TGU is like the trigger circuit + of a Logic Analyzer.The corresponding trigger logic can be realized by + configuring the conditions for each step after sensing the signal. + Once setup and enabled, it will observe sense inputs and based upon + the activity of those inputs, even over clock cycles, may detect a + preprogrammed state/sequence and then produce a trigger or interrupt. + + The primary use case of the TGU is to detect patterns or sequences on a + given set of signals within some region of the SoC. + +maintainers: + - Mao Jinlong + - Sam Chai + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + enum: + - qcom,coresight-tgu + required: + - compatible + +properties: + compatible: + items: + - const: qcom,coresight-tgu + - const: arm,primecell + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb_pclk + + qcom,tgu-steps: + description: + The trigger logic is realized by configuring each step after sensing + the signal. The parameter here is used to describe the maximum of st= eps + that could be configured in the current TGU. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 8 + + qcom,tgu-regs: + description: + There are some "groups" register clusters in each step, which are us= ed to configure the signal + that we want to detect.Meanwhile, each group has its own priority, a= nd the priority increases + with number of groups.For example, group3 has a higher priority than= group2 ,the signal configured + in group3 will be sensed more preferentially than the signal which i= s configured in group2. + The parameter here is used to describe the signal number that each g= roup could be configured. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 18 + + qcom,tgu-conditions: + description: + A condition sets a specific requirement for a step and defines the s= ubsequent + action once the requirement is met. For example, in step two, if sig= nal A is + detected three times, the process jumps back to step one. The parame= ter describes + the register number for each functionality, whether it is setting a = specific + requirement or defining a subsequent action. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 4 + + qcom,tgu-timer-counters: + description: + TGU has timer and counter which are used to set some requirement on = each step. + For example, we could use counter to create a trigger into CTI once = TGU senses + the target signal three times.This parameter is used to describe the= number of + Timers/Counters in TGU. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 2 + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: AXI Slave connected to another Coresight component + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + tgu@10b0e000 { + compatible =3D "qcom,coresight-tgu", "arm,primecell"; + reg =3D <0x10b0e000 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,tgu-steps =3D <3>; + qcom,tgu-regs =3D <4>; + qcom,tgu-conditions =3D <4>; + qcom,tgu-timer-counters =3D <1>; + + in-ports { + port { + tgu_in_tpdm_swao: endpoint{ + remote-endpoint =3D <&tpdm_swao_out_tgu>; + }; + }; + }; + }; +...