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Thu, 10 Oct 2024 02:57:50 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49A2vnTN006799 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 10 Oct 2024 02:57:49 GMT Received: from yijiyang-gv.ap.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 9 Oct 2024 19:57:45 -0700 From: Yijie Yang Date: Thu, 10 Oct 2024 10:57:18 +0800 Subject: [PATCH 4/5] arm64: dts: qcom: move common parts for qcs8300-ride variants into a .dtsi Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241010-dts_qcs8300-v1-4-bf5acf05830b@quicinc.com> References: <20241010-dts_qcs8300-v1-0-bf5acf05830b@quicinc.com> In-Reply-To: <20241010-dts_qcs8300-v1-0-bf5acf05830b@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran CC: , , , , , , Yijie Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728529047; l=19673; i=quic_yijiyang@quicinc.com; s=20240408; h=from:subject:message-id; bh=6narqRi8KziZ22D1F57NmU8nYnxlF1oonBrL9qPLHWc=; b=PKfP7HcJWt1oyc+LMCDHvIuTec0UxKE1087J+K14w+kH6VcdvAogwqOAloIFZSif8nKwcyhaW +QQrE2L9D6qCQw+NDoa3aw9pa7kO8ON23khKrgN8UJ0MrUAhc7kWOW4 X-Developer-Key: i=quic_yijiyang@quicinc.com; a=ed25519; pk=XvMv0rxjrXLYFdBXoFjTdOdAwDT5SPbQ5uAKGESDihk= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: x9Seg8dZsEatEcqJJ3XHP8x-3zid6MVD X-Proofpoint-GUID: x9Seg8dZsEatEcqJJ3XHP8x-3zid6MVD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 mlxlogscore=999 impostorscore=0 spamscore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 malwarescore=0 adultscore=1 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410100018 In order to support multiple revisions of the qcs8300-ride board, create a .dtsi containing the common parts and split out the ethernet bits into the actual board file as they will change in revision 2. Signed-off-by: Yijie Yang --- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 373 +------------------------= ---- arch/arm64/boot/dts/qcom/qcs8300-ride.dtsi | 364 +++++++++++++++++++++++++= +++ 2 files changed, 377 insertions(+), 360 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dt= s/qcom/qcs8300-ride.dts index b1c9f2cb9749..9b9922f1fcc6 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -5,375 +5,28 @@ =20 /dts-v1/; =20 -#include -#include - -#include "qcs8300.dtsi" +#include "qcs8300-ride.dtsi" / { model =3D "Qualcomm Technologies, Inc. QCS8300 Ride"; compatible =3D "qcom,qcs8300-ride", "qcom,qcs8300"; chassis-type =3D "embedded"; - - aliases { - serial0 =3D &uart7; - }; - - chosen { - stdout-path =3D "serial0:115200n8"; - }; - - clocks { - xo_board_clk: xo-board-clk { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <38400000>; - }; - - sleep_clk: sleep-clk { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <32000>; - }; - }; -}; - -&apps_rsc { - regulators-0 { - compatible =3D "qcom,pmm8654au-rpmh-regulators"; - qcom,pmic-id =3D "a"; - - vreg_s4a: smps4 { - regulator-name =3D "vreg_s4a"; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - regulator-initial-mode =3D ; - }; - - vreg_s9a: smps9 { - regulator-name =3D "vreg_s9a"; - regulator-min-microvolt =3D <1352000>; - regulator-max-microvolt =3D <1352000>; - regulator-initial-mode =3D ; - }; - - vreg_l3a: ldo3 { - regulator-name =3D "vreg_l3a"; - regulator-min-microvolt =3D <1200000>; - regulator-max-microvolt =3D <1200000>; - regulator-initial-mode =3D ; - regulator-allow-set-load; - regulator-allowed-modes =3D ; - }; - - vreg_l4a: ldo4 { - regulator-name =3D "vreg_l4a"; - regulator-min-microvolt =3D <880000>; - regulator-max-microvolt =3D <912000>; - regulator-initial-mode =3D ; - regulator-allow-set-load; - regulator-allowed-modes =3D ; - }; - - vreg_l5a: ldo5 { - regulator-name =3D "vreg_l5a"; - regulator-min-microvolt =3D <1200000>; - regulator-max-microvolt =3D <1200000>; - regulator-initial-mode =3D ; - regulator-allow-set-load; - regulator-allowed-modes =3D ; - }; - - vreg_l6a: ldo6 { - regulator-name =3D "vreg_l6a"; - regulator-min-microvolt =3D <880000>; - regulator-max-microvolt =3D <912000>; - regulator-initial-mode =3D ; - regulator-allow-set-load; - regulator-allowed-modes =3D ; - }; - - vreg_l7a: ldo7 { - regulator-name =3D "vreg_l7a"; - regulator-min-microvolt =3D <880000>; - regulator-max-microvolt =3D <912000>; - regulator-initial-mode =3D ; - regulator-allow-set-load; - regulator-allowed-modes =3D ; - }; - - vreg_l8a: ldo8 { - regulator-name =3D "vreg_l8a"; - regulator-min-microvolt =3D <2504000>; - regulator-max-microvolt =3D <2960000>; - regulator-initial-mode =3D ; - regulator-allow-set-load; - regulator-allowed-modes =3D ; - }; - - vreg_l9a: ldo9 { - regulator-name =3D "vreg_l9a"; - regulator-min-microvolt =3D <2970000>; - regulator-max-microvolt =3D <3072000>; - regulator-initial-mode =3D ; - regulator-allow-set-load; - regulator-allowed-modes =3D ; - }; - }; - - regulators-1 { - compatible =3D "qcom,pmm8654au-rpmh-regulators"; - qcom,pmic-id =3D "c"; - - vreg_s5c: smps5 { - regulator-name =3D "vreg_s5c"; - regulator-min-microvolt =3D <1104000>; - regulator-max-microvolt =3D <1104000>; - regulator-initial-mode =3D ; - }; - - vreg_l1c: ldo1 { - regulator-name =3D "vreg_l1c"; - regulator-min-microvolt =3D <300000>; - regulator-max-microvolt =3D <500000>; - regulator-initial-mode =3D ; - regulator-allow-set-load; - regulator-allowed-modes =3D ; - }; - - vreg_l2c: ldo2 { - regulator-name =3D "vreg_l2c"; - regulator-min-microvolt =3D <900000>; - regulator-max-microvolt =3D <904000>; - regulator-initial-mode =3D ; - regulator-allow-set-load; - regulator-allowed-modes =3D ; - }; - - vreg_l4c: ldo4 { - regulator-name =3D "vreg_l4c"; - regulator-min-microvolt =3D <1200000>; - regulator-max-microvolt =3D <1200000>; - regulator-initial-mode =3D ; - regulator-allow-set-load; - regulator-allowed-modes =3D ; - }; - - vreg_l6c: ldo6 { - regulator-name =3D "vreg_l6c"; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - regulator-initial-mode =3D ; - regulator-allow-set-load; - regulator-allowed-modes =3D ; - }; - - vreg_l7c: ldo7 { - regulator-name =3D "vreg_l7c"; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - regulator-initial-mode =3D ; - regulator-allow-set-load; - regulator-allowed-modes =3D ; - }; - - vreg_l8c: ldo8 { - regulator-name =3D "vreg_l8c"; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - regulator-initial-mode =3D ; - regulator-allow-set-load; - regulator-allowed-modes =3D ; - }; - - vreg_l9c: ldo9 { - regulator-name =3D "vreg_l9c"; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - regulator-initial-mode =3D ; - regulator-allow-set-load; - regulator-allowed-modes =3D ; - }; - }; }; =20 ðernet0 { phy-mode =3D "sgmii"; - phy-handle =3D <&sgmii_phy0>; - - pinctrl-0 =3D <ðernet0_default>; - pinctrl-names =3D "default"; - - snps,mtl-rx-config =3D <&mtl_rx_setup>; - snps,mtl-tx-config =3D <&mtl_tx_setup>; - snps,ps-speed =3D <1000>; - - status =3D "okay"; - - mdio { - compatible =3D "snps,dwmac-mdio"; - #address-cells =3D <1>; - #size-cells =3D <0>; - - sgmii_phy0: phy@8 { - compatible =3D "ethernet-phy-id0141.0dd4"; - reg =3D <0x8>; - device_type =3D "ethernet-phy"; - interrupts-extended =3D <&tlmm 4 IRQ_TYPE_EDGE_FALLING>; - reset-gpios =3D <&tlmm 31 GPIO_ACTIVE_LOW>; - reset-assert-us =3D <11000>; - reset-deassert-us =3D <70000>; - }; - }; - - mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use =3D <4>; - snps,rx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,map-to-dma-channel =3D <0x0>; - snps,route-up; - snps,priority =3D <0x1>; - }; - - queue1 { - snps,dcb-algorithm; - snps,map-to-dma-channel =3D <0x1>; - snps,route-ptp; - }; - - queue2 { - snps,avb-algorithm; - snps,map-to-dma-channel =3D <0x2>; - snps,route-avcp; - }; - - queue3 { - snps,avb-algorithm; - snps,map-to-dma-channel =3D <0x3>; - snps,priority =3D <0xc>; - }; - }; - - mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use =3D <4>; - snps,tx-sched-sp; - - queue0 { - snps,dcb-algorithm; - }; - - queue1 { - snps,dcb-algorithm; - }; - - queue2 { - snps,avb-algorithm; - snps,send_slope =3D <0x1000>; - snps,idle_slope =3D <0x1000>; - snps,high_credit =3D <0x3e800>; - snps,low_credit =3D <0xffc18000>; - }; - - queue3 { - snps,avb-algorithm; - snps,send_slope =3D <0x1000>; - snps,idle_slope =3D <0x1000>; - snps,high_credit =3D <0x3e800>; - snps,low_credit =3D <0xffc18000>; - }; - }; -}; - -&gcc { - clocks =3D <&rpmhcc RPMH_CXO_CLK>, - <&sleep_clk>, - <0>, - <0>, - <0>, - <0>, - <0>, - <0>, - <0>, - <0>; -}; - -&qupv3_id_0 { - status =3D "okay"; }; =20 -&remoteproc_adsp { - firmware-name =3D "qcom/qcs8300/adsp.mbn"; - status =3D "okay"; -}; - -&remoteproc_cdsp { - firmware-name =3D "qcom/qcs8300/cdsp0.mbn"; - status =3D "okay"; -}; - -&remoteproc_gpdsp { - firmware-name =3D "qcom/qcs8300/gpdsp0.mbn"; - status =3D "okay"; -}; - -&rpmhcc { - clocks =3D <&xo_board_clk>; - clock-names =3D "xo"; -}; - -&serdes0 { - phy-supply =3D <&vreg_l5a>; - status =3D "okay"; -}; - -&tlmm { - ethernet0_default: ethernet0-default-state { - ethernet0_mdc: ethernet0-mdc-pins { - pins =3D "gpio5"; - function =3D "emac0_mdc"; - drive-strength =3D <16>; - bias-pull-up; - }; - - ethernet0_mdio: ethernet0-mdio-pins { - pins =3D "gpio6"; - function =3D "emac0_mdio"; - drive-strength =3D <16>; - bias-pull-up; - }; +&mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + sgmii_phy0: phy@8 { + compatible =3D "ethernet-phy-id0141.0dd4"; + reg =3D <0x8>; + device_type =3D "ethernet-phy"; + interrupts-extended =3D <&tlmm 4 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&tlmm 31 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <11000>; + reset-deassert-us =3D <70000>; }; }; - -&uart7 { - status =3D "okay"; -}; - -&ufs_mem_hc { - reset-gpios =3D <&tlmm 133 GPIO_ACTIVE_LOW>; - vcc-supply =3D <&vreg_l8a>; - vcc-max-microamp =3D <1100000>; - vccq-supply =3D <&vreg_l4c>; - vccq-max-microamp =3D <1200000>; - status =3D "okay"; -}; - -&ufs_mem_phy { - vdda-phy-supply =3D <&vreg_l4a>; - vdda-pll-supply =3D <&vreg_l5a>; - status =3D "okay"; -}; diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dtsi b/arch/arm64/boot/d= ts/qcom/qcs8300-ride.dtsi new file mode 100644 index 000000000000..e6099f7d80cb --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dtsi @@ -0,0 +1,364 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include +#include + +#include "qcs8300.dtsi" +/ { + aliases { + serial0 =3D &uart7; + }; + + chosen { + stdout-path =3D "serial0: 115200n8"; + }; + + clocks { + xo_board_clk: xo-board-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <38400000>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32000>; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id =3D "a"; + + vreg_s4a: smps4 { + regulator-name =3D "vreg_s4a"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_s9a: smps9 { + regulator-name =3D "vreg_s9a"; + regulator-min-microvolt =3D <1352000>; + regulator-max-microvolt =3D <1352000>; + regulator-initial-mode =3D ; + }; + + vreg_l3a: ldo3 { + regulator-name =3D "vreg_l3a"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l4a: ldo4 { + regulator-name =3D "vreg_l4a"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l5a: ldo5 { + regulator-name =3D "vreg_l5a"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l6a: ldo6 { + regulator-name =3D "vreg_l6a"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l7a: ldo7 { + regulator-name =3D "vreg_l7a"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l8a: ldo8 { + regulator-name =3D "vreg_l8a"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <2960000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l9a: ldo9 { + regulator-name =3D "vreg_l9a"; + regulator-min-microvolt =3D <2970000>; + regulator-max-microvolt =3D <3072000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id =3D "c"; + + vreg_s5c: smps5 { + regulator-name =3D "vreg_s5c"; + regulator-min-microvolt =3D <1104000>; + regulator-max-microvolt =3D <1104000>; + regulator-initial-mode =3D ; + }; + + vreg_l1c: ldo1 { + regulator-name =3D "vreg_l1c"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <500000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2c: ldo2 { + regulator-name =3D "vreg_l2c"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <904000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l4c: ldo4 { + regulator-name =3D "vreg_l4c"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l6c: ldo6 { + regulator-name =3D "vreg_l6c"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l7c: ldo7 { + regulator-name =3D "vreg_l7c"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l8c: ldo8 { + regulator-name =3D "vreg_l8c"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l9c: ldo9 { + regulator-name =3D "vreg_l9c"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; +}; + +ðernet0 { + phy-handle =3D <&sgmii_phy0>; + + pinctrl-0 =3D <ðernet0_default>; + pinctrl-names =3D "default"; + + snps,mtl-rx-config =3D <&mtl_rx_setup>; + snps,mtl-tx-config =3D <&mtl_tx_setup>; + snps,ps-speed =3D <1000>; + + status =3D "okay"; + + mdio: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + snps,route-up; + snps,priority =3D <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel =3D <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel =3D <0x3>; + snps,priority =3D <0xc>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <4>; + snps,tx-sched-sp; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope =3D <0x1000>; + snps,idle_slope =3D <0x1000>; + snps,high_credit =3D <0x3e800>; + snps,low_credit =3D <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope =3D <0x1000>; + snps,idle_slope =3D <0x1000>; + snps,high_credit =3D <0x3e800>; + snps,low_credit =3D <0xffc18000>; + }; + }; +}; + +&gcc { + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&remoteproc_adsp { + firmware-name =3D "qcom/qcs8300/adsp.mbn"; + status =3D "okay"; +}; + +&remoteproc_cdsp { + firmware-name =3D "qcom/qcs8300/cdsp0.mbn"; + status =3D "okay"; +}; + +&remoteproc_gpdsp { + firmware-name =3D "qcom/qcs8300/gpdsp0.mbn"; + status =3D "okay"; +}; + +&rpmhcc { + clocks =3D <&xo_board_clk>; + clock-names =3D "xo"; +}; + +&serdes0 { + phy-supply =3D <&vreg_l5a>; + status =3D "okay"; +}; + +&tlmm { + ethernet0_default: ethernet0-default-state { + ethernet0_mdc: ethernet0-mdc-pins { + pins =3D "gpio5"; + function =3D "emac0_mdc"; + drive-strength =3D <16>; + bias-pull-up; + }; + + ethernet0_mdio: ethernet0-mdio-pins { + pins =3D "gpio6"; + function =3D "emac0_mdio"; + drive-strength =3D <16>; + bias-pull-up; + }; + }; +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 133 GPIO_ACTIVE_LOW>; + vcc-supply =3D <&vreg_l8a>; + vcc-max-microamp =3D <1100000>; + vccq-supply =3D <&vreg_l4c>; + vccq-max-microamp =3D <1200000>; + status =3D "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l4a>; + vdda-pll-supply =3D <&vreg_l5a>; + status =3D "okay"; +}; + +&uart7 { + status =3D "okay"; +}; --=20 2.34.1