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Thu, 10 Oct 2024 02:57:45 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49A2vjxq028412 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 10 Oct 2024 02:57:45 GMT Received: from yijiyang-gv.ap.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 9 Oct 2024 19:57:41 -0700 From: Yijie Yang Date: Thu, 10 Oct 2024 10:57:17 +0800 Subject: [PATCH 3/5] arm64: dts: qcom: qcs8300-ride: enable ethernet0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241010-dts_qcs8300-v1-3-bf5acf05830b@quicinc.com> References: <20241010-dts_qcs8300-v1-0-bf5acf05830b@quicinc.com> In-Reply-To: <20241010-dts_qcs8300-v1-0-bf5acf05830b@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran CC: , , , , , , Yijie Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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Add the MDC and MDIO pin functions for ethernet0 on qcs8300-ride. Enable the first 1Gb ethernet port on qcs8300-ride development board. Signed-off-by: Yijie Yang --- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 112 ++++++++++++++++++++++++++= ++++ 1 file changed, 112 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dt= s/qcom/qcs8300-ride.dts index 7eed19a694c3..b1c9f2cb9749 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -210,6 +210,95 @@ vreg_l9c: ldo9 { }; }; =20 +ðernet0 { + phy-mode =3D "sgmii"; + phy-handle =3D <&sgmii_phy0>; + + pinctrl-0 =3D <ðernet0_default>; + pinctrl-names =3D "default"; + + snps,mtl-rx-config =3D <&mtl_rx_setup>; + snps,mtl-tx-config =3D <&mtl_tx_setup>; + snps,ps-speed =3D <1000>; + + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + sgmii_phy0: phy@8 { + compatible =3D "ethernet-phy-id0141.0dd4"; + reg =3D <0x8>; + device_type =3D "ethernet-phy"; + interrupts-extended =3D <&tlmm 4 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&tlmm 31 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <11000>; + reset-deassert-us =3D <70000>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + snps,route-up; + snps,priority =3D <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel =3D <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel =3D <0x3>; + snps,priority =3D <0xc>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <4>; + snps,tx-sched-sp; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope =3D <0x1000>; + snps,idle_slope =3D <0x1000>; + snps,high_credit =3D <0x3e800>; + snps,low_credit =3D <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope =3D <0x1000>; + snps,idle_slope =3D <0x1000>; + snps,high_credit =3D <0x3e800>; + snps,low_credit =3D <0xffc18000>; + }; + }; +}; + &gcc { clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, @@ -247,6 +336,29 @@ &rpmhcc { clock-names =3D "xo"; }; =20 +&serdes0 { + phy-supply =3D <&vreg_l5a>; + status =3D "okay"; +}; + +&tlmm { + ethernet0_default: ethernet0-default-state { + ethernet0_mdc: ethernet0-mdc-pins { + pins =3D "gpio5"; + function =3D "emac0_mdc"; + drive-strength =3D <16>; + bias-pull-up; + }; + + ethernet0_mdio: ethernet0-mdio-pins { + pins =3D "gpio6"; + function =3D "emac0_mdio"; + drive-strength =3D <16>; + bias-pull-up; + }; + }; +}; + &uart7 { status =3D "okay"; }; --=20 2.34.1