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Thu, 10 Oct 2024 03:06:00 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49A35xKR027727 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 10 Oct 2024 03:06:00 GMT Received: from yijiyang-gv.ap.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 9 Oct 2024 20:05:55 -0700 From: Yijie Yang Date: Thu, 10 Oct 2024 11:05:36 +0800 Subject: [PATCH 1/2] arm64: dts: qcom: qcs615: add ethernet node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241010-dts_qcs615-v1-1-05f27f6ac4d3@quicinc.com> References: <20241010-dts_qcs615-v1-0-05f27f6ac4d3@quicinc.com> In-Reply-To: <20241010-dts_qcs615-v1-0-05f27f6ac4d3@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran CC: , , , , , , Yijie Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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Signed-off-by: Yijie Yang --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qco= m/qcs615.dtsi index 0d8fb557cf48..ba737cd89679 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -420,6 +420,33 @@ soc: soc@0 { #address-cells =3D <2>; #size-cells =3D <2>; =20 + ethernet: ethernet@20000 { + compatible =3D "qcom,qcs615-ethqos", "qcom,sm8150-ethqos"; + reg =3D <0x0 0x20000 0x0 0x10000>, + <0x0 0x36000 0x0 0x100>; + reg-names =3D "stmmaceth", "rgmii"; + + clocks =3D <&gcc GCC_EMAC_AXI_CLK>, + <&gcc GCC_EMAC_SLV_AHB_CLK>, + <&gcc GCC_EMAC_PTP_CLK>, + <&gcc GCC_EMAC_RGMII_CLK>; + clock-names =3D "stmmaceth", "pclk", "ptp_ref", "rgmii"; + + interrupts =3D , + ; + interrupt-names =3D "macirq", "eth_lpi"; + + power-domains =3D <&gcc EMAC_GDSC>; + iommus =3D <&apps_smmu 0x1c0 0x0>; + + snps,tso; + snps,pbl =3D <32>; + rx-fifo-depth =3D <16384>; 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Signed-off-by: Yijie Yang --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 105 +++++++++++++++++++++++++++= ++++ 1 file changed, 105 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts= /qcom/qcs615-ride.dts index 538e697e2dac..3d3c9edd860b 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -5,6 +5,7 @@ /dts-v1/; =20 #include +#include #include "qcs615.dtsi" #include "qcs615-pmic.dtsi" =20 @@ -201,6 +202,60 @@ vreg_l17a: ldo17 { }; }; =20 +ðernet { + status =3D "okay"; + + pinctrl-0 =3D <ðernet_defaults>; + pinctrl-names =3D "default"; + + phy-handle =3D <&rgmii_phy>; + phy-mode =3D "rgmii"; + max-speed =3D <1000>; + + snps,mtl-rx-config =3D <&mtl_rx_setup>; + snps,mtl-tx-config =3D <&mtl_tx_setup>; + + mdio: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + rgmii_phy: phy@7 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x7>; + + interrupts-extended =3D <&tlmm 121 IRQ_TYPE_EDGE_FALLING>; + device_type =3D "ethernet-phy"; + reset-gpios =3D <&tlmm 104 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <11000>; + reset-deassert-us =3D <70000>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <1>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + snps,route-up; + snps,priority =3D <0x1>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <1>; + snps,tx-sched-wrr; + + queue0 { + snps,weight =3D <0x10>; + snps,dcb-algorithm; + snps,priority =3D <0x0>; + }; + }; +}; + &gcc { clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, @@ -292,6 +347,56 @@ &mdss_dsi0_phy { vdds-supply =3D <&vreg_l5a>; }; =20 +&tlmm { + ethernet_defaults: ethernet-defaults-state { + mdc-pins { + pins =3D "gpio113"; + function =3D "rgmii"; + bias-pull-up; + }; + + mdio-pins { + pins =3D "gpio114"; + function =3D "rgmii"; + bias-pull-up; + }; + + rgmii-rx-pins { + pins =3D "gpio81", "gpio82", "gpio83", "gpio102", "gpio103", "gpio112"; + function =3D "rgmii"; + bias-disable; + drive-strength =3D <2>; + }; + + rgmii-tx-pins { + pins =3D "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97"; + function =3D "rgmii"; + bias-pull-up; + drive-strength =3D <16>; + }; + + phy-intr-pins { + pins =3D "gpio121"; + function =3D "gpio"; + bias-disable; + drive-strength =3D <8>; + }; + + pps-pins { + pins =3D "gpio91"; + function =3D "rgmii"; + bias-disable; + drive-strength =3D <8>; + }; + + phy-reset-pins { + pins =3D "gpio104"; + function =3D "gpio"; + bias-pull-up; + drive-strength =3D <16>; + }; + }; +}; =20 &tlmm { ioexp_intr_active: ioexp_intr_active { --=20 2.34.1