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AJvYcCVufpgBS3ob94bH0ZZITfFbj1yrDdv5k5beJAtVP5CWdbWT6KV0rvgo1Va3EDZ8ON3ahgHJgri9c/KEnadf@vger.kernel.org, AJvYcCWdPAdDNcQQ79ye5q/iyiPpdOX2NG2TDFmy5Ug0Eys3P0cpz7RCWUCmWMQq4dr3ZEUYNDRHQVMv2/df@vger.kernel.org X-Gm-Message-State: AOJu0YxxhoRhNFZDEpgp39MEmISUoAy18LYRIpixGhU+Hdj2sfWN1zaG JwmjD3LprP4YA92annBEsKidURU3knFYW1Pl9IB3YrgCFgkv0zn8 X-Google-Smtp-Source: AGHT+IEKuoY00MBONYoYEZvNUwHwFgGZe++kurc8BivmtPoW128dTz3seqWpdUhyU5wFto11gZmpkA== X-Received: by 2002:a17:903:189:b0:20b:b0c1:712b with SMTP id d9443c01a7336-20c63726b02mr69101965ad.15.1728513877101; Wed, 09 Oct 2024 15:44:37 -0700 (PDT) Received: from localhost ([2001:da8:7001:11::cb]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c1393107asm75591135ad.156.2024.10.09.15.44.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 15:44:36 -0700 (PDT) From: Inochi Amaoto To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Peter Zijlstra , Chen Wang , Inochi Amaoto , Guo Ren , Lad Prabhakar , Heikki Krogerus , Yangyu Chen , Jinyu Tang , Hal Feng , Geert Uytterhoeven Cc: Yixun Lan , Inochi Amaoto , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v2 1/3] dt-bindings: interrupt-controller: Add Sophgo SG2044 ACLINT SSWI Date: Thu, 10 Oct 2024 06:44:07 +0800 Message-ID: <20241009224410.53188-2-inochiama@gmail.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241009224410.53188-1-inochiama@gmail.com> References: <20241009224410.53188-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Sophgo SG2044 has a new version of T-HEAD C920, which implement a fully featured ACLINT device. This ACLINT has an extra SSWI field to support fast S-mode IPI. Add necessary compatible string for the T-HEAD ACLINT sswi device. Signed-off-by: Inochi Amaoto Reviewed-by: Conor Dooley --- .../thead,c900-aclint-sswi.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= thead,c900-aclint-sswi.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c= 900-aclint-sswi.yaml b/Documentation/devicetree/bindings/interrupt-controll= er/thead,c900-aclint-sswi.yaml new file mode 100644 index 000000000000..0106fbf3ea1f --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-acl= int-sswi.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-= sswi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo sg2044 ACLINT Supervisor-level Software Interrupt Device + +maintainers: + - Inochi Amaoto + +description: + The SSWI device is a part of the riscv ACLINT device. It provides + supervisor-level IPI functionality for a set of HARTs on a RISC-V + platform. It provides a register to set an IPI (SETSSIP) for each + HART connected to the SSWI device. + +properties: + compatible: + items: + - enum: + - sophgo,sg2044-aclint-sswi + - const: thead,c900-aclint-sswi + + reg: + maxItems: 1 + + "#interrupt-cells": + const: 0 + + interrupt-controller: true + + interrupts-extended: + minItems: 1 + maxItems: 4095 + +additionalProperties: false + +required: + - compatible + - reg + - "#interrupt-cells" + - interrupt-controller + - interrupts-extended + +examples: + - | + interrupt-controller@94000000 { + compatible =3D "sophgo,sg2044-aclint-sswi", "thead,c900-aclint-sswi"; + reg =3D <0x94000000 0x00004000>; + #interrupt-cells =3D <0>; + interrupt-controller; + interrupts-extended =3D <&cpu1intc 1>, + <&cpu2intc 1>, + <&cpu3intc 1>, + <&cpu4intc 1>; + }; +... --=20 2.47.0 From nobody Wed Nov 27 12:58:31 2024 Received: from mail-pf1-f172.google.com (mail-pf1-f172.google.com [209.85.210.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A5D11E3DDC; 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Wed, 09 Oct 2024 15:44:39 -0700 (PDT) Received: from localhost ([2001:da8:7001:11::cb]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7e9f680a681sm8792461a12.14.2024.10.09.15.44.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 15:44:39 -0700 (PDT) From: Inochi Amaoto To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Peter Zijlstra , Chen Wang , Inochi Amaoto , Guo Ren , Lad Prabhakar , Heikki Krogerus , Yangyu Chen , Jinyu Tang , Hal Feng , Geert Uytterhoeven Cc: Yixun Lan , Inochi Amaoto , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v2 2/3] irqchip: add T-HEAD C900 ACLINT SSWI driver Date: Thu, 10 Oct 2024 06:44:08 +0800 Message-ID: <20241009224410.53188-3-inochiama@gmail.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241009224410.53188-1-inochiama@gmail.com> References: <20241009224410.53188-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a driver for the T-HEAD C900 ACLINT SSWI device, which is an enhanced implementation of the RISC-V ACLINT SSWI specification. This device allows the system to send ipi via fast device interface. Signed-off-by: Inochi Amaoto --- drivers/irqchip/Kconfig | 10 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-thead-c900-aclint-sswi.c | 166 +++++++++++++++++++ include/linux/cpuhotplug.h | 1 + 4 files changed, 178 insertions(+) create mode 100644 drivers/irqchip/irq-thead-c900-aclint-sswi.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 341cd9ca5a05..32671385cbb7 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -611,6 +611,16 @@ config STARFIVE_JH8100_INTC =20 If you don't know what to do here, say Y. =20 +config THEAD_C900_ACLINT_SSWI + bool "THEAD C9XX ACLINT S-mode IPI Interrupt Controller" + depends on RISCV + select IRQ_DOMAIN_HIERARCHY + help + This enables support for T-HEAD specific ACLINT SSWI device + support. + + If you don't know what to do here, say Y. + config EXYNOS_IRQ_COMBINER bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index e3679ec2b9f7..583418261253 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -101,6 +101,7 @@ obj-$(CONFIG_RISCV_APLIC_MSI) +=3D irq-riscv-aplic-msi= .o obj-$(CONFIG_RISCV_IMSIC) +=3D irq-riscv-imsic-state.o irq-riscv-imsic-ea= rly.o irq-riscv-imsic-platform.o obj-$(CONFIG_SIFIVE_PLIC) +=3D irq-sifive-plic.o obj-$(CONFIG_STARFIVE_JH8100_INTC) +=3D irq-starfive-jh8100-intc.o +obj-$(CONFIG_THEAD_C900_ACLINT_SSWI) +=3D irq-thead-c900-aclint-sswi.o obj-$(CONFIG_IMX_IRQSTEER) +=3D irq-imx-irqsteer.o obj-$(CONFIG_IMX_INTMUX) +=3D irq-imx-intmux.o obj-$(CONFIG_IMX_MU_MSI) +=3D irq-imx-mu-msi.o diff --git a/drivers/irqchip/irq-thead-c900-aclint-sswi.c b/drivers/irqchip= /irq-thead-c900-aclint-sswi.c new file mode 100644 index 000000000000..b96d3b81dc14 --- /dev/null +++ b/drivers/irqchip/irq-thead-c900-aclint-sswi.c @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Inochi Amaoto + */ + +#define pr_fmt(fmt) "thead-c900-aclint-sswi: " fmt +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ACLINT_xSWI_REGISTER_SIZE 4 + +static int sswi_ipi_virq __ro_after_init; +static DEFINE_PER_CPU(void __iomem *, sswi_cpu_regs); + +static void thead_aclint_sswi_ipi_send(unsigned int cpu) +{ + writel_relaxed(0x1, per_cpu(sswi_cpu_regs, cpu)); +} + +static void thead_aclint_sswi_ipi_clear(void) +{ + writel_relaxed(0x0, this_cpu_read(sswi_cpu_regs)); +} + +static void thead_aclint_sswi_ipi_handle(struct irq_desc *desc) +{ + struct irq_chip *chip =3D irq_desc_get_chip(desc); + + chained_irq_enter(chip, desc); + + csr_clear(CSR_IP, IE_SIE); + thead_aclint_sswi_ipi_clear(); + + ipi_mux_process(); + + chained_irq_exit(chip, desc); +} + +static int thead_aclint_sswi_starting_cpu(unsigned int cpu) +{ + enable_percpu_irq(sswi_ipi_virq, irq_get_trigger_type(sswi_ipi_virq)); + + return 0; +} + +static int thead_aclint_sswi_dying_cpu(unsigned int cpu) +{ + thead_aclint_sswi_ipi_clear(); + + disable_percpu_irq(sswi_ipi_virq); + + return 0; +} + +static int __init aclint_sswi_parse_irq(struct fwnode_handle *fwnode, + void __iomem *reg) +{ + struct of_phandle_args parent; + unsigned long hartid; + u32 contexts, i; + int rc, cpu; + + contexts =3D of_irq_count(to_of_node(fwnode)); + if (!(contexts)) { + pr_err("%pfwP: no ACLINT SSWI context available\n", fwnode); + return -EINVAL; + } + + for (i =3D 0; i < contexts; i++) { + rc =3D of_irq_parse_one(to_of_node(fwnode), i, &parent); + if (rc) + return rc; + + rc =3D riscv_of_parent_hartid(parent.np, &hartid); + if (rc) + return rc; + + if (parent.args[0] !=3D RV_IRQ_SOFT) + return -ENOTSUPP; + + cpu =3D riscv_hartid_to_cpuid(hartid); + + per_cpu(sswi_cpu_regs, cpu) =3D reg + i * ACLINT_xSWI_REGISTER_SIZE; + } + + pr_info("%pfwP: register %u CPU%s\n", fwnode, contexts, str_plural(contex= ts)); + + return 0; +} + +static int __init aclint_sswi_probe(struct fwnode_handle *fwnode) +{ + struct irq_domain *domain; + void __iomem *reg; + int virq, rc; + + if (!is_of_node(fwnode)) + return -EINVAL; + + reg =3D of_iomap(to_of_node(fwnode), 0); + if (!reg) + return -ENOMEM; + + /* Parse SSWI setting */ + rc =3D aclint_sswi_parse_irq(fwnode, reg); + if (rc < 0) + return rc; + + /* If mulitple SSWI devices are present, do not register irq again */ + if (sswi_ipi_virq) + return 0; + + /* Find riscv intc domain and create IPI irq mapping */ + domain =3D irq_find_matching_fwnode(riscv_get_intc_hwnode(), DOMAIN_BUS_A= NY); + if (!domain) { + pr_err("%pfwP: Failed to find INTC domain\n", fwnode); + return -ENOENT; + } + + sswi_ipi_virq =3D irq_create_mapping(domain, RV_IRQ_SOFT); + if (!sswi_ipi_virq) { + pr_err("unable to create ACLINT SSWI IRQ mapping\n"); + return -ENOMEM; + } + + /* Register SSWI irq and handler */ + virq =3D ipi_mux_create(BITS_PER_BYTE, thead_aclint_sswi_ipi_send); + if (virq <=3D 0) { + pr_err("unable to create muxed IPIs\n"); + irq_dispose_mapping(sswi_ipi_virq); + return virq < 0 ? virq : -ENOMEM; + } + + irq_set_chained_handler(sswi_ipi_virq, thead_aclint_sswi_ipi_handle); + + cpuhp_setup_state(CPUHP_AP_IRQ_THEAD_ACLINT_SSWI_STARTING, + "irqchip/thead-aclint-sswi:starting", + thead_aclint_sswi_starting_cpu, + thead_aclint_sswi_dying_cpu); + + riscv_ipi_set_virq_range(virq, BITS_PER_BYTE); + + /* Announce that SSWI is providing IPIs */ + pr_info("providing IPIs using THEAD ACLINT SSWI\n"); + + return 0; +} + +static int __init aclint_sswi_early_probe(struct device_node *node, + struct device_node *parent) +{ + return aclint_sswi_probe(&node->fwnode); +} +IRQCHIP_DECLARE(thead_aclint_sswi, "thead,c900-aclint-sswi", aclint_sswi_e= arly_probe); diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index 2361ed4d2b15..799052249c7b 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -147,6 +147,7 @@ enum cpuhp_state { CPUHP_AP_IRQ_EIOINTC_STARTING, CPUHP_AP_IRQ_AVECINTC_STARTING, CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, + CPUHP_AP_IRQ_THEAD_ACLINT_SSWI_STARTING, CPUHP_AP_IRQ_RISCV_IMSIC_STARTING, CPUHP_AP_IRQ_RISCV_SBI_IPI_STARTING, CPUHP_AP_ARM_MVEBU_COHERENCY, --=20 2.47.0 From nobody Wed Nov 27 12:58:31 2024 Received: from mail-pf1-f174.google.com (mail-pf1-f174.google.com [209.85.210.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E2FAF1E47AF; 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Wed, 09 Oct 2024 15:44:42 -0700 (PDT) Received: from localhost ([2001:da8:7001:11::cb]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71df0ccdb93sm8265778b3a.55.2024.10.09.15.44.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 15:44:41 -0700 (PDT) From: Inochi Amaoto To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Peter Zijlstra , Chen Wang , Inochi Amaoto , Guo Ren , Lad Prabhakar , Heikki Krogerus , Yangyu Chen , Jinyu Tang , Hal Feng , Geert Uytterhoeven Cc: Yixun Lan , Inochi Amaoto , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v2 3/3] riscv: defconfig: Enable T-HEAD C900 ACLINT SSWI drivers Date: Thu, 10 Oct 2024 06:44:09 +0800 Message-ID: <20241009224410.53188-4-inochiama@gmail.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241009224410.53188-1-inochiama@gmail.com> References: <20241009224410.53188-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for T-HEAD C900 ACLINT SSWI irqchip. Signed-off-by: Inochi Amaoto --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 2341393cfac1..5b1d6325df85 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -256,6 +256,7 @@ CONFIG_RPMSG_CTRL=3Dy CONFIG_RPMSG_VIRTIO=3Dy CONFIG_PM_DEVFREQ=3Dy CONFIG_IIO=3Dy +CONFIG_THEAD_C900_ACLINT_SSWI=3Dy CONFIG_PHY_SUN4I_USB=3Dm CONFIG_PHY_STARFIVE_JH7110_DPHY_RX=3Dm CONFIG_PHY_STARFIVE_JH7110_PCIE=3Dm --=20 2.47.0