From nobody Wed Nov 27 14:26:49 2024 Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C21701FF7C5 for ; Wed, 9 Oct 2024 15:49:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728489001; cv=none; b=orGl48WtRwcQFymzyBYW4WstsDu3AtcF2rh7ek46VerXXyNgY9QhzvcIEgZaoBwSN6qRYV+Q6lOhYgZYIUwSEA3FIyibKhbVAK3QShV6W7g9kfpvwsT29hhnkPY6imsMyA4mFou6ht2xg7SWqufCvI5yMP6q++Xh/222pzjoBX8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728489001; c=relaxed/simple; bh=LPFOToixC43DMJpxxdLhELluVDI5pW/ki1X7rgFZYA4=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=SgENtU2wwfnEULYZiRN/pI75vxm1lQQBnzAzmsB08WmYrpQddITtU4oeq1HWctbRTL4Doac9wBHCPgiCWpDnsF6rd8JysKqmKn/S0hnsYUKoH7bkQO3t1yApdc0wxpQ1pFqchpnf2yGqx9yZ89CuIEX/D2PwHfvLMI/Dowk0Umk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=ZDEVa4PD; arc=none smtp.client-ip=209.85.128.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="ZDEVa4PD" Received: by mail-yw1-f202.google.com with SMTP id 00721157ae682-6e26ba37314so376207b3.0 for ; Wed, 09 Oct 2024 08:49:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1728488998; x=1729093798; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=+3zZkwU+2EpnRGguJhn2Ww+Ghmvy6uOMqwsBdHy8Row=; b=ZDEVa4PDOhQ1q/Q0LSGFJku8Btp1er6OCVG6vGwD+/yDBR6aZA8GPUOV3Vb10jIHvM 7ok0cW2YCsnop9udUND3nhQjNn2vFzZfinkObODIfkztzLYczolMRha4Vw7+444EyiiC rOdmLaGO3uabbVEg98u9vyRSumhJ+YgscW6mfRG3l5Bh0NSQipcyDps4PAv9IaEX6B0L Jn5n5MdDIfIkEjsyirpaA2oGAF78rdWuvvIrG4qCAGVm8bcsuLXxDo16cWsMy+9JNie1 JK73gvZOikKA5YsCekCCRo9SKVlEBEGju00xWZjS9QcDr6C0cmIT3wII/Y7AsKFpT/Zj fRqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728488998; x=1729093798; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=+3zZkwU+2EpnRGguJhn2Ww+Ghmvy6uOMqwsBdHy8Row=; b=MsDNHUdmOR43bJQ6iZaaMZ+d/otrOBi5f+XuFMcsZJtQYe5F9DParIch8ZgOa9fUyR lwYsr/Q5rCPFPRHGD3xw+7Wur08c6X8mL/qYBY+8HcNIBuJF9REp1xr6wo/sj3pxT9Rf /rPkYr4HKW3MFoNyn3kjQC3fuZPntqPoOwmWaiViB2y5NqGly1I/zH6PKJNYefobFoYr ktNpu1pz0d2fjX8/GRmsBRKamnSi1jLnc/Oyvz4vYdkELSHqNpBe2sbpS4QwB31zEH3Z oam/NtkO2BfQ3j3Dwv8aWuO/EZHhSA71ybvCQ4UUAV/E7MlJEQr2TKGCutqmAs84wqXG 1TSw== X-Forwarded-Encrypted: i=1; AJvYcCXAjFwL9oI1JJRMmKMtIY2zk171jdJurlz/I7C6MSFiIy4CW8bvQmVfvI3RCDFBCbxdFmBVu03kty/T2xQ=@vger.kernel.org X-Gm-Message-State: AOJu0YyKBqU0qIUP/6EUGlymScdW9Ofs5M6cX+58sZC6qw9nS42X47wc phGSciFqcsRMNnsZ1Du/lXKUMfl7Pd71F/ObhaPoXeSM2WJkKMJWQRQ+S2CE8cp5rPwm7J8HEly vfw== X-Google-Smtp-Source: AGHT+IGq8S+cJ3hbYyw4prFkdU6bbiVB3Ddo6czJU4p6VUDHrgM9P6PS5yQttOYl+xpjVaNBwpEpnchtMNk= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:9d:3983:ac13:c240]) (user=seanjc job=sendgmr) by 2002:a05:690c:460d:b0:6db:89f0:b897 with SMTP id 00721157ae682-6e3221683d8mr69407b3.4.1728488997664; Wed, 09 Oct 2024 08:49:57 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 9 Oct 2024 08:49:40 -0700 In-Reply-To: <20241009154953.1073471-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241009154953.1073471-1-seanjc@google.com> X-Mailer: git-send-email 2.47.0.rc0.187.ge670bccf7e-goog Message-ID: <20241009154953.1073471-2-seanjc@google.com> Subject: [PATCH v3 01/14] KVM: Move KVM_REG_SIZE() definition to common uAPI header From: Sean Christopherson To: Marc Zyngier , Oliver Upton , Anup Patel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Paolo Bonzini , Christian Borntraeger , Janosch Frank , Claudio Imbrenda Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Sean Christopherson , Andrew Jones , James Houghton Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Define KVM_REG_SIZE() in the common kvm.h header, and delete the arm64 and RISC-V versions. As evidenced by the surrounding definitions, all aspects of the register size encoding are generic, i.e. RISC-V should have moved arm64's definition to common code instead of copy+pasting. Signed-off-by: Sean Christopherson Acked-by: Anup Patel --- arch/arm64/include/uapi/asm/kvm.h | 3 --- arch/riscv/include/uapi/asm/kvm.h | 3 --- include/uapi/linux/kvm.h | 4 ++++ 3 files changed, 4 insertions(+), 6 deletions(-) diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/as= m/kvm.h index 964df31da975..80b26134e59e 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -43,9 +43,6 @@ #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 #define KVM_DIRTY_LOG_PAGE_OFFSET 64 =20 -#define KVM_REG_SIZE(id) \ - (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) - struct kvm_regs { struct user_pt_regs regs; /* sp =3D sp_el0 */ =20 diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index e97db3296456..4f8d0c04a47b 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -207,9 +207,6 @@ struct kvm_riscv_sbi_sta { #define KVM_RISCV_TIMER_STATE_OFF 0 #define KVM_RISCV_TIMER_STATE_ON 1 =20 -#define KVM_REG_SIZE(id) \ - (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) - /* If you need to interpret the index values, here is the key: */ #define KVM_REG_RISCV_TYPE_MASK 0x00000000FF000000 #define KVM_REG_RISCV_TYPE_SHIFT 24 diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 637efc055145..9deeb13e3e01 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -1070,6 +1070,10 @@ struct kvm_dirty_tlb { =20 #define KVM_REG_SIZE_SHIFT 52 #define KVM_REG_SIZE_MASK 0x00f0000000000000ULL + +#define KVM_REG_SIZE(id) \ + (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT)) + #define KVM_REG_SIZE_U8 0x0000000000000000ULL #define KVM_REG_SIZE_U16 0x0010000000000000ULL #define KVM_REG_SIZE_U32 0x0020000000000000ULL --=20 2.47.0.rc0.187.ge670bccf7e-goog From nobody Wed Nov 27 14:26:49 2024 Received: from mail-yb1-f201.google.com (mail-yb1-f201.google.com [209.85.219.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6C041FF7CD for ; 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Wed, 09 Oct 2024 08:49:59 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 9 Oct 2024 08:49:41 -0700 In-Reply-To: <20241009154953.1073471-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241009154953.1073471-1-seanjc@google.com> X-Mailer: git-send-email 2.47.0.rc0.187.ge670bccf7e-goog Message-ID: <20241009154953.1073471-3-seanjc@google.com> Subject: [PATCH v3 02/14] KVM: selftests: Disable strict aliasing From: Sean Christopherson To: Marc Zyngier , Oliver Upton , Anup Patel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Paolo Bonzini , Christian Borntraeger , Janosch Frank , Claudio Imbrenda Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Sean Christopherson , Andrew Jones , James Houghton Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Disable strict aliasing, as has been done in the kernel proper for decades (literally since before git history) to fix issues where gcc will optimize away loads in code that looks 100% correct, but is _technically_ undefined behavior, and thus can be thrown away by the compiler. E.g. arm64's vPMU counter access test casts a uint64_t (unsigned long) pointer to a u64 (unsigned long long) pointer when setting PMCR.N via u64p_replace_bits(), which gcc-13 detects and optimizes away, i.e. ignores the result and uses the original PMCR. The issue is most easily observed by making set_pmcr_n() noinline and wrapping the call with printf(), e.g. sans comments, for this code: printf("orig =3D %lx, next =3D %lx, want =3D %lu\n", pmcr_orig, pmcr, pmc= r_n); set_pmcr_n(&pmcr, pmcr_n); printf("orig =3D %lx, next =3D %lx, want =3D %lu\n", pmcr_orig, pmcr, pmc= r_n); gcc-13 generates: 0000000000401c90 : 401c90: f9400002 ldr x2, [x0] 401c94: b3751022 bfi x2, x1, #11, #5 401c98: f9000002 str x2, [x0] 401c9c: d65f03c0 ret 0000000000402660 : 402724: aa1403e3 mov x3, x20 402728: aa1503e2 mov x2, x21 40272c: aa1603e0 mov x0, x22 402730: aa1503e1 mov x1, x21 402734: 940060ff bl 41ab30 <_IO_printf> 402738: aa1403e1 mov x1, x20 40273c: 910183e0 add x0, sp, #0x60 402740: 97fffd54 bl 401c90 402744: aa1403e3 mov x3, x20 402748: aa1503e2 mov x2, x21 40274c: aa1503e1 mov x1, x21 402750: aa1603e0 mov x0, x22 402754: 940060f7 bl 41ab30 <_IO_printf> with the value stored in [sp + 0x60] ignored by both printf() above and in the test proper, resulting in a false failure due to vcpu_set_reg() simply storing the original value, not the intended value. $ ./vpmu_counter_access Random seed: 0x6b8b4567 orig =3D 3040, next =3D 3040, want =3D 0 orig =3D 3040, next =3D 3040, want =3D 0 =3D=3D=3D=3D Test Assertion Failure =3D=3D=3D=3D aarch64/vpmu_counter_access.c:505: pmcr_n =3D=3D get_pmcr_n(pmcr) pid=3D71578 tid=3D71578 errno=3D9 - Bad file descriptor 1 0x400673: run_access_test at vpmu_counter_access.c:522 2 (inlined by) main at vpmu_counter_access.c:643 3 0x4132d7: __libc_start_call_main at libc-start.o:0 4 0x413653: __libc_start_main at ??:0 5 0x40106f: _start at ??:0 Failed to update PMCR.N to 0 (received: 6) Somewhat bizarrely, gcc-11 also exhibits the same behavior, but only if set_pmcr_n() is marked noinline, whereas gcc-13 fails even if set_pmcr_n() is inlined in its sole caller. Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D116912 Signed-off-by: Sean Christopherson --- tools/testing/selftests/kvm/Makefile | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests= /kvm/Makefile index 960cf6a77198..6246d69d82d7 100644 --- a/tools/testing/selftests/kvm/Makefile +++ b/tools/testing/selftests/kvm/Makefile @@ -241,10 +241,10 @@ CFLAGS +=3D -Wall -Wstrict-prototypes -Wuninitialized= -O2 -g -std=3Dgnu99 \ -Wno-gnu-variable-sized-type-not-at-end -MD -MP -DCONFIG_64BIT \ -fno-builtin-memcmp -fno-builtin-memcpy \ -fno-builtin-memset -fno-builtin-strnlen \ - -fno-stack-protector -fno-PIE -I$(LINUX_TOOL_INCLUDE) \ - -I$(LINUX_TOOL_ARCH_INCLUDE) -I$(LINUX_HDR_PATH) -Iinclude \ - -I$(; Wed, 9 Oct 2024 15:50:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728489004; 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Wed, 09 Oct 2024 08:50:01 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 9 Oct 2024 08:49:42 -0700 In-Reply-To: <20241009154953.1073471-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241009154953.1073471-1-seanjc@google.com> X-Mailer: git-send-email 2.47.0.rc0.187.ge670bccf7e-goog Message-ID: <20241009154953.1073471-4-seanjc@google.com> Subject: [PATCH v3 03/14] KVM: selftests: Return a value from vcpu_get_reg() instead of using an out-param From: Sean Christopherson To: Marc Zyngier , Oliver Upton , Anup Patel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Paolo Bonzini , Christian Borntraeger , Janosch Frank , Claudio Imbrenda Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Sean Christopherson , Andrew Jones , James Houghton Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Return a uint64_t from vcpu_get_reg() instead of having the caller provide a pointer to storage, as none of the vcpu_get_reg() usage in KVM selftests accesses a register larger than 64 bits, and vcpu_set_reg() only accepts a 64-bit value. If a use case comes along that needs to get a register that is larger than 64 bits, then a utility can be added to assert success and take a void pointer, but until then, forcing an out param yields ugly code and prevents feeding the output of vcpu_get_reg() into vcpu_set_reg(). Reviewed-by: Andrew Jones Signed-off-by: Sean Christopherson --- .../selftests/kvm/aarch64/aarch32_id_regs.c | 10 +-- .../selftests/kvm/aarch64/debug-exceptions.c | 4 +- .../selftests/kvm/aarch64/hypercalls.c | 6 +- .../selftests/kvm/aarch64/no-vgic-v3.c | 2 +- .../testing/selftests/kvm/aarch64/psci_test.c | 6 +- .../selftests/kvm/aarch64/set_id_regs.c | 18 ++--- .../kvm/aarch64/vpmu_counter_access.c | 19 +++--- .../testing/selftests/kvm/include/kvm_util.h | 6 +- .../selftests/kvm/lib/aarch64/processor.c | 8 +-- .../selftests/kvm/lib/riscv/processor.c | 66 +++++++++---------- .../testing/selftests/kvm/riscv/arch_timer.c | 2 +- .../testing/selftests/kvm/riscv/ebreak_test.c | 2 +- .../selftests/kvm/riscv/sbi_pmu_test.c | 2 +- tools/testing/selftests/kvm/s390x/resets.c | 2 +- tools/testing/selftests/kvm/steal_time.c | 3 +- 15 files changed, 78 insertions(+), 78 deletions(-) diff --git a/tools/testing/selftests/kvm/aarch64/aarch32_id_regs.c b/tools/= testing/selftests/kvm/aarch64/aarch32_id_regs.c index 8e5bd07a3727..447d61cae4db 100644 --- a/tools/testing/selftests/kvm/aarch64/aarch32_id_regs.c +++ b/tools/testing/selftests/kvm/aarch64/aarch32_id_regs.c @@ -97,7 +97,7 @@ static void test_user_raz_wi(struct kvm_vcpu *vcpu) uint64_t reg_id =3D raz_wi_reg_ids[i]; uint64_t val; =20 - vcpu_get_reg(vcpu, reg_id, &val); + val =3D vcpu_get_reg(vcpu, reg_id); TEST_ASSERT_EQ(val, 0); =20 /* @@ -106,7 +106,7 @@ static void test_user_raz_wi(struct kvm_vcpu *vcpu) */ vcpu_set_reg(vcpu, reg_id, BAD_ID_REG_VAL); =20 - vcpu_get_reg(vcpu, reg_id, &val); + val =3D vcpu_get_reg(vcpu, reg_id); TEST_ASSERT_EQ(val, 0); } } @@ -126,14 +126,14 @@ static void test_user_raz_invariant(struct kvm_vcpu *= vcpu) uint64_t reg_id =3D raz_invariant_reg_ids[i]; uint64_t val; =20 - vcpu_get_reg(vcpu, reg_id, &val); + val =3D vcpu_get_reg(vcpu, reg_id); TEST_ASSERT_EQ(val, 0); =20 r =3D __vcpu_set_reg(vcpu, reg_id, BAD_ID_REG_VAL); TEST_ASSERT(r < 0 && errno =3D=3D EINVAL, "unexpected KVM_SET_ONE_REG error: r=3D%d, errno=3D%d", r, errno); =20 - vcpu_get_reg(vcpu, reg_id, &val); + val =3D vcpu_get_reg(vcpu, reg_id); TEST_ASSERT_EQ(val, 0); } } @@ -144,7 +144,7 @@ static bool vcpu_aarch64_only(struct kvm_vcpu *vcpu) { uint64_t val, el0; =20 - vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), &val); + val =3D vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1)); =20 el0 =3D FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), val); return el0 =3D=3D ID_AA64PFR0_EL1_ELx_64BIT_ONLY; diff --git a/tools/testing/selftests/kvm/aarch64/debug-exceptions.c b/tools= /testing/selftests/kvm/aarch64/debug-exceptions.c index 2582c49e525a..b3f3025d2f02 100644 --- a/tools/testing/selftests/kvm/aarch64/debug-exceptions.c +++ b/tools/testing/selftests/kvm/aarch64/debug-exceptions.c @@ -501,7 +501,7 @@ void test_single_step_from_userspace(int test_cnt) TEST_ASSERT(ss_enable, "Unexpected KVM_EXIT_DEBUG"); =20 /* Check if the current pc is expected. */ - vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc), &pc); + pc =3D vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc)); TEST_ASSERT(!test_pc || pc =3D=3D test_pc, "Unexpected pc 0x%lx (expected 0x%lx)", pc, test_pc); @@ -583,7 +583,7 @@ int main(int argc, char *argv[]) uint64_t aa64dfr0; =20 vm =3D vm_create_with_one_vcpu(&vcpu, guest_code); - vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1), &aa64dfr0); + aa64dfr0 =3D vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1)); __TEST_REQUIRE(debug_version(aa64dfr0) >=3D 6, "Armv8 debug architecture not supported."); kvm_vm_free(vm); diff --git a/tools/testing/selftests/kvm/aarch64/hypercalls.c b/tools/testi= ng/selftests/kvm/aarch64/hypercalls.c index 9d192ce0078d..ec54ec7726e9 100644 --- a/tools/testing/selftests/kvm/aarch64/hypercalls.c +++ b/tools/testing/selftests/kvm/aarch64/hypercalls.c @@ -173,7 +173,7 @@ static void test_fw_regs_before_vm_start(struct kvm_vcp= u *vcpu) const struct kvm_fw_reg_info *reg_info =3D &fw_reg_info[i]; =20 /* First 'read' should be an upper limit of the features supported */ - vcpu_get_reg(vcpu, reg_info->reg, &val); + val =3D vcpu_get_reg(vcpu, reg_info->reg); TEST_ASSERT(val =3D=3D FW_REG_ULIMIT_VAL(reg_info->max_feat_bit), "Expected all the features to be set for reg: 0x%lx; expected: 0x%lx; r= ead: 0x%lx", reg_info->reg, FW_REG_ULIMIT_VAL(reg_info->max_feat_bit), val); @@ -184,7 +184,7 @@ static void test_fw_regs_before_vm_start(struct kvm_vcp= u *vcpu) "Failed to clear all the features of reg: 0x%lx; ret: %d", reg_info->reg, errno); =20 - vcpu_get_reg(vcpu, reg_info->reg, &val); + val =3D vcpu_get_reg(vcpu, reg_info->reg); TEST_ASSERT(val =3D=3D 0, "Expected all the features to be cleared for reg: 0x%lx", reg_info->reg= ); =20 @@ -214,7 +214,7 @@ static void test_fw_regs_after_vm_start(struct kvm_vcpu= *vcpu) * Before starting the VM, the test clears all the bits. * Check if that's still the case. */ - vcpu_get_reg(vcpu, reg_info->reg, &val); + val =3D vcpu_get_reg(vcpu, reg_info->reg); TEST_ASSERT(val =3D=3D 0, "Expected all the features to be cleared for reg: 0x%lx", reg_info->reg); diff --git a/tools/testing/selftests/kvm/aarch64/no-vgic-v3.c b/tools/testi= ng/selftests/kvm/aarch64/no-vgic-v3.c index 943d65fc6b0b..f80a519f73bb 100644 --- a/tools/testing/selftests/kvm/aarch64/no-vgic-v3.c +++ b/tools/testing/selftests/kvm/aarch64/no-vgic-v3.c @@ -164,7 +164,7 @@ int main(int argc, char *argv[]) uint64_t pfr0; =20 vm =3D vm_create_with_one_vcpu(&vcpu, NULL); - vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), &pfr0); + pfr0 =3D vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1)); __TEST_REQUIRE(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC), pfr0), "GICv3 not supported."); kvm_vm_free(vm); diff --git a/tools/testing/selftests/kvm/aarch64/psci_test.c b/tools/testin= g/selftests/kvm/aarch64/psci_test.c index 61731a950def..544ebd2b121b 100644 --- a/tools/testing/selftests/kvm/aarch64/psci_test.c +++ b/tools/testing/selftests/kvm/aarch64/psci_test.c @@ -102,8 +102,8 @@ static void assert_vcpu_reset(struct kvm_vcpu *vcpu) { uint64_t obs_pc, obs_x0; =20 - vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc), &obs_pc); - vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.regs[0]), &obs_x0); + obs_pc =3D vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc)); + obs_x0 =3D vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.regs[0])); =20 TEST_ASSERT(obs_pc =3D=3D CPU_ON_ENTRY_ADDR, "unexpected target cpu pc: %lx (expected: %lx)", @@ -143,7 +143,7 @@ static void host_test_cpu_on(void) */ vcpu_power_off(target); =20 - vcpu_get_reg(target, KVM_ARM64_SYS_REG(SYS_MPIDR_EL1), &target_mpidr); + target_mpidr =3D vcpu_get_reg(target, KVM_ARM64_SYS_REG(SYS_MPIDR_EL1)); vcpu_args_set(source, 1, target_mpidr & MPIDR_HWID_BITMASK); enter_guest(source); =20 diff --git a/tools/testing/selftests/kvm/aarch64/set_id_regs.c b/tools/test= ing/selftests/kvm/aarch64/set_id_regs.c index 2a3fe7914b72..8a1d92048aef 100644 --- a/tools/testing/selftests/kvm/aarch64/set_id_regs.c +++ b/tools/testing/selftests/kvm/aarch64/set_id_regs.c @@ -336,7 +336,7 @@ static uint64_t test_reg_set_success(struct kvm_vcpu *v= cpu, uint64_t reg, uint64_t mask =3D ftr_bits->mask; uint64_t val, new_val, ftr; =20 - vcpu_get_reg(vcpu, reg, &val); + val =3D vcpu_get_reg(vcpu, reg); ftr =3D (val & mask) >> shift; =20 ftr =3D get_safe_value(ftr_bits, ftr); @@ -346,7 +346,7 @@ static uint64_t test_reg_set_success(struct kvm_vcpu *v= cpu, uint64_t reg, val |=3D ftr; =20 vcpu_set_reg(vcpu, reg, val); - vcpu_get_reg(vcpu, reg, &new_val); + new_val =3D vcpu_get_reg(vcpu, reg); TEST_ASSERT_EQ(new_val, val); =20 return new_val; @@ -360,7 +360,7 @@ static void test_reg_set_fail(struct kvm_vcpu *vcpu, ui= nt64_t reg, uint64_t val, old_val, ftr; int r; =20 - vcpu_get_reg(vcpu, reg, &val); + val =3D vcpu_get_reg(vcpu, reg); ftr =3D (val & mask) >> shift; =20 ftr =3D get_invalid_value(ftr_bits, ftr); @@ -374,7 +374,7 @@ static void test_reg_set_fail(struct kvm_vcpu *vcpu, ui= nt64_t reg, TEST_ASSERT(r < 0 && errno =3D=3D EINVAL, "Unexpected KVM_SET_ONE_REG error: r=3D%d, errno=3D%d", r, errno); =20 - vcpu_get_reg(vcpu, reg, &val); + val =3D vcpu_get_reg(vcpu, reg); TEST_ASSERT_EQ(val, old_val); } =20 @@ -471,7 +471,7 @@ static void test_clidr(struct kvm_vcpu *vcpu) uint64_t clidr; int level; =20 - vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CLIDR_EL1), &clidr); + clidr =3D vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CLIDR_EL1)); =20 /* find the first empty level in the cache hierarchy */ for (level =3D 1; level < 7; level++) { @@ -496,7 +496,7 @@ static void test_ctr(struct kvm_vcpu *vcpu) { u64 ctr; =20 - vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CTR_EL0), &ctr); + ctr =3D vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CTR_EL0)); ctr &=3D ~CTR_EL0_DIC_MASK; if (ctr & CTR_EL0_IminLine_MASK) ctr--; @@ -512,7 +512,7 @@ static void test_vcpu_ftr_id_regs(struct kvm_vcpu *vcpu) test_clidr(vcpu); test_ctr(vcpu); =20 - vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_MPIDR_EL1), &val); + val =3D vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_MPIDR_EL1)); val++; vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_MPIDR_EL1), val); =20 @@ -525,7 +525,7 @@ static void test_assert_id_reg_unchanged(struct kvm_vcp= u *vcpu, uint32_t encodin size_t idx =3D encoding_to_range_idx(encoding); uint64_t observed; =20 - vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(encoding), &observed); + observed =3D vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(encoding)); TEST_ASSERT_EQ(test_reg_vals[idx], observed); } =20 @@ -560,7 +560,7 @@ int main(void) vm =3D vm_create_with_one_vcpu(&vcpu, guest_code); =20 /* Check for AARCH64 only system */ - vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), &val); + val =3D vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1)); el0 =3D FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), val); aarch64_only =3D (el0 =3D=3D ID_AA64PFR0_EL1_ELx_64BIT_ONLY); =20 diff --git a/tools/testing/selftests/kvm/aarch64/vpmu_counter_access.c b/to= ols/testing/selftests/kvm/aarch64/vpmu_counter_access.c index d31b9f64ba14..30d9c9e7ae35 100644 --- a/tools/testing/selftests/kvm/aarch64/vpmu_counter_access.c +++ b/tools/testing/selftests/kvm/aarch64/vpmu_counter_access.c @@ -440,8 +440,7 @@ static void create_vpmu_vm(void *guest_code) "Failed to create vgic-v3, skipping"); =20 /* Make sure that PMUv3 support is indicated in the ID register */ - vcpu_get_reg(vpmu_vm.vcpu, - KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1), &dfr0); + dfr0 =3D vcpu_get_reg(vpmu_vm.vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1= )); pmuver =3D FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), dfr0); TEST_ASSERT(pmuver !=3D ID_AA64DFR0_EL1_PMUVer_IMP_DEF && pmuver >=3D ID_AA64DFR0_EL1_PMUVer_IMP, @@ -484,7 +483,7 @@ static void test_create_vpmu_vm_with_pmcr_n(uint64_t pm= cr_n, bool expect_fail) create_vpmu_vm(guest_code); vcpu =3D vpmu_vm.vcpu; =20 - vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_PMCR_EL0), &pmcr_orig); + pmcr_orig =3D vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_PMCR_EL0)); pmcr =3D pmcr_orig; =20 /* @@ -493,7 +492,7 @@ static void test_create_vpmu_vm_with_pmcr_n(uint64_t pm= cr_n, bool expect_fail) */ set_pmcr_n(&pmcr, pmcr_n); vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_PMCR_EL0), pmcr); - vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_PMCR_EL0), &pmcr); + pmcr =3D vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_PMCR_EL0)); =20 if (expect_fail) TEST_ASSERT(pmcr_orig =3D=3D pmcr, @@ -521,7 +520,7 @@ static void run_access_test(uint64_t pmcr_n) vcpu =3D vpmu_vm.vcpu; =20 /* Save the initial sp to restore them later to run the guest again */ - vcpu_get_reg(vcpu, ARM64_CORE_REG(sp_el1), &sp); + sp =3D vcpu_get_reg(vcpu, ARM64_CORE_REG(sp_el1)); =20 run_vcpu(vcpu, pmcr_n); =20 @@ -572,12 +571,12 @@ static void run_pmregs_validity_test(uint64_t pmcr_n) * Test if the 'set' and 'clr' variants of the registers * are initialized based on the number of valid counters. */ - vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(set_reg_id), ®_val); + reg_val =3D vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(set_reg_id)); TEST_ASSERT((reg_val & (~valid_counters_mask)) =3D=3D 0, "Initial read of set_reg: 0x%llx has unimplemented counters enabled= : 0x%lx", KVM_ARM64_SYS_REG(set_reg_id), reg_val); =20 - vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(clr_reg_id), ®_val); + reg_val =3D vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(clr_reg_id)); TEST_ASSERT((reg_val & (~valid_counters_mask)) =3D=3D 0, "Initial read of clr_reg: 0x%llx has unimplemented counters enabled= : 0x%lx", KVM_ARM64_SYS_REG(clr_reg_id), reg_val); @@ -589,12 +588,12 @@ static void run_pmregs_validity_test(uint64_t pmcr_n) */ vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(set_reg_id), max_counters_mask); =20 - vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(set_reg_id), ®_val); + reg_val =3D vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(set_reg_id)); TEST_ASSERT((reg_val & (~valid_counters_mask)) =3D=3D 0, "Read of set_reg: 0x%llx has unimplemented counters enabled: 0x%lx", KVM_ARM64_SYS_REG(set_reg_id), reg_val); =20 - vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(clr_reg_id), ®_val); + reg_val =3D vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(clr_reg_id)); TEST_ASSERT((reg_val & (~valid_counters_mask)) =3D=3D 0, "Read of clr_reg: 0x%llx has unimplemented counters enabled: 0x%lx", KVM_ARM64_SYS_REG(clr_reg_id), reg_val); @@ -625,7 +624,7 @@ static uint64_t get_pmcr_n_limit(void) uint64_t pmcr; =20 create_vpmu_vm(guest_code); - vcpu_get_reg(vpmu_vm.vcpu, KVM_ARM64_SYS_REG(SYS_PMCR_EL0), &pmcr); + pmcr =3D vcpu_get_reg(vpmu_vm.vcpu, KVM_ARM64_SYS_REG(SYS_PMCR_EL0)); destroy_vpmu_vm(); return get_pmcr_n(pmcr); } diff --git a/tools/testing/selftests/kvm/include/kvm_util.h b/tools/testing= /selftests/kvm/include/kvm_util.h index bc7c242480d6..287a3ec06df4 100644 --- a/tools/testing/selftests/kvm/include/kvm_util.h +++ b/tools/testing/selftests/kvm/include/kvm_util.h @@ -702,11 +702,13 @@ static inline int __vcpu_set_reg(struct kvm_vcpu *vcp= u, uint64_t id, uint64_t va =20 return __vcpu_ioctl(vcpu, KVM_SET_ONE_REG, ®); } -static inline void vcpu_get_reg(struct kvm_vcpu *vcpu, uint64_t id, void *= addr) +static inline uint64_t vcpu_get_reg(struct kvm_vcpu *vcpu, uint64_t id) { - struct kvm_one_reg reg =3D { .id =3D id, .addr =3D (uint64_t)addr }; + uint64_t val; + struct kvm_one_reg reg =3D { .id =3D id, .addr =3D (uint64_t)&val }; =20 vcpu_ioctl(vcpu, KVM_GET_ONE_REG, ®); + return val; } static inline void vcpu_set_reg(struct kvm_vcpu *vcpu, uint64_t id, uint64= _t val) { diff --git a/tools/testing/selftests/kvm/lib/aarch64/processor.c b/tools/te= sting/selftests/kvm/lib/aarch64/processor.c index fe4dc3693112..4af94272a758 100644 --- a/tools/testing/selftests/kvm/lib/aarch64/processor.c +++ b/tools/testing/selftests/kvm/lib/aarch64/processor.c @@ -281,8 +281,8 @@ void aarch64_vcpu_setup(struct kvm_vcpu *vcpu, struct k= vm_vcpu_init *init) */ vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CPACR_EL1), 3 << 20); =20 - vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_SCTLR_EL1), &sctlr_el1); - vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_TCR_EL1), &tcr_el1); + sctlr_el1 =3D vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_SCTLR_EL1)); + tcr_el1 =3D vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_TCR_EL1)); =20 /* Configure base granule size */ switch (vm->mode) { @@ -360,8 +360,8 @@ void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu= , uint8_t indent) { uint64_t pstate, pc; =20 - vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pstate), &pstate); - vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc), &pc); + pstate =3D vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pstate)); + pc =3D vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc)); =20 fprintf(stream, "%*spstate: 0x%.16lx pc: 0x%.16lx\n", indent, "", pstate, pc); diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/test= ing/selftests/kvm/lib/riscv/processor.c index 6ae47b3d6b25..dd663bcf0cc0 100644 --- a/tools/testing/selftests/kvm/lib/riscv/processor.c +++ b/tools/testing/selftests/kvm/lib/riscv/processor.c @@ -221,39 +221,39 @@ void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vc= pu, uint8_t indent) { struct kvm_riscv_core core; =20 - vcpu_get_reg(vcpu, RISCV_CORE_REG(mode), &core.mode); - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.pc), &core.regs.pc); - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.ra), &core.regs.ra); - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.sp), &core.regs.sp); - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.gp), &core.regs.gp); - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.tp), &core.regs.tp); - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t0), &core.regs.t0); - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t1), &core.regs.t1); - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t2), &core.regs.t2); - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s0), &core.regs.s0); - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s1), &core.regs.s1); - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a0), &core.regs.a0); - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a1), &core.regs.a1); - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a2), &core.regs.a2); - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a3), &core.regs.a3); - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a4), &core.regs.a4); - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a5), &core.regs.a5); - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a6), &core.regs.a6); - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a7), &core.regs.a7); - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s2), &core.regs.s2); - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s3), &core.regs.s3); - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s4), &core.regs.s4); - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s5), &core.regs.s5); - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s6), &core.regs.s6); - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s7), &core.regs.s7); - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s8), &core.regs.s8); - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s9), &core.regs.s9); - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s10), &core.regs.s10); - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s11), &core.regs.s11); - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t3), &core.regs.t3); - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t4), &core.regs.t4); - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t5), &core.regs.t5); - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t6), &core.regs.t6); + core.mode =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(mode)); + core.regs.pc =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.pc)); + core.regs.ra =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.ra)); + core.regs.sp =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.sp)); + core.regs.gp =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.gp)); + core.regs.tp =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.tp)); + core.regs.t0 =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t0)); + core.regs.t1 =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t1)); + core.regs.t2 =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t2)); + core.regs.s0 =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s0)); + core.regs.s1 =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s1)); + core.regs.a0 =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a0)); + core.regs.a1 =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a1)); + core.regs.a2 =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a2)); + core.regs.a3 =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a3)); + core.regs.a4 =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a4)); + core.regs.a5 =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a5)); + core.regs.a6 =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a6)); + core.regs.a7 =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a7)); + core.regs.s2 =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s2)); + core.regs.s3 =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s3)); + core.regs.s4 =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s4)); + core.regs.s5 =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s5)); + core.regs.s6 =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s6)); + core.regs.s7 =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s7)); + core.regs.s8 =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s8)); + core.regs.s9 =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s9)); + core.regs.s10 =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s10)); + core.regs.s11 =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s11)); + core.regs.t3 =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t3)); + core.regs.t4 =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t4)); + core.regs.t5 =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t5)); + core.regs.t6 =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t6)); =20 fprintf(stream, " MODE: 0x%lx\n", core.mode); diff --git a/tools/testing/selftests/kvm/riscv/arch_timer.c b/tools/testing= /selftests/kvm/riscv/arch_timer.c index 2c792228ac0b..9e370800a6a2 100644 --- a/tools/testing/selftests/kvm/riscv/arch_timer.c +++ b/tools/testing/selftests/kvm/riscv/arch_timer.c @@ -93,7 +93,7 @@ struct kvm_vm *test_vm_create(void) vcpu_init_vector_tables(vcpus[i]); =20 /* Initialize guest timer frequency. */ - vcpu_get_reg(vcpus[0], RISCV_TIMER_REG(frequency), &timer_freq); + timer_freq =3D vcpu_get_reg(vcpus[0], RISCV_TIMER_REG(frequency)); sync_global_to_guest(vm, timer_freq); pr_debug("timer_freq: %lu\n", timer_freq); =20 diff --git a/tools/testing/selftests/kvm/riscv/ebreak_test.c b/tools/testin= g/selftests/kvm/riscv/ebreak_test.c index 0e0712854953..cfed6c727bfc 100644 --- a/tools/testing/selftests/kvm/riscv/ebreak_test.c +++ b/tools/testing/selftests/kvm/riscv/ebreak_test.c @@ -60,7 +60,7 @@ int main(void) =20 TEST_ASSERT_KVM_EXIT_REASON(vcpu, KVM_EXIT_DEBUG); =20 - vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.pc), &pc); + pc =3D vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.pc)); TEST_ASSERT_EQ(pc, LABEL_ADDRESS(sw_bp_1)); =20 /* skip sw_bp_1 */ diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c b/tools/testi= ng/selftests/kvm/riscv/sbi_pmu_test.c index f299cbfd23ca..f45c0ecc902d 100644 --- a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c +++ b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c @@ -608,7 +608,7 @@ static void test_vm_events_overflow(void *guest_code) =20 vcpu_init_vector_tables(vcpu); /* Initialize guest timer frequency. */ - vcpu_get_reg(vcpu, RISCV_TIMER_REG(frequency), &timer_freq); + timer_freq =3D vcpu_get_reg(vcpu, RISCV_TIMER_REG(frequency)); sync_global_to_guest(vm, timer_freq); =20 run_vcpu(vcpu); diff --git a/tools/testing/selftests/kvm/s390x/resets.c b/tools/testing/sel= ftests/kvm/s390x/resets.c index 357943f2bea8..b58f75b381e5 100644 --- a/tools/testing/selftests/kvm/s390x/resets.c +++ b/tools/testing/selftests/kvm/s390x/resets.c @@ -61,7 +61,7 @@ static void test_one_reg(struct kvm_vcpu *vcpu, uint64_t = id, uint64_t value) { uint64_t eval_reg; =20 - vcpu_get_reg(vcpu, id, &eval_reg); + eval_reg =3D vcpu_get_reg(vcpu, id); TEST_ASSERT(eval_reg =3D=3D value, "value =3D=3D 0x%lx", value); } =20 diff --git a/tools/testing/selftests/kvm/steal_time.c b/tools/testing/selft= ests/kvm/steal_time.c index a8d3afa0b86b..cce2520af720 100644 --- a/tools/testing/selftests/kvm/steal_time.c +++ b/tools/testing/selftests/kvm/steal_time.c @@ -269,9 +269,8 @@ static void guest_code(int cpu) static bool is_steal_time_supported(struct kvm_vcpu *vcpu) { uint64_t id =3D RISCV_SBI_EXT_REG(KVM_RISCV_SBI_EXT_STA); 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charset="utf-8" Assert that the register being read/written by vcpu_{g,s}et_reg() is no larger than a uint64_t, i.e. that a selftest isn't unintentionally truncating the value being read/written. Ideally, the assert would be done at compile-time, but that would limit the checks to hardcoded accesses and/or require fancier compile-time assertion infrastructure to filter out dynamic usage. Reviewed-by: Andrew Jones Signed-off-by: Sean Christopherson --- tools/testing/selftests/kvm/include/kvm_util.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tools/testing/selftests/kvm/include/kvm_util.h b/tools/testing= /selftests/kvm/include/kvm_util.h index 287a3ec06df4..4c4e5a847f67 100644 --- a/tools/testing/selftests/kvm/include/kvm_util.h +++ b/tools/testing/selftests/kvm/include/kvm_util.h @@ -707,6 +707,8 @@ static inline uint64_t vcpu_get_reg(struct kvm_vcpu *vc= pu, uint64_t id) uint64_t val; struct kvm_one_reg reg =3D { .id =3D id, .addr =3D (uint64_t)&val }; =20 + TEST_ASSERT(KVM_REG_SIZE(id) <=3D sizeof(val), "Reg %lx too big", id); + vcpu_ioctl(vcpu, KVM_GET_ONE_REG, ®); return val; } @@ -714,6 +716,8 @@ static inline void vcpu_set_reg(struct kvm_vcpu *vcpu, = uint64_t id, uint64_t val { struct kvm_one_reg reg =3D { .id =3D id, .addr =3D (uint64_t)&val }; =20 + TEST_ASSERT(KVM_REG_SIZE(id) <=3D sizeof(val), "Reg %lx too big", id); + vcpu_ioctl(vcpu, KVM_SET_ONE_REG, ®); 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AJvYcCXE/8Kw9549eX5PTOFiPkbZEbhB/HTU/khCBWRaWfTm2OMg68fy8aaGNnBXPlfn0I90s9N6ioMYtHAhYE4=@vger.kernel.org X-Gm-Message-State: AOJu0YyljHrwH6rryvFZGF6s4d/FWrON/+TAyk43AXkFRFmYMpXYhO46 cpWjq7yGp7hTXUHrQPOykeIpCMoFlB8zns7G1c8c3KQOr8UbmYFbJvZkzAMc33nVXqlb8/GCxZz dXQ== X-Google-Smtp-Source: AGHT+IFrWalNmEyn72/5CXUVKhi80GHo8XaYDR+iQ/XjxOT9S8VfevqUwXplC0nvvzPPLclQ9b5vmaVf6gI= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:9d:3983:ac13:c240]) (user=seanjc job=sendgmr) by 2002:a0d:cd84:0:b0:6e3:b08:92cb with SMTP id 00721157ae682-6e321d4062cmr303877b3.0.1728489005619; Wed, 09 Oct 2024 08:50:05 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 9 Oct 2024 08:49:44 -0700 In-Reply-To: <20241009154953.1073471-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241009154953.1073471-1-seanjc@google.com> X-Mailer: git-send-email 2.47.0.rc0.187.ge670bccf7e-goog Message-ID: <20241009154953.1073471-6-seanjc@google.com> Subject: [PATCH v3 05/14] KVM: selftests: Check for a potential unhandled exception iff KVM_RUN succeeded From: Sean Christopherson To: Marc Zyngier , Oliver Upton , Anup Patel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Paolo Bonzini , Christian Borntraeger , Janosch Frank , Claudio Imbrenda Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Sean Christopherson , Andrew Jones , James Houghton Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Don't check for an unhandled exception if KVM_RUN failed, e.g. if it returned errno=3DEFAULT, as reporting unhandled exceptions is done via a ucall, i.e. requires KVM_RUN to exit cleanly. Theoretically, checking for a ucall on a failed KVM_RUN could get a false positive, e.g. if there were stale data in vcpu->run from a previous exit. Reviewed-by: James Houghton Signed-off-by: Sean Christopherson --- tools/testing/selftests/kvm/lib/kvm_util.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/kvm/lib/kvm_util.c b/tools/testing/sel= ftests/kvm/lib/kvm_util.c index a2b7df5f1d39..6b3161a0990f 100644 --- a/tools/testing/selftests/kvm/lib/kvm_util.c +++ b/tools/testing/selftests/kvm/lib/kvm_util.c @@ -1646,7 +1646,8 @@ int _vcpu_run(struct kvm_vcpu *vcpu) rc =3D __vcpu_run(vcpu); } while (rc =3D=3D -1 && errno =3D=3D EINTR); =20 - assert_on_unhandled_exception(vcpu); + if (!rc) + assert_on_unhandled_exception(vcpu); =20 return rc; } --=20 2.47.0.rc0.187.ge670bccf7e-goog From nobody Wed Nov 27 14:26:49 2024 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B419F202F6E for ; Wed, 9 Oct 2024 15:50:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 09 Oct 2024 08:50:07 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 9 Oct 2024 08:49:45 -0700 In-Reply-To: <20241009154953.1073471-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241009154953.1073471-1-seanjc@google.com> X-Mailer: git-send-email 2.47.0.rc0.187.ge670bccf7e-goog Message-ID: <20241009154953.1073471-7-seanjc@google.com> Subject: [PATCH v3 06/14] KVM: selftests: Rename max_guest_memory_test to mmu_stress_test From: Sean Christopherson To: Marc Zyngier , Oliver Upton , Anup Patel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Paolo Bonzini , Christian Borntraeger , Janosch Frank , Claudio Imbrenda Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Sean Christopherson , Andrew Jones , James Houghton Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rename max_guest_memory_test to mmu_stress_test so that the name isn't horribly misleading when future changes extend the test to verify things like mprotect() interactions, and because the test is useful even when its configured to populate far less than the maximum amount of guest memory. Reviewed-by: James Houghton Signed-off-by: Sean Christopherson --- tools/testing/selftests/kvm/Makefile | 2 +- .../kvm/{max_guest_memory_test.c =3D> mmu_stress_test.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename tools/testing/selftests/kvm/{max_guest_memory_test.c =3D> mmu_stres= s_test.c} (100%) diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests= /kvm/Makefile index 6246d69d82d7..8c69a14dc93d 100644 --- a/tools/testing/selftests/kvm/Makefile +++ b/tools/testing/selftests/kvm/Makefile @@ -139,7 +139,7 @@ TEST_GEN_PROGS_x86_64 +=3D guest_print_test TEST_GEN_PROGS_x86_64 +=3D hardware_disable_test TEST_GEN_PROGS_x86_64 +=3D kvm_create_max_vcpus TEST_GEN_PROGS_x86_64 +=3D kvm_page_table_test -TEST_GEN_PROGS_x86_64 +=3D max_guest_memory_test +TEST_GEN_PROGS_x86_64 +=3D mmu_stress_test TEST_GEN_PROGS_x86_64 +=3D memslot_modification_stress_test TEST_GEN_PROGS_x86_64 +=3D memslot_perf_test TEST_GEN_PROGS_x86_64 +=3D rseq_test diff --git a/tools/testing/selftests/kvm/max_guest_memory_test.c b/tools/te= sting/selftests/kvm/mmu_stress_test.c similarity index 100% rename from tools/testing/selftests/kvm/max_guest_memory_test.c rename to tools/testing/selftests/kvm/mmu_stress_test.c --=20 2.47.0.rc0.187.ge670bccf7e-goog From nobody Wed Nov 27 14:26:49 2024 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C3EE202F8E for ; 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Wed, 09 Oct 2024 08:50:09 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 9 Oct 2024 08:49:46 -0700 In-Reply-To: <20241009154953.1073471-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241009154953.1073471-1-seanjc@google.com> X-Mailer: git-send-email 2.47.0.rc0.187.ge670bccf7e-goog Message-ID: <20241009154953.1073471-8-seanjc@google.com> Subject: [PATCH v3 07/14] KVM: selftests: Only muck with SREGS on x86 in mmu_stress_test From: Sean Christopherson To: Marc Zyngier , Oliver Upton , Anup Patel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Paolo Bonzini , Christian Borntraeger , Janosch Frank , Claudio Imbrenda Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Sean Christopherson , Andrew Jones , James Houghton Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Try to get/set SREGS in mmu_stress_test only when running on x86, as the ioctls are supported only by x86 and PPC, and the latter doesn't yet support KVM selftests. Reviewed-by: James Houghton Signed-off-by: Sean Christopherson --- tools/testing/selftests/kvm/mmu_stress_test.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/testing/selftests/kvm/mmu_stress_test.c b/tools/testing/= selftests/kvm/mmu_stress_test.c index 0b9678858b6d..847da23ec1b1 100644 --- a/tools/testing/selftests/kvm/mmu_stress_test.c +++ b/tools/testing/selftests/kvm/mmu_stress_test.c @@ -59,10 +59,10 @@ static void run_vcpu(struct kvm_vcpu *vcpu) =20 static void *vcpu_worker(void *data) { + struct kvm_sregs __maybe_unused sregs; struct vcpu_info *info =3D data; struct kvm_vcpu *vcpu =3D info->vcpu; struct kvm_vm *vm =3D vcpu->vm; - struct kvm_sregs sregs; =20 vcpu_args_set(vcpu, 3, info->start_gpa, info->end_gpa, vm->page_size); =20 @@ -70,12 +70,12 @@ static void *vcpu_worker(void *data) =20 run_vcpu(vcpu); rendezvous_with_boss(); +#ifdef __x86_64__ vcpu_sregs_get(vcpu, &sregs); -#ifdef __x86_64__ /* Toggle CR0.WP to trigger a MMU context reset. */ sregs.cr0 ^=3D X86_CR0_WP; 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AJvYcCWhM5i0K18nOcP0iSddgyTw7U7zIW9PmBQx9flvp2U7sqOdFHWj/HhP8ECLASiMegHiVocY2loEA42jAr0=@vger.kernel.org X-Gm-Message-State: AOJu0Yx7o0zE52rsZjUU2SMaGkk3Fikn2McbMVyYn9PSmaRJVHtwnd6Y SLB204YjtoZot6wYdSfW43za6r+V1nKLbX3BSpm7cpSWOWiz5Kqy/NAwkc8if820Ax/K3TwNDyE pmA== X-Google-Smtp-Source: AGHT+IHLwQuTuSKn2K83jzMORxhmnJG2QJIDSetKispH+vrqgQjqJfiOQ3+gOO6ZQgZWYqSyd9aEi5B6J6c= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:9d:3983:ac13:c240]) (user=seanjc job=sendgmr) by 2002:a25:6948:0:b0:e29:6a6:ed83 with SMTP id 3f1490d57ef6-e2906a6f043mr903276.11.1728489011277; Wed, 09 Oct 2024 08:50:11 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 9 Oct 2024 08:49:47 -0700 In-Reply-To: <20241009154953.1073471-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241009154953.1073471-1-seanjc@google.com> X-Mailer: git-send-email 2.47.0.rc0.187.ge670bccf7e-goog Message-ID: <20241009154953.1073471-9-seanjc@google.com> Subject: [PATCH v3 08/14] KVM: selftests: Compute number of extra pages needed in mmu_stress_test From: Sean Christopherson To: Marc Zyngier , Oliver Upton , Anup Patel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Paolo Bonzini , Christian Borntraeger , Janosch Frank , Claudio Imbrenda Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Sean Christopherson , Andrew Jones , James Houghton Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Create mmu_stress_tests's VM with the correct number of extra pages needed to map all of memory in the guest. The bug hasn't been noticed before as the test currently runs only on x86, which maps guest memory with 1GiB pages, i.e. doesn't need much memory in the guest for page tables. Reviewed-by: James Houghton Signed-off-by: Sean Christopherson --- tools/testing/selftests/kvm/mmu_stress_test.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/kvm/mmu_stress_test.c b/tools/testing/= selftests/kvm/mmu_stress_test.c index 847da23ec1b1..5467b12f5903 100644 --- a/tools/testing/selftests/kvm/mmu_stress_test.c +++ b/tools/testing/selftests/kvm/mmu_stress_test.c @@ -209,7 +209,13 @@ int main(int argc, char *argv[]) vcpus =3D malloc(nr_vcpus * sizeof(*vcpus)); TEST_ASSERT(vcpus, "Failed to allocate vCPU array"); =20 - vm =3D vm_create_with_vcpus(nr_vcpus, guest_code, vcpus); + vm =3D __vm_create_with_vcpus(VM_SHAPE_DEFAULT, nr_vcpus, +#ifdef __x86_64__ + max_mem / SZ_1G, +#else + max_mem / vm_guest_mode_params[VM_MODE_DEFAULT].page_size, +#endif + guest_code, vcpus); =20 max_gpa =3D vm->max_gfn << vm->page_shift; TEST_ASSERT(max_gpa > (4 * slot_size), "MAXPHYADDR <4gb "); --=20 2.47.0.rc0.187.ge670bccf7e-goog From nobody Wed Nov 27 14:26:49 2024 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F11020408B for ; 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Wed, 09 Oct 2024 08:50:13 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 9 Oct 2024 08:49:48 -0700 In-Reply-To: <20241009154953.1073471-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241009154953.1073471-1-seanjc@google.com> X-Mailer: git-send-email 2.47.0.rc0.187.ge670bccf7e-goog Message-ID: <20241009154953.1073471-10-seanjc@google.com> Subject: [PATCH v3 09/14] KVM: sefltests: Explicitly include ucall_common.h in mmu_stress_test.c From: Sean Christopherson To: Marc Zyngier , Oliver Upton , Anup Patel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Paolo Bonzini , Christian Borntraeger , Janosch Frank , Claudio Imbrenda Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Sean Christopherson , Andrew Jones , James Houghton Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Explicitly include ucall_common.h in the MMU stress test, as unlike arm64 and x86-64, RISC-V doesn't include ucall_common.h in its processor.h, i.e. this will allow enabling the test on RISC-V. Reported-by: Andrew Jones Signed-off-by: Sean Christopherson --- tools/testing/selftests/kvm/mmu_stress_test.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/testing/selftests/kvm/mmu_stress_test.c b/tools/testing/= selftests/kvm/mmu_stress_test.c index 5467b12f5903..fbb693428a82 100644 --- a/tools/testing/selftests/kvm/mmu_stress_test.c +++ b/tools/testing/selftests/kvm/mmu_stress_test.c @@ -15,6 +15,7 @@ #include "test_util.h" #include "guest_modes.h" #include "processor.h" +#include "ucall_common.h" =20 static void guest_code(uint64_t start_gpa, uint64_t end_gpa, uint64_t stri= de) { --=20 2.47.0.rc0.187.ge670bccf7e-goog From nobody Wed Nov 27 14:26:49 2024 Received: from mail-pf1-f202.google.com (mail-pf1-f202.google.com [209.85.210.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 533BE204932 for ; Wed, 9 Oct 2024 15:50:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 09 Oct 2024 08:50:15 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 9 Oct 2024 08:49:49 -0700 In-Reply-To: <20241009154953.1073471-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241009154953.1073471-1-seanjc@google.com> X-Mailer: git-send-email 2.47.0.rc0.187.ge670bccf7e-goog Message-ID: <20241009154953.1073471-11-seanjc@google.com> Subject: [PATCH v3 10/14] KVM: selftests: Enable mmu_stress_test on arm64 From: Sean Christopherson To: Marc Zyngier , Oliver Upton , Anup Patel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Paolo Bonzini , Christian Borntraeger , Janosch Frank , Claudio Imbrenda Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Sean Christopherson , Andrew Jones , James Houghton Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable the mmu_stress_test on arm64. The intent was to enable the test across all architectures when it was first added, but a few goofs made it unrunnable on !x86. Now that those goofs are fixed, at least for arm64, enable the test. Cc: Oliver Upton Cc: Marc Zyngier Reviewed-by: James Houghton Signed-off-by: Sean Christopherson --- tools/testing/selftests/kvm/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests= /kvm/Makefile index 8c69a14dc93d..4db74792d689 100644 --- a/tools/testing/selftests/kvm/Makefile +++ b/tools/testing/selftests/kvm/Makefile @@ -178,6 +178,7 @@ TEST_GEN_PROGS_aarch64 +=3D kvm_create_max_vcpus TEST_GEN_PROGS_aarch64 +=3D kvm_page_table_test TEST_GEN_PROGS_aarch64 +=3D memslot_modification_stress_test TEST_GEN_PROGS_aarch64 +=3D memslot_perf_test +TEST_GEN_PROGS_aarch64 +=3D mmu_stress_test TEST_GEN_PROGS_aarch64 +=3D rseq_test TEST_GEN_PROGS_aarch64 +=3D set_memory_region_test TEST_GEN_PROGS_aarch64 +=3D steal_time --=20 2.47.0.rc0.187.ge670bccf7e-goog From nobody Wed Nov 27 14:26:49 2024 Received: from mail-yb1-f202.google.com (mail-yb1-f202.google.com [209.85.219.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C10B1204F66 for ; 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Wed, 09 Oct 2024 08:50:18 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 9 Oct 2024 08:49:50 -0700 In-Reply-To: <20241009154953.1073471-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241009154953.1073471-1-seanjc@google.com> X-Mailer: git-send-email 2.47.0.rc0.187.ge670bccf7e-goog Message-ID: <20241009154953.1073471-12-seanjc@google.com> Subject: [PATCH v3 11/14] KVM: selftests: Use vcpu_arch_put_guest() in mmu_stress_test From: Sean Christopherson To: Marc Zyngier , Oliver Upton , Anup Patel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Paolo Bonzini , Christian Borntraeger , Janosch Frank , Claudio Imbrenda Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Sean Christopherson , Andrew Jones , James Houghton Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use vcpu_arch_put_guest() to write memory from the guest in mmu_stress_test as an easy way to provide a bit of extra coverage. Reviewed-by: James Houghton Signed-off-by: Sean Christopherson --- tools/testing/selftests/kvm/mmu_stress_test.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/testing/selftests/kvm/mmu_stress_test.c b/tools/testing/= selftests/kvm/mmu_stress_test.c index fbb693428a82..656a837c7f49 100644 --- a/tools/testing/selftests/kvm/mmu_stress_test.c +++ b/tools/testing/selftests/kvm/mmu_stress_test.c @@ -23,7 +23,7 @@ static void guest_code(uint64_t start_gpa, uint64_t end_g= pa, uint64_t stride) =20 for (;;) { for (gpa =3D start_gpa; gpa < end_gpa; gpa +=3D stride) - *((volatile uint64_t *)gpa) =3D gpa; + vcpu_arch_put_guest(*((volatile uint64_t *)gpa), gpa); GUEST_SYNC(0); } } --=20 2.47.0.rc0.187.ge670bccf7e-goog From nobody Wed Nov 27 14:26:49 2024 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55790204F79 for ; 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Wed, 09 Oct 2024 08:50:20 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 9 Oct 2024 08:49:51 -0700 In-Reply-To: <20241009154953.1073471-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241009154953.1073471-1-seanjc@google.com> X-Mailer: git-send-email 2.47.0.rc0.187.ge670bccf7e-goog Message-ID: <20241009154953.1073471-13-seanjc@google.com> Subject: [PATCH v3 12/14] KVM: selftests: Precisely limit the number of guest loops in mmu_stress_test From: Sean Christopherson To: Marc Zyngier , Oliver Upton , Anup Patel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Paolo Bonzini , Christian Borntraeger , Janosch Frank , Claudio Imbrenda Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Sean Christopherson , Andrew Jones , James Houghton Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Run the exact number of guest loops required in mmu_stress_test instead of looping indefinitely in anticipation of adding more stages that run different code (e.g. reads instead of writes). Reviewed-by: James Houghton Signed-off-by: Sean Christopherson --- tools/testing/selftests/kvm/mmu_stress_test.c | 25 ++++++++++++++----- 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/tools/testing/selftests/kvm/mmu_stress_test.c b/tools/testing/= selftests/kvm/mmu_stress_test.c index 656a837c7f49..c6bf18cb7c89 100644 --- a/tools/testing/selftests/kvm/mmu_stress_test.c +++ b/tools/testing/selftests/kvm/mmu_stress_test.c @@ -20,12 +20,15 @@ static void guest_code(uint64_t start_gpa, uint64_t end_gpa, uint64_t stri= de) { uint64_t gpa; + int i; =20 - for (;;) { + for (i =3D 0; i < 2; i++) { for (gpa =3D start_gpa; gpa < end_gpa; gpa +=3D stride) vcpu_arch_put_guest(*((volatile uint64_t *)gpa), gpa); - GUEST_SYNC(0); + GUEST_SYNC(i); } + + GUEST_ASSERT(0); } =20 struct vcpu_info { @@ -52,10 +55,18 @@ static void rendezvous_with_boss(void) } } =20 -static void run_vcpu(struct kvm_vcpu *vcpu) +static void assert_sync_stage(struct kvm_vcpu *vcpu, int stage) +{ + struct ucall uc; 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Wed, 09 Oct 2024 08:50:22 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 9 Oct 2024 08:49:52 -0700 In-Reply-To: <20241009154953.1073471-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241009154953.1073471-1-seanjc@google.com> X-Mailer: git-send-email 2.47.0.rc0.187.ge670bccf7e-goog Message-ID: <20241009154953.1073471-14-seanjc@google.com> Subject: [PATCH v3 13/14] KVM: selftests: Add a read-only mprotect() phase to mmu_stress_test From: Sean Christopherson To: Marc Zyngier , Oliver Upton , Anup Patel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Paolo Bonzini , Christian Borntraeger , Janosch Frank , Claudio Imbrenda Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Sean Christopherson , Andrew Jones , James Houghton Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a third phase of mmu_stress_test to verify that mprotect()ing guest memory to make it read-only doesn't cause explosions, e.g. to verify KVM correctly handles the resulting mmu_notifier invalidations. Reviewed-by: James Houghton Signed-off-by: Sean Christopherson --- tools/testing/selftests/kvm/mmu_stress_test.c | 22 +++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/tools/testing/selftests/kvm/mmu_stress_test.c b/tools/testing/= selftests/kvm/mmu_stress_test.c index c6bf18cb7c89..0918fade9267 100644 --- a/tools/testing/selftests/kvm/mmu_stress_test.c +++ b/tools/testing/selftests/kvm/mmu_stress_test.c @@ -28,6 +28,10 @@ static void guest_code(uint64_t start_gpa, uint64_t end_= gpa, uint64_t stride) GUEST_SYNC(i); } =20 + for (gpa =3D start_gpa; gpa < end_gpa; gpa +=3D stride) + *((volatile uint64_t *)gpa); + GUEST_SYNC(2); + GUEST_ASSERT(0); } =20 @@ -95,6 +99,10 @@ static void *vcpu_worker(void *data) run_vcpu(vcpu, 1); rendezvous_with_boss(); =20 + /* Stage 2, read all of guest memory, which is now read-only. */ + run_vcpu(vcpu, 2); + rendezvous_with_boss(); + return NULL; } =20 @@ -175,7 +183,7 @@ int main(int argc, char *argv[]) const uint64_t start_gpa =3D SZ_4G; const int first_slot =3D 1; =20 - struct timespec time_start, time_run1, time_reset, time_run2; + struct timespec time_start, time_run1, time_reset, time_run2, time_ro; uint64_t max_gpa, gpa, slot_size, max_mem, i; int max_slots, slot, opt, fd; bool hugepages =3D false; @@ -279,14 +287,20 @@ int main(int argc, char *argv[]) rendezvous_with_vcpus(&time_reset, "reset"); rendezvous_with_vcpus(&time_run2, "run 2"); =20 + mprotect(mem, slot_size, PROT_READ); + rendezvous_with_vcpus(&time_ro, "mprotect RO"); + + time_ro =3D timespec_sub(time_ro, time_run2); time_run2 =3D timespec_sub(time_run2, time_reset); - time_reset =3D timespec_sub(time_reset, time_run1); + time_reset =3D timespec_sub(time_reset, time_run1); time_run1 =3D timespec_sub(time_run1, time_start); =20 - pr_info("run1 =3D %ld.%.9lds, reset =3D %ld.%.9lds, run2 =3D %ld.%.9lds\= n", + pr_info("run1 =3D %ld.%.9lds, reset =3D %ld.%.9lds, run2 =3D %ld.%.9lds, " + "ro =3D %ld.%.9lds\n", time_run1.tv_sec, time_run1.tv_nsec, time_reset.tv_sec, time_reset.tv_nsec, - time_run2.tv_sec, time_run2.tv_nsec); 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AJvYcCWzONEGEMP3nXFyLB16EyhNPdjWSPVzMF0GXjQDNH6SPVQYTC9XTQILQfseI5DAp5okgWpl/bZ04+KBles=@vger.kernel.org X-Gm-Message-State: AOJu0YyQh2N+XImIHup0MCWH1vpmuLl7bFm193pPyfmWwrvyCJjjv7Kb 2+oO9QH+GQd0xKBndKaHXXIKsn20BvP0zY3f3jWQaf7X/dGlNZZd+n2/DTsuq+lenBwF+tzRhU0 MSQ== X-Google-Smtp-Source: AGHT+IF06EOvabba1YpY/m+9TdddfKJv+phXMs6xFxlGn64HlbjifXqL0d0/QpkP5vVUJng9o1/hHhmQcTE= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:9d:3983:ac13:c240]) (user=seanjc job=sendgmr) by 2002:a17:902:d2c2:b0:20b:ad74:c83d with SMTP id d9443c01a7336-20c6377b2e8mr457555ad.8.1728489024593; Wed, 09 Oct 2024 08:50:24 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 9 Oct 2024 08:49:53 -0700 In-Reply-To: <20241009154953.1073471-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241009154953.1073471-1-seanjc@google.com> X-Mailer: git-send-email 2.47.0.rc0.187.ge670bccf7e-goog Message-ID: <20241009154953.1073471-15-seanjc@google.com> Subject: [PATCH v3 14/14] KVM: selftests: Verify KVM correctly handles mprotect(PROT_READ) From: Sean Christopherson To: Marc Zyngier , Oliver Upton , Anup Patel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Paolo Bonzini , Christian Borntraeger , Janosch Frank , Claudio Imbrenda Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Sean Christopherson , Andrew Jones , James Houghton Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add two phases to mmu_stress_test to verify that KVM correctly handles guest memory that was writable, and then made read-only in the primary MMU, and then made writable again. Add bonus coverage for x86 and arm64 to verify that all of guest memory was marked read-only. Making forward progress (without making memory writable) requires arch specific code to skip over the faulting instruction, but the test can at least verify each vCPU's starting page was made read-only for other architectures. Signed-off-by: Sean Christopherson --- tools/testing/selftests/kvm/mmu_stress_test.c | 104 +++++++++++++++++- 1 file changed, 101 insertions(+), 3 deletions(-) diff --git a/tools/testing/selftests/kvm/mmu_stress_test.c b/tools/testing/= selftests/kvm/mmu_stress_test.c index 0918fade9267..d9c76b4c0d88 100644 --- a/tools/testing/selftests/kvm/mmu_stress_test.c +++ b/tools/testing/selftests/kvm/mmu_stress_test.c @@ -17,6 +17,8 @@ #include "processor.h" #include "ucall_common.h" =20 +static bool mprotect_ro_done; + static void guest_code(uint64_t start_gpa, uint64_t end_gpa, uint64_t stri= de) { uint64_t gpa; @@ -32,6 +34,42 @@ static void guest_code(uint64_t start_gpa, uint64_t end_= gpa, uint64_t stride) *((volatile uint64_t *)gpa); GUEST_SYNC(2); =20 + /* + * Write to the region while mprotect(PROT_READ) is underway. Keep + * looping until the memory is guaranteed to be read-only, otherwise + * vCPUs may complete their writes and advance to the next stage + * prematurely. + * + * For architectures that support skipping the faulting instruction, + * generate the store via inline assembly to ensure the exact length + * of the instruction is known and stable (vcpu_arch_put_guest() on + * fixed-length architectures should work, but the cost of paranoia + * is low in this case). For x86, hand-code the exact opcode so that + * there is no room for variability in the generated instruction. + */ + do { + for (gpa =3D start_gpa; gpa < end_gpa; gpa +=3D stride) +#ifdef __x86_64__ + asm volatile(".byte 0x48,0x89,0x00" :: "a"(gpa) : "memory"); /* mov %ra= x, (%rax) */ +#elif defined(__aarch64__) + asm volatile("str %0, [%0]" :: "r" (gpa) : "memory"); +#else + vcpu_arch_put_guest(*((volatile uint64_t *)gpa), gpa); +#endif + } while (!READ_ONCE(mprotect_ro_done)); + + /* + * Only architectures that write the entire range can explicitly sync, + * as other architectures will be stuck on the write fault. + */ +#if defined(__x86_64__) || defined(__aarch64__) + GUEST_SYNC(3); +#endif + + for (gpa =3D start_gpa; gpa < end_gpa; gpa +=3D stride) + vcpu_arch_put_guest(*((volatile uint64_t *)gpa), gpa); + GUEST_SYNC(4); + GUEST_ASSERT(0); } =20 @@ -79,6 +117,7 @@ static void *vcpu_worker(void *data) struct vcpu_info *info =3D data; struct kvm_vcpu *vcpu =3D info->vcpu; struct kvm_vm *vm =3D vcpu->vm; + int r; =20 vcpu_args_set(vcpu, 3, info->start_gpa, info->end_gpa, vm->page_size); =20 @@ -101,6 +140,57 @@ static void *vcpu_worker(void *data) =20 /* Stage 2, read all of guest memory, which is now read-only. */ run_vcpu(vcpu, 2); + + /* + * Stage 3, write guest memory and verify KVM returns -EFAULT for once + * the mprotect(PROT_READ) lands. Only architectures that support + * validating *all* of guest memory sync for this stage, as vCPUs will + * be stuck on the faulting instruction for other architectures. Go to + * stage 3 without a rendezvous + */ + do { + r =3D _vcpu_run(vcpu); + } while (!r); + TEST_ASSERT(r =3D=3D -1 && errno =3D=3D EFAULT, + "Expected EFAULT on write to RO memory, got r =3D %d, errno =3D %d",= r, errno); + +#if defined(__x86_64__) || defined(__aarch64__) + /* + * Verify *all* writes from the guest hit EFAULT due to the VMA now + * being read-only. x86 and arm64 only at this time as skipping the + * instruction that hits the EFAULT requires advancing the program + * counter, which is arch specific and relies on inline assembly. + */ +#ifdef __x86_64__ + vcpu->run->kvm_valid_regs =3D KVM_SYNC_X86_REGS; +#endif + for (;;) { + r =3D _vcpu_run(vcpu); + if (!r) + break; + TEST_ASSERT_EQ(errno, EFAULT); +#if defined(__x86_64__) + WRITE_ONCE(vcpu->run->kvm_dirty_regs, KVM_SYNC_X86_REGS); + vcpu->run->s.regs.regs.rip +=3D 3; +#elif defined(__aarch64__) + vcpu_set_reg(vcpu, ARM64_CORE_REG(regs.pc), + vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc)) + 4); +#endif + + } + assert_sync_stage(vcpu, 3); +#endif /* __x86_64__ || __aarch64__ */ + rendezvous_with_boss(); + + /* + * Stage 4. Run to completion, waiting for mprotect(PROT_WRITE) to + * make the memory writable again. + */ + do { + r =3D _vcpu_run(vcpu); + } while (r && errno =3D=3D EFAULT); + TEST_ASSERT_EQ(r, 0); + assert_sync_stage(vcpu, 4); rendezvous_with_boss(); =20 return NULL; @@ -183,7 +273,7 @@ int main(int argc, char *argv[]) const uint64_t start_gpa =3D SZ_4G; const int first_slot =3D 1; =20 - struct timespec time_start, time_run1, time_reset, time_run2, time_ro; + struct timespec time_start, time_run1, time_reset, time_run2, time_ro, ti= me_rw; uint64_t max_gpa, gpa, slot_size, max_mem, i; int max_slots, slot, opt, fd; bool hugepages =3D false; @@ -288,19 +378,27 @@ int main(int argc, char *argv[]) rendezvous_with_vcpus(&time_run2, "run 2"); =20 mprotect(mem, slot_size, PROT_READ); + usleep(10); + mprotect_ro_done =3D true; + sync_global_to_guest(vm, mprotect_ro_done); + rendezvous_with_vcpus(&time_ro, "mprotect RO"); + mprotect(mem, slot_size, PROT_READ | PROT_WRITE); + rendezvous_with_vcpus(&time_rw, "mprotect RW"); =20 + time_rw =3D timespec_sub(time_rw, time_ro); time_ro =3D timespec_sub(time_ro, time_run2); time_run2 =3D timespec_sub(time_run2, time_reset); time_reset =3D timespec_sub(time_reset, time_run1); time_run1 =3D timespec_sub(time_run1, time_start); =20 pr_info("run1 =3D %ld.%.9lds, reset =3D %ld.%.9lds, run2 =3D %ld.%.9lds, " - "ro =3D %ld.%.9lds\n", + "ro =3D %ld.%.9lds, rw =3D %ld.%.9lds\n", time_run1.tv_sec, time_run1.tv_nsec, time_reset.tv_sec, time_reset.tv_nsec, time_run2.tv_sec, time_run2.tv_nsec, - time_ro.tv_sec, time_ro.tv_nsec); + time_ro.tv_sec, time_ro.tv_nsec, + time_rw.tv_sec, time_rw.tv_nsec); =20 /* * Delete even numbered slots (arbitrary) and unmap the first half of --=20 2.47.0.rc0.187.ge670bccf7e-goog