From nobody Wed Nov 27 16:38:25 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1DA84192B89; Wed, 9 Oct 2024 12:02:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728475367; cv=none; b=QBWtFJIJTgIzsmWF4rqwP2n74nXUvuGuwoCFivR85ANT38tfYCc+Am3bYl+9cjs0+DdWn6WqTE6vRZh/nULsXEkmDreEWzcmxIKXtPmp70PQpeSExoijxiiXHk9HPGip7MMsrpp3NDgS3uU2TK9tfI8Q6ui6nqsSIFgoqP1ba+k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728475367; c=relaxed/simple; bh=5eJ5itnq5Pqo2kCd+48EfVWhNr9i4pzZ8iS7x/qcYKc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=CXiFg39mfpCjRXMDImLyMCmbPHnpl2YfijnX2IVa2BSe+vvBeCDajyXQ62KoERqten9J0vdRYEfq2Mm3fhBztTrM/1KoIw9LyAnxMKw94mwPv5mZVYU3bvU4AmJQGj4q2Atx30p6ZnuyT9EQtNYgymBzcUj7eB6Pi5XdU4NCMC0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=J2yN2wWv; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="J2yN2wWv" X-UUID: 6127667c863611ef88ecadb115cee93b-20241009 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=0HZS/yt81yGM8+lk4cRjFAiTKAwgRjPBEqGkttJks2E=; b=J2yN2wWvcJj7fWAxi2uQ0GiJfEaN2dMt3RLgzcpdlUPDgYiVjPu9w3EAobvyGA36vEM5+64Ww0bQA4h8mg1gXAmq/oIOjSzDePIz/RYrZ7snXL/QqgNvnRRXCiGK57JV/dXTFAmCf7IgwTG8zuy3PBrrxfk/lrrMTneDVafzuo8=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.41,REQID:7ccae316-1702-40d6-b998-af3b96d4bb48,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:6dc6a47,CLOUDID:ebc6fe64-444a-4b47-a99a-591ade3b04b2,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES :1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: 6127667c863611ef88ecadb115cee93b-20241009 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1072874375; Wed, 09 Oct 2024 20:02:38 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 9 Oct 2024 20:02:37 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 9 Oct 2024 20:02:36 +0800 From: Andy-ld Lu To: , , , , , CC: , , , , , Andy-ld Lu , Krzysztof Kozlowski Subject: [PATCH v3 3/3] dt-bindings: mmc: mtk-sd: Add support for MT8196 Date: Wed, 9 Oct 2024 20:01:26 +0800 Message-ID: <20241009120203.14913-4-andy-ld.lu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20241009120203.14913-1-andy-ld.lu@mediatek.com> References: <20241009120203.14913-1-andy-ld.lu@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extend the devicetree bindings to include the MT8196 mmc controller, new tx/rx would be supported from MT8196, and the register settings of STOP_DLY_SEL and POP_EN_CNT would also be variant. Signed-off-by: Andy-ld Lu Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentat= ion/devicetree/bindings/mmc/mtk-sd.yaml index c532ec92d2d9..9281a0326891 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml @@ -24,6 +24,7 @@ properties: - mediatek,mt8135-mmc - mediatek,mt8173-mmc - mediatek,mt8183-mmc + - mediatek,mt8196-mmc - mediatek,mt8516-mmc - items: - const: mediatek,mt7623-mmc @@ -190,6 +191,7 @@ allOf: - mediatek,mt8186-mmc - mediatek,mt8188-mmc - mediatek,mt8195-mmc + - mediatek,mt8196-mmc - mediatek,mt8516-mmc then: properties: --=20 2.46.0