From nobody Wed Nov 27 16:55:53 2024 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B91E7192B74; Wed, 9 Oct 2024 11:58:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728475110; cv=none; b=fLwqxxAACWF6Tzu+KuvBfVv/c2UOhfWPiDVAKgjgmIN2RhUn7orkF9mJGk6g4xKNcjDW5MdlNbkP6PAeo9LfJg0xhcEqMkeNHC9PFVzLTTmYxymgQ3JvirFDlhLxmHoLpGsPGMRsIlcryiE/HxiSJJM0wgh+HG2G5riLmpgVk+M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728475110; c=relaxed/simple; bh=1W3KdtQLZREJ1HZXpeHa/+Chww0aNa7K4ZfTee0fnE0=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kg7+YslBI/rVJdwoiyZfZckRp69GpOTrMwPeAGq816y+CKzUst7QGfUFm+fXSXU5Lvo/PVXMeiGYtVriZv1hFlame7YX5GfoL7nCLhaliziCZK+7axCm5qs4WepXu3mRwGIhpX0+FQ+/9uonbmiOypcUu9OefNaWRC6hJr9gXMo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Wed, 9 Oct 2024 19:58:18 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Wed, 9 Oct 2024 19:58:18 +0800 From: Kevin Chen To: , , , , , , , , , , Subject: [PATCH v3 1/2] dt-bindings: interrupt-controller: Add support for ASPEED AST27XX INTC Date: Wed, 9 Oct 2024 19:58:12 +0800 Message-ID: <20241009115813.2908803-2-kevin_chen@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241009115813.2908803-1-kevin_chen@aspeedtech.com> References: <20241009115813.2908803-1-kevin_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The ASPEED AST27XX interrupt controller(INTC) contain second level and third level interrupt controller. INTC0: The second level INTC, which used to assert GIC(#192~#197) if interrupt in INTC1 asserted. There are 6 GIC interrupt number(#192~#197) used in one INTC0. INTC1_x: The third level INTC, which used to assert GIC(#192~#197) if interrupt in INTC1 asserted. There are 6 GIC interrupt number(#192~#197) used in one INT= C0. Signed-off-by: Kevin Chen --- .../aspeed,ast2700-intc.yaml | 87 +++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= aspeed,ast2700-intc.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,= ast2700-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/= aspeed,ast2700-intc.yaml new file mode 100644 index 000000000000..650a1f6e1177 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700= -intc.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-int= c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed AST2700 Interrupt Controller + +description: + This interrupt controller hardware is second level interrupt controller = that + is hooked to a parent interrupt controller. It's useful to combine multi= ple + interrupt sources into 1 interrupt to parent interrupt controller. + +maintainers: + - Kevin Chen + +properties: + compatible: + enum: + - aspeed,ast2700-intc-ic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + maxItems: 10 + description: + Depend to which INTC0 or INTC1 used. + INTC0 and INTC1 are two kinds of interrupt controller with enable an= d raw + status registers for use. + INTC0 is used to assert GIC if interrupt in INTC1 asserted. + INTC1 is used to assert INTC0 if interrupt of modules asserted. + +-----+ +-------+ +---------+---module0 + | GIC |---| INTC0 |--+--| INTC1_0 |---module2 + | | | | | | |---... + +-----+ +-------+ | +---------+---module31 + | + | +---------+---module0 + +---| INTC1_1 |---module2 + | | |---... + | +---------+---module31 + ... + | +---------+---module0 + +---| INTC1_5 |---module2 + | |---... + +---------+---module31 + + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - interrupts + +additionalProperties: false + +examples: + - | + #include + + bus { + #address-cells =3D <2>; + #size-cells =3D <2>; + + interrupt-controller@12101b00 { + compatible =3D "aspeed,ast2700-intc-ic"; + reg =3D <0 0x12101b00 0 0x10>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts =3D , + , + , + , + , + , + , + , + , + ; + }; + }; --=20 2.34.1