From nobody Wed Nov 27 16:41:24 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BDEDE18DF62; Wed, 9 Oct 2024 09:57:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728467822; cv=none; b=ud3y7CDTxqdXL1MPoWCazGzSkyg0B2hBBRt+X45lZYvIUsK2JO4cSgSAgRgZGm6kEzORCkQ0HaXEMekXz3sPFZJR1I1sIp0LmPPh31sXf3pADPkAKfoeCWvArY6GinHEutMp+1aMhmNYE6oDp+6LUAY2Gxw5BHHP1r08ZkyouVE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728467822; c=relaxed/simple; bh=HEEcfnOq54LR0U51mqX/+LvcTri4c03Xzg8uUxcuZx0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tDwWVwW3K7l052P4lcSdHQb0jkelZ/uMpa22JdMfaqGe46g349kuWPhK45kFYHSQ3xPOIOvz/AMW+ZCpvQjdfkbQPNtb4F9CGUxzxFvnmf3VsMqHTgIogdlVZUeQGOdCmY+HAbg48cv4wahBape8JWW8OVqCfRyqTtcR1H/1rGU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=A1431uoF; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="A1431uoF" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4995cA3b022378; Wed, 9 Oct 2024 09:56:39 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 9T6vDCQgh1gIYQoLsdnmEUZ+H4oulTkXaYpu8/f4F1Q=; b=A1431uoFL/8i4WTN HcfVDynIeT7hDms+zyiKbBTe+EUXiKIlQA7Riy66O4eSw27+y4CNLND+GM7OIgR9 fNHJmQMErMe4zLF9zRwtahNlXau0rCxF8RvLkzuqs6w+rz1Madlpm+uaY+MIwJkR pd0icp4DovVj6Snm+x1IxsOXMrp7kwNiTIKGLsBOHyuSw4CPMOBJvmAB5vxmZunG Lci/cf6dU7e46TrygHoDyhE8CPWVuYSlZ2ISV5xBJsTsGwjcRG/YiS6BBK3xJG3Z nt1ZkntVjfGj1n2xQYqULPmais9bnySV0E7qpzHCxgTCCaytOSwVCIaugxqIUO9Z y3qipQ== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 424kaewk6v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 09 Oct 2024 09:56:39 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4999ucJJ010669 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 9 Oct 2024 09:56:38 GMT Received: from jiegan-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 9 Oct 2024 02:56:32 -0700 From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , "Alexander Shishkin" , Maxime Coquelin , Alexandre Torgue , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio CC: Jinlong Mao , , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Song Chai , , Subject: [PATCH v5 RESEND 3/5] dt-bindings: arm: Add Coresight TMC Control Unit hardware Date: Wed, 9 Oct 2024 17:55:54 +0800 Message-ID: <20241009095556.1754876-4-quic_jiegan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241009095556.1754876-1-quic_jiegan@quicinc.com> References: <20241009095556.1754876-1-quic_jiegan@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 0-toF4dwtZaS0gDmIw2FuAsR-JOG-e5R X-Proofpoint-GUID: 0-toF4dwtZaS0gDmIw2FuAsR-JOG-e5R X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 adultscore=1 spamscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 impostorscore=0 priorityscore=1501 mlxlogscore=999 suspectscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410090064 Content-Type: text/plain; charset="utf-8" Add binding file to specify how to define a Coresight TMC Control Unit device in device tree. It is responsible for controlling the data filter function based on the source device's Trace ID for TMC ETR device. The trace data with that Trace id can get into ETR's buffer while other trace data gets ignored. Reviewed-by: Rob Herring (Arm) Signed-off-by: Jie Gan --- .../bindings/arm/qcom,coresight-ctcu.yaml | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-ct= cu.yaml diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml= b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml new file mode 100644 index 000000000000..843b52eaf872 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/qcom,coresight-ctcu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CoreSight TMC Control Unit + +maintainers: + - Yuanfang Zhang + - Mao Jinlong + - Jie Gan + +description: | + The Trace Memory Controller(TMC) is used for Embedded Trace Buffer(ETB), + Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR) configurations. + The configuration mode (ETB, ETF, ETR) is discovered at boot time when + the device is probed. + + The Coresight TMC Control unit controls various Coresight behaviors. + It works as a helper device when connected to TMC ETR device. + It is responsible for controlling the data filter function based on + the source device's Trace ID for TMC ETR device. The trace data with + that Trace id can get into ETR's buffer while other trace data gets + ignored. + +properties: + compatible: + enum: + - qcom,sa8775p-ctcu + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + + patternProperties: + '^port(@[0-1])?$': + description: Input connections from CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - in-ports + +additionalProperties: false + +examples: + - | + ctcu@1001000 { + compatible =3D "qcom,sa8775p-ctcu"; + reg =3D <0x1001000 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + ctcu_in_port0: endpoint { + remote-endpoint =3D <&etr0_out_port>; + }; + }; + + port@1 { + reg =3D <1>; + ctcu_in_port1: endpoint { + remote-endpoint =3D <&etr1_out_port>; + }; + }; + }; + }; --=20 2.34.1