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Wed, 09 Oct 2024 09:15:50 +0000 (GMT) Received: from pps.filterd (NALASPPMTA01.qualcomm.com [127.0.0.1]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 4999FnNs027448; Wed, 9 Oct 2024 09:15:49 GMT Received: from pps.reinject (localhost [127.0.0.1]) by NALASPPMTA01.qualcomm.com (PPS) with ESMTPS id 425cdvw4rd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 09 Oct 2024 09:15:49 +0000 Received: from NALASPPMTA01.qualcomm.com (NALASPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 49996b1L000693; Wed, 9 Oct 2024 09:15:49 GMT Received: from hu-devc-lv-u22-c.qualcomm.com (hu-qianyu-lv.qualcomm.com [10.81.25.114]) by NALASPPMTA01.qualcomm.com (PPS) with ESMTPS id 4999FnQ8027437 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 09 Oct 2024 09:15:49 +0000 Received: by hu-devc-lv-u22-c.qualcomm.com (Postfix, from userid 4098150) id 09FA3656; Wed, 9 Oct 2024 02:15:49 -0700 (PDT) From: Qiang Yu To: manivannan.sadhasivam@linaro.org, vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, andersson@kernel.org, konradybcio@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, abel.vesa@linaro.org, quic_msarkar@quicinc.com, quic_devipriy@quicinc.com Cc: dmitry.baryshkov@linaro.org, kw@linux.com, lpieralisi@kernel.org, neil.armstrong@linaro.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Qiang Yu Subject: [PATCH v5 6/7] PCI: qcom: Fix the ops for X1E80100 and SC8280X family SoC Date: Wed, 9 Oct 2024 02:15:39 -0700 Message-Id: <20241009091540.1446-7-quic_qianyu@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241009091540.1446-1-quic_qianyu@quicinc.com> References: <20241009091540.1446-1-quic_qianyu@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: xM1KA-pfNJLpOcKnTp1QJlQyop0Er0Sc X-Proofpoint-ORIG-GUID: xM1KA-pfNJLpOcKnTp1QJlQyop0Er0Sc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 phishscore=0 mlxlogscore=999 spamscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 adultscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410090060 Content-Type: text/plain; charset="utf-8" On X1E80100 and SC8280X family SoC, PCIe controllers are connected to SMMUv3, hence they don't need the config_sid() callback in ops_1_9_0 struct. Fix it by introducing a new ops struct, namely ops_1_21_0, so that BDF2SID mapping won't be configured during init. In addition, since it is recommended to disable ASPM L0s on X1E80100 as same as SC8280X, hence X1E80100 can simply reuse cfg_sc8280xp as its config. Signed-off-by: Qiang Yu --- drivers/pci/controller/dwc/pcie-qcom.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 88a98be930e3..c533e6024ba2 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1367,6 +1367,16 @@ static const struct qcom_pcie_ops ops_2_9_0 =3D { .ltssm_enable =3D qcom_pcie_2_3_2_ltssm_enable, }; =20 +/* Qcom IP rev.: 1.21.0 */ +static const struct qcom_pcie_ops ops_1_21_0 =3D { + .get_resources =3D qcom_pcie_get_resources_2_7_0, + .init =3D qcom_pcie_init_2_7_0, + .post_init =3D qcom_pcie_post_init_2_7_0, + .host_post_init =3D qcom_pcie_host_post_init_2_7_0, + .deinit =3D qcom_pcie_deinit_2_7_0, + .ltssm_enable =3D qcom_pcie_2_3_2_ltssm_enable, +}; + static const struct qcom_pcie_cfg cfg_1_0_0 =3D { .ops =3D &ops_1_0_0, }; @@ -1405,7 +1415,7 @@ static const struct qcom_pcie_cfg cfg_2_9_0 =3D { }; =20 static const struct qcom_pcie_cfg cfg_sc8280xp =3D { - .ops =3D &ops_1_9_0, + .ops =3D &ops_1_21_0, .no_l0s =3D true, }; =20 @@ -1837,7 +1847,7 @@ static const struct of_device_id qcom_pcie_match[] = =3D { { .compatible =3D "qcom,pcie-sm8450-pcie0", .data =3D &cfg_1_9_0 }, { .compatible =3D "qcom,pcie-sm8450-pcie1", .data =3D &cfg_1_9_0 }, { .compatible =3D "qcom,pcie-sm8550", .data =3D &cfg_1_9_0 }, - { .compatible =3D "qcom,pcie-x1e80100", .data =3D &cfg_1_9_0 }, + { .compatible =3D "qcom,pcie-x1e80100", .data =3D &cfg_sc8280xp }, { } }; =20 --=20 2.34.1