From nobody Wed Nov 27 16:50:00 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6287618FC6B; Wed, 9 Oct 2024 09:16:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728465370; cv=none; b=iQ1adl6CmJc3/us+8kG0JmQ+1voqNJXt7wWqPnysaq6tV287yi7TNMGOEHM1HZiDdTYRVmGWbM2qakgsZri6UPsjC3y8PDjm569SS9H/03y71pNOuJz9RK8b5+88pDguAOtX+8HtTiHQjDdHKJezfnXeGXeitGqTQqCNlmxhpGo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728465370; c=relaxed/simple; bh=H1ziV5tyupxzZh4Cd1MkMsrgUXkihHsPR7l8O8TlpOg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hrgkCtRQ9/PGIec5+ErLduzIC/fANjgGfRoYo6w0h6YHX148epjpzSYd+5VrFDfmDKcJj4jpp0RluXRadlls1a9paOmYR2YjM1bL3ahuTHjLMpjEB4eCyZdYkzQwgA61OP0Es+9A3ZS0YFKzNdXbIleFWR3Nfk3uhxO0cQNP86o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=AynCizNT; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="AynCizNT" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49986qRm025656; Wed, 9 Oct 2024 09:15:49 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=fM+DrFtFwy1 +oio8hpHJjcoOsNaQT5+Glmr5yzAR83g=; b=AynCizNT5kk+4InbtS5j9Gy+Qgq /53hLlYuRPLKMX173r5cq1gGiWNJKkfGcPDCmoal+jNLMIarCDfPx5MOk3sgh0lT +jecP/okfFw0KOQTQ/htK5eoVdar42n9yibn30s0ctC91eoGllptucQ02v9OQTVx zm+N2ENkho+/PGo6d2sVbkgsA/3Ee+tf0MpuWwGLuGw3RCnZvkiuUhXtsCFgZ13Q VxbSxlRW5XYqusmz8v4yUDXO+610acCgHmpwbYsH/xHaTgZ4O8XcJ1v7zeBMe0pm EjqSsZc36ynaZ84xDS9FkLE+haY7+Wq9I9iFmok17mvo1X7rdzvEtAL+3Sg== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4258pst336-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 09 Oct 2024 09:15:49 +0000 (GMT) Received: from pps.filterd (NALASPPMTA04.qualcomm.com [127.0.0.1]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 4999BNvR000864; Wed, 9 Oct 2024 09:15:48 GMT Received: from pps.reinject (localhost [127.0.0.1]) by NALASPPMTA04.qualcomm.com (PPS) with ESMTPS id 425cbww5gd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 09 Oct 2024 09:15:48 +0000 Received: from NALASPPMTA04.qualcomm.com (NALASPPMTA04.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 49996RC2017554; Wed, 9 Oct 2024 09:15:48 GMT Received: from hu-devc-lv-u22-c.qualcomm.com (hu-qianyu-lv.qualcomm.com [10.81.25.114]) by NALASPPMTA04.qualcomm.com (PPS) with ESMTPS id 4999FmEM013694 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 09 Oct 2024 09:15:48 +0000 Received: by hu-devc-lv-u22-c.qualcomm.com (Postfix, from userid 4098150) id 1D651656; Wed, 9 Oct 2024 02:15:48 -0700 (PDT) From: Qiang Yu To: manivannan.sadhasivam@linaro.org, vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, andersson@kernel.org, konradybcio@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, abel.vesa@linaro.org, quic_msarkar@quicinc.com, quic_devipriy@quicinc.com Cc: dmitry.baryshkov@linaro.org, kw@linux.com, lpieralisi@kernel.org, neil.armstrong@linaro.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Qiang Yu , stable@vger.kernel.org, Mike Tipton , Johan Hovold Subject: [PATCH v5 5/7] clk: qcom: gcc-x1e80100: Fix halt_check for pipediv2 clocks Date: Wed, 9 Oct 2024 02:15:38 -0700 Message-Id: <20241009091540.1446-6-quic_qianyu@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241009091540.1446-1-quic_qianyu@quicinc.com> References: <20241009091540.1446-1-quic_qianyu@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: X6R3JhV-EvWrRhHfP6My7FtSktUCkqYp X-Proofpoint-ORIG-GUID: X6R3JhV-EvWrRhHfP6My7FtSktUCkqYp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 mlxscore=0 bulkscore=0 impostorscore=0 clxscore=1011 suspectscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 adultscore=0 mlxlogscore=954 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410090060 Content-Type: text/plain; charset="utf-8" The pipediv2_clk's source from the same mux as pipe clock. So they have same limitation, which is that the PHY sequence requires to enable these local CBCs before the PHY is actually outputting a clock to them. This means the clock won't actually turn on when we vote them. Hence, let's skip the halt bit check of the pipediv2_clk, otherwise pipediv2_clk may stuck at off state during bootup. Cc: stable@vger.kernel.org Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver f= or X1E80100") Suggested-by: Mike Tipton Signed-off-by: Qiang Yu Reviewed-by: Konrad Dybcio Reviewed-by: Johan Hovold --- drivers/clk/qcom/gcc-x1e80100.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/clk/qcom/gcc-x1e80100.c b/drivers/clk/qcom/gcc-x1e8010= 0.c index 0f578771071f..81ba5ceab342 100644 --- a/drivers/clk/qcom/gcc-x1e80100.c +++ b/drivers/clk/qcom/gcc-x1e80100.c @@ -3123,7 +3123,7 @@ static struct clk_branch gcc_pcie_3_pipe_clk =3D { =20 static struct clk_branch gcc_pcie_3_pipediv2_clk =3D { .halt_reg =3D 0x58060, - .halt_check =3D BRANCH_HALT_VOTED, + .halt_check =3D BRANCH_HALT_SKIP, .clkr =3D { .enable_reg =3D 0x52020, .enable_mask =3D BIT(5), @@ -3248,7 +3248,7 @@ static struct clk_branch gcc_pcie_4_pipe_clk =3D { =20 static struct clk_branch gcc_pcie_4_pipediv2_clk =3D { .halt_reg =3D 0x6b054, - .halt_check =3D BRANCH_HALT_VOTED, + .halt_check =3D BRANCH_HALT_SKIP, .clkr =3D { .enable_reg =3D 0x52010, .enable_mask =3D BIT(27), @@ -3373,7 +3373,7 @@ static struct clk_branch gcc_pcie_5_pipe_clk =3D { =20 static struct clk_branch gcc_pcie_5_pipediv2_clk =3D { .halt_reg =3D 0x2f054, - .halt_check =3D BRANCH_HALT_VOTED, + .halt_check =3D BRANCH_HALT_SKIP, .clkr =3D { .enable_reg =3D 0x52018, .enable_mask =3D BIT(19), @@ -3511,7 +3511,7 @@ static struct clk_branch gcc_pcie_6a_pipe_clk =3D { =20 static struct clk_branch gcc_pcie_6a_pipediv2_clk =3D { .halt_reg =3D 0x31060, - .halt_check =3D BRANCH_HALT_VOTED, + .halt_check =3D BRANCH_HALT_SKIP, .clkr =3D { .enable_reg =3D 0x52018, .enable_mask =3D BIT(28), @@ -3649,7 +3649,7 @@ static struct clk_branch gcc_pcie_6b_pipe_clk =3D { =20 static struct clk_branch gcc_pcie_6b_pipediv2_clk =3D { .halt_reg =3D 0x8d060, - .halt_check =3D BRANCH_HALT_VOTED, + .halt_check =3D BRANCH_HALT_SKIP, .clkr =3D { .enable_reg =3D 0x52010, .enable_mask =3D BIT(28), --=20 2.34.1