From nobody Wed Nov 27 16:45:41 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1CD917DE2D; Wed, 9 Oct 2024 09:15:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728465357; cv=none; b=ZEKE76X1nZ/sOZRwLB6cT7vcUgpHZ9P39CNvs1KWBTC89ftLVEYQITKNFYvPtVhYP8O6GafUoyPhi12AprwT4vh4E99TYExUBkcrLgvu1s5kVeSS+ftzY6wAOPAlF/fuqIidHuGfWJXoLQVInSxuqXydv5qS9fvI0dEcfpItc4o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728465357; c=relaxed/simple; bh=LrpI0dD2DjCEDRs5OuXV4EpLBYMv216CkNSw0TFh9m8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=AuYJOwsjPnp5P+wDw/FTu1yqYRJSTN05o7tiaWp5vEnurTC3uWq2e3M6XMJwbkpkBxkNU+6LLW5D5eXwtJf7+FRNR9+GrHLD1FXvPksI5hl6j8lJpOj26INzvDTFp6q0W8S6KvEBSBpN+IYYNyQOr3QAAqdwGmx4bChlbwSS2aw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=SVKEXQ7F; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="SVKEXQ7F" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4995xvRY026856; Wed, 9 Oct 2024 09:15:47 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=hcPms38KKhb Ru3or83Mvz85iKMK7wQ3C9wLMciB9yLk=; b=SVKEXQ7F4UpFYfCYhezJAstQBEL Ci1DdSDACfOLiPknN/9uCBUztjHj3SgvAGZ6o3f91fplTnepau+4772D4yJQaSFH R0lmGo7jPChJFMjXGOf9LO8JdsXWSCMWLVFtLk0dKdlumolWgZ5ZXTQqZgZyLIiB 0Mcy2MNha8cbsgctwR+PG53k7EBod1gyGEeVh7LZfYEoElblxdBrCaNuSkCcFD5L LF+VHfkXlMcNkwezJKU/QXg3dPilIGdcwkxZvwN/A/VnigntsZIhywdBPipm3+CZ qthoRJ5gxlTHXlt3JlGDJwC3DP72pYIfHDfTrTwR+KAByHuMf5JjsfJ3aWw== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 422xqa2bbf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 09 Oct 2024 09:15:47 +0000 (GMT) Received: from pps.filterd (NALASPPMTA02.qualcomm.com [127.0.0.1]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 49997bgc010729; Wed, 9 Oct 2024 09:15:46 GMT Received: from pps.reinject (localhost [127.0.0.1]) by NALASPPMTA02.qualcomm.com (PPS) with ESMTPS id 425ccrd57a-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 09 Oct 2024 09:15:46 +0000 Received: from NALASPPMTA02.qualcomm.com (NALASPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 4999Fk20004313; Wed, 9 Oct 2024 09:15:46 GMT Received: from hu-devc-lv-u22-c.qualcomm.com (hu-qianyu-lv.qualcomm.com [10.81.25.114]) by NALASPPMTA02.qualcomm.com (PPS) with ESMTPS id 4999Fj2r004297 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 09 Oct 2024 09:15:46 +0000 Received: by hu-devc-lv-u22-c.qualcomm.com (Postfix, from userid 4098150) id C0453656; Wed, 9 Oct 2024 02:15:45 -0700 (PDT) From: Qiang Yu To: manivannan.sadhasivam@linaro.org, vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, andersson@kernel.org, konradybcio@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, abel.vesa@linaro.org, quic_msarkar@quicinc.com, quic_devipriy@quicinc.com Cc: dmitry.baryshkov@linaro.org, kw@linux.com, lpieralisi@kernel.org, neil.armstrong@linaro.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Qiang Yu Subject: [PATCH v5 3/7] dt-bindings: PCI: qcom,pcie-x1e80100: Add 'global' interrupt Date: Wed, 9 Oct 2024 02:15:36 -0700 Message-Id: <20241009091540.1446-4-quic_qianyu@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241009091540.1446-1-quic_qianyu@quicinc.com> References: <20241009091540.1446-1-quic_qianyu@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: AotMRjP3mSqpq7RHsI_BCTgMBSh95LYe X-Proofpoint-GUID: AotMRjP3mSqpq7RHsI_BCTgMBSh95LYe X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 suspectscore=0 malwarescore=0 adultscore=0 mlxlogscore=999 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410090060 Content-Type: text/plain; charset="utf-8" Document 'global' SPI interrupt along with the existing MSI interrupts so that QCOM PCIe RC driver can make use of it to get events such as PCIe link specific events, safety events, etc. Signed-off-by: Qiang Yu --- .../devicetree/bindings/pci/qcom,pcie-x1e80100.yaml | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml = b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml index a9db0a231563..2c0e01fc0ab8 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml @@ -46,8 +46,8 @@ properties: - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock =20 interrupts: - minItems: 8 - maxItems: 8 + minItems: 9 + maxItems: 9 =20 interrupt-names: items: @@ -59,6 +59,7 @@ properties: - const: msi5 - const: msi6 - const: msi7 + - const: global =20 resets: minItems: 1 @@ -130,9 +131,10 @@ examples: , , , - ; + , + ; interrupt-names =3D "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7"; + "msi4", "msi5", "msi6", "msi7", "global"; #interrupt-cells =3D <1>; interrupt-map-mask =3D <0 0 0 0x7>; interrupt-map =3D <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH= >, /* int_a */ --=20 2.34.1