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charset="utf-8" Add DT support for QUPV3 Serial Engines. Co-developed-by: Mukesh Kumar Savaliya Signed-off-by: Mukesh Kumar Savaliya Signed-off-by: Viken Dadhaniya --- Build Dependencies: Base Link: https://lore.kernel.org/linux-arm-msm/20240904-qcs8300_initial_dtsi-v1-18-d= 0ea9afdc007@quicinc.com/ https://lore.kernel.org/all/202409080715.rGuyyNu2-lkp@intel.com/T/ GCC Link: https://lore.kernel.org/all/20240820-qcs8300-gcc-v1-0-d81720517a8= 2@quicinc.com/ ICC Link: https://lore.kernel.org/linux-arm-msm/20240906151534.6418-2-quic_= rlaggysh@quicinc.com/ --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 2077 +++++++++++++++++++++++-- 1 file changed, 1932 insertions(+), 145 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qc= om/qcs8300.dtsi index 2c35f96c3f28..ab9c9dc61a4f 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -5,6 +5,7 @@ =20 #include #include +#include #include #include #include @@ -18,6 +19,39 @@ #address-cells =3D <2>; #size-cells =3D <2>; =20 + aliases { + i2c0 =3D &i2c0; + i2c1 =3D &i2c1; + i2c2 =3D &i2c2; + i2c3 =3D &i2c3; + i2c4 =3D &i2c4; + i2c5 =3D &i2c5; + i2c6 =3D &i2c6; + i2c8 =3D &i2c8; + i2c9 =3D &i2c9; + i2c10 =3D &i2c10; + i2c11 =3D &i2c11; + i2c12 =3D &i2c12; + i2c13 =3D &i2c13; + i2c14 =3D &i2c14; + i2c15 =3D &i2c15; + spi0 =3D &spi0; + spi1 =3D &spi1; + spi2 =3D &spi2; + spi3 =3D &spi3; + spi4 =3D &spi4; + spi5 =3D &spi5; + spi6 =3D &spi6; + spi8 =3D &spi8; + spi9 =3D &spi9; + spi10 =3D &spi10; + spi12 =3D &spi12; + spi13 =3D &spi13; + spi14 =3D &spi14; + spi15 =3D &spi15; + serial0 =3D &uart7; + }; + cpus { #address-cells =3D <2>; #size-cells =3D <0>; @@ -372,6 +406,15 @@ }; }; =20 + qup_opp_table: opp-table-qup { + compatible =3D "operating-points-v2"; + + opp-120000000 { + opp-hz =3D /bits/ 64 <120000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + reserved-memory { #address-cells =3D <2>; #size-cells =3D <2>; @@ -558,6 +601,29 @@ #size-cells =3D <1>; }; =20 + gpi_dma0: qcom,gpi-dma@900000 { + compatible =3D "qcom,sm6350-gpi-dma"; + #dma-cells =3D <3>; + reg =3D <0x0 0x900000 0x0 0x60000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + iommus =3D <&apps_smmu 0x416 0x0>; + dma-channels =3D <12>; + dma-channel-mask =3D <0xfff>; + dma-coherent; + status =3D "disabled"; + }; + qupv3_id_0: geniqup@9c0000 { compatible =3D "qcom,geni-se-qup"; reg =3D <0x0 0x9c0000 0x0 0x2000>; @@ -568,175 +634,1277 @@ "s-ahb"; #address-cells =3D <2>; #size-cells =3D <2>; + iommus =3D <&apps_smmu 0x403 0x0>; + dma-coherent; status =3D "disabled"; =20 - uart7: serial@99c000 { - compatible =3D "qcom,geni-debug-uart"; - reg =3D <0x0 0x0099c000 0x0 0x4000>; - clocks =3D <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + i2c0: i2c@980000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x980000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S0_CLK>; clock-names =3D "se"; - pinctrl-0 =3D <&qup_uart7_default>; + pinctrl-0 =3D <&qup_i2c0_data_clk>; pinctrl-names =3D "default"; - interrupts =3D ; - interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 - &clk_virt SLAVE_QUP_CORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 - &config_noc SLAVE_QUP_0 0>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", - "qup-config"; + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; status =3D "disabled"; }; - }; =20 - config_noc: interconnect@14c0000 { - compatible =3D "qcom,qcs8300-config-noc"; - reg =3D <0x0 0x014c0000 0x0 0x13080>; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; + spi0: spi@980000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x980000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi0_data_clk>, <&qup_spi0_cs>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + dmas =3D <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; =20 - system_noc: interconnect@1680000 { - compatible =3D "qcom,qcs8300-system-noc"; - reg =3D <0x0 0x01680000 0x0 0x15080>; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; + uart0: serial@980000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x980000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart0_cts>, <&qup_uart0_rts>, + <&qup_uart0_tx>, <&qup_uart0_rx>; + pinctrl-names =3D "default"; + interrupts =3D ; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + status =3D "disabled"; + }; =20 - aggre1_noc: interconnect@16c0000 { - compatible =3D "qcom,qcs8300-aggre1-noc"; - reg =3D <0x0 0x016c0000 0x0 0x17080>; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; + i2c1: i2c@984000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x984000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c1_data_clk>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; =20 - aggre2_noc: interconnect@1700000 { - compatible =3D "qcom,qcs8300-aggre2-noc"; - reg =3D <0x0 0x01700000 0x0 0x1a080>; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; + spi1: spi@984000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x984000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi1_data_clk>, <&qup_spi1_cs>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + dmas =3D <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; =20 - pcie_anoc: interconnect@1760000 { - compatible =3D "qcom,qcs8300-pcie-anoc"; - reg =3D <0x0 0x01760000 0x0 0xc080>; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; + uart1: serial@984000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x984000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart1_cts>, <&qup_uart1_rts>, + <&qup_uart1_tx>, <&qup_uart1_rx>; + pinctrl-names =3D "default"; + interrupts =3D ; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + status =3D "disabled"; + }; =20 - gpdsp_anoc: interconnect@1780000 { - compatible =3D "qcom,qcs8300-gpdsp-anoc"; - reg =3D <0x0 0x01780000 0x0 0xd080>; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; + i2c2: i2c@988000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x988000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c2_data_clk>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; =20 - mmss_noc: interconnect@17a0000 { - compatible =3D "qcom,qcs8300-mmss-noc"; - reg =3D <0x0 0x017a0000 0x0 0x40000>; - #interconnect-cells =3D <2>; - qcom,bcm-voters =3D <&apps_bcm_voter>; - }; + spi2: spi@988000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x988000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi2_data_clk>, <&qup_spi2_cs>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + dmas =3D <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; =20 - ufs_mem_hc: ufs@1d84000 { - compatible =3D "qcom,qcs8300-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg =3D <0x0 0x01d84000 0x0 0x3000>; - interrupts =3D ; - phys =3D <&ufs_mem_phy>; - phy-names =3D "ufsphy"; - lanes-per-direction =3D <2>; - #reset-cells =3D <1>; - resets =3D <&gcc GCC_UFS_PHY_BCR>; - reset-names =3D "rst"; + uart2: serial@988000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x988000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart2_cts>, <&qup_uart2_rts>, + <&qup_uart2_tx>, <&qup_uart2_rx>; + pinctrl-names =3D "default"; + interrupts =3D ; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + status =3D "disabled"; + }; =20 - power-domains =3D <&gcc GCC_UFS_PHY_GDSC>; - required-opps =3D <&rpmhpd_opp_nom>; + i2c3: i2c@98c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x98c000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c3_data_clk>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; =20 - iommus =3D <&apps_smmu 0x100 0x0>; - dma-coherent; + spi3: spi@98c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x98c000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi3_data_clk>, <&qup_spi3_cs>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + dmas =3D <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; =20 - interconnects =3D <&aggre1_noc MASTER_UFS_MEM 0 - &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 - &config_noc SLAVE_UFS_MEM_CFG 0>; - interconnect-names =3D "ufs-ddr", - "cpu-ufs"; + uart3: serial@98c000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x98c000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart3_cts>, <&qup_uart3_rts>, + <&qup_uart3_tx>, <&qup_uart3_rx>; + pinctrl-names =3D "default"; + interrupts =3D ; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + status =3D "disabled"; + }; =20 - clocks =3D <&gcc GCC_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>, - <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; - clock-names =3D "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; - freq-table-hz =3D <75000000 300000000>, - <0 0>, - <0 0>, - <75000000 300000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>; - status =3D "disabled"; - }; + i2c4: i2c@990000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x990000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c4_data_clk>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; =20 - ufs_mem_phy: phy@1d87000 { - compatible =3D "qcom,qcs8300-qmp-ufs-phy", "qcom,sa8775p-qmp-ufs-phy"; - reg =3D <0x0 0x01d87000 0x0 0xe10>; - /* - * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It - * enables the CXO clock to eDP *and* UFS PHY. - */ - clocks =3D <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, - <&gcc GCC_EDP_REF_CLKREF_EN>; - clock-names =3D "ref", - "ref_aux", - "qref"; - power-domains =3D <&gcc GCC_UFS_PHY_GDSC>; + spi4: spi@990000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x990000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi4_data_clk>, <&qup_spi4_cs>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + dmas =3D <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; =20 - resets =3D <&ufs_mem_hc 0>; - reset-names =3D "ufsphy"; + uart4: serial@990000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x990000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart4_cts>, <&qup_uart4_rts>, + <&qup_uart4_tx>, <&qup_uart4_rx>; + pinctrl-names =3D "default"; + interrupts =3D ; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + status =3D "disabled"; + }; =20 - #phy-cells =3D <0>; - status =3D "disabled"; - }; + i2c5: i2c@994000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x994000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c5_data_clk>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; =20 - tcsr_mutex: hwlock@1f40000 { - compatible =3D "qcom,tcsr-mutex"; - reg =3D <0x0 0x01f40000 0x0 0x20000>; - #hwlock-cells =3D <1>; - }; + spi5: spi@994000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x994000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi5_data_clk>, <&qup_spi5_cs>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + dmas =3D <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; =20 - tcsr: syscon@1fc0000 { - compatible =3D "qcom,qcs8300-tcsr", "syscon"; - reg =3D <0x0 0x1fc0000 0x0 0x30000>; - }; + uart5: serial@994000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x994000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart5_cts>, <&qup_uart5_rts>, + <&qup_uart5_tx>, <&qup_uart5_rx>; + pinctrl-names =3D "default"; + interrupts =3D ; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + status =3D "disabled"; + }; =20 - remoteproc_adsp: remoteproc@3000000 { - compatible =3D "qcom,qcs8300-adsp-pas", "qcom,sa8775p-adsp-pas"; - reg =3D <0x0 0x3000000 0x0 0x00100>; + i2c6: i2c@998000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x998000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c6_data_clk>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma0 0 6 QCOM_GPI_I2C>, + <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; =20 - interrupts-extended =3D <&pdc 6 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names =3D "wdog", - "fatal", - "ready", - "handover", - "stop-ack"; + spi6: spi@998000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x998000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi6_data_clk>, <&qup_spi6_cs>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + dmas =3D <&gpi_dma0 0 6 QCOM_GPI_SPI>, + <&gpi_dma0 1 6 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; =20 - clocks =3D <&rpmhcc RPMH_CXO_CLK>; + uart6: serial@998000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x998000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart6_cts>, <&qup_uart6_rts>, + <&qup_uart6_tx>, <&qup_uart6_rx>; + pinctrl-names =3D "default"; + interrupts =3D ; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + status =3D "disabled"; + }; + + uart7: serial@99c000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0x0 0x0099c000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart7_tx>, <&qup_uart7_rx>; + pinctrl-names =3D "default"; + interrupts =3D ; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + status =3D "disabled"; + }; + }; + + gpi_dma1: qcom,gpi-dma@a00000 { + compatible =3D "qcom,sm6350-gpi-dma"; + reg =3D <0x0 0xa00000 0x0 0x60000>; + #dma-cells =3D <3>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + iommus =3D <&apps_smmu 0x456 0x0>; + dma-channels =3D <12>; + dma-channel-mask =3D <0xfff>; + dma-coherent; + status =3D "disabled"; + }; + + qupv3_id_1: geniqup@ac0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0xac0000 0x0 0x2000>; + ranges; + clocks =3D <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names =3D "m-ahb", + "s-ahb"; + #address-cells =3D <2>; + #size-cells =3D <2>; + iommus =3D <&apps_smmu 0x443 0x0>; + dma-coherent; + status =3D "disabled"; + + i2c8: i2c@a80000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0xa80000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c8_data_clk>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; + + spi8: spi@a80000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0xa80000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi8_data_clk>, <&qup_spi8_cs>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + dmas =3D <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; + + uart8: serial@a80000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0xa80000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart8_cts>, <&qup_uart8_rts>, + <&qup_uart8_tx>, <&qup_uart8_rx>; + pinctrl-names =3D "default"; + interrupts =3D ; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + status =3D "disabled"; + }; + + i2c9: i2c@a84000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0xa84000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c9_data_clk>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; + + spi9: spi@a84000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0xa84000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi9_data_clk>, <&qup_spi9_cs>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + dmas =3D <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; + + uart9: serial@a84000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0xa84000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart9_cts>, <&qup_uart9_rts>, + <&qup_uart9_tx>, <&qup_uart9_rx>; + pinctrl-names =3D "default"; + interrupts =3D ; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + status =3D "disabled"; + }; + + i2c10: i2c@a88000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0xa88000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c10_data_clk>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; + + spi10: spi@a88000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0xa88000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi10_data_clk>, <&qup_spi10_cs>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + dmas =3D <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; + + uart10: serial@a88000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0xa88000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart10_cts>, <&qup_uart10_rts>, + <&qup_uart10_tx>, <&qup_uart10_rx>; + pinctrl-names =3D "default"; + interrupts =3D ; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + status =3D "disabled"; + }; + + i2c11: i2c@a8c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0xa8c000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c11_data_clk>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; + + uart11: serial@a8c000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0xa8c000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart11_tx>, <&qup_uart11_rx>; + pinctrl-names =3D "default"; + interrupts =3D ; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + status =3D "disabled"; + }; + + i2c12: i2c@a90000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0xa90000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c12_data_clk>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; + + spi12: spi@a90000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0xa90000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi12_data_clk>, <&qup_spi12_cs>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + dmas =3D <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; + + uart12: serial@a90000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0xa90000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart12_cts>, <&qup_uart12_rts>, + <&qup_uart12_tx>, <&qup_uart12_rx>; + pinctrl-names =3D "default"; + interrupts =3D ; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + status =3D "disabled"; + }; + + i2c13: i2c@a94000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0xa94000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c13_data_clk>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; + + spi13: spi@a94000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0xa94000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi13_data_clk>, <&qup_spi13_cs>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + dmas =3D <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; + + uart13: serial@a94000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0xa94000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart13_cts>, <&qup_uart13_rts>, + <&qup_uart13_tx>, <&qup_uart13_rx>; + pinctrl-names =3D "default"; + interrupts =3D ; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + status =3D "disabled"; + }; + + i2c14: i2c@a98000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0xa98000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c14_data_clk>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; + + spi14: spi@a98000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0xa98000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi14_data_clk>, <&qup_spi14_cs>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + dmas =3D <&gpi_dma1 0 6 QCOM_GPI_SPI>, + <&gpi_dma1 1 6 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; + + uart14: serial@a98000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0xa98000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart14_cts>, <&qup_uart14_rts>, + <&qup_uart14_tx>, <&qup_uart14_rx>; + pinctrl-names =3D "default"; + interrupts =3D ; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + status =3D "disabled"; + }; + + i2c15: i2c@a9c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0xa9c000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c15_data_clk>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma1 0 7 QCOM_GPI_I2C>, + <&gpi_dma1 1 7 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; + + spi15: spi@a9c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0xa9c000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi15_data_clk>, <&qup_spi15_cs>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + dmas =3D <&gpi_dma1 0 7 QCOM_GPI_SPI>, + <&gpi_dma1 1 7 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; + + uart15: serial@a9c000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0xa9c000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart15_cts>, <&qup_uart15_rts>, + <&qup_uart15_tx>, <&qup_uart15_rx>; + pinctrl-names =3D "default"; + interrupts =3D ; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + status =3D "disabled"; + }; + }; + + gpi_dma3: qcom,gpi-dma@b00000 { + compatible =3D "qcom,sm6350-gpi-dma"; + reg =3D <0x0 0xb00000 0x0 0x60000>; + #dma-cells =3D <3>; + interrupts =3D , + , + , + ; + iommus =3D <&apps_smmu 0x56 0x0>; + dma-channels =3D <4>; + dma-channel-mask =3D <0xf>; + dma-coherent; + status =3D "disabled"; + }; + + qupv3_id_3: geniqup@bc0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0xbc0000 0x0 0x2000>; + ranges; + clocks =3D <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; + clock-names =3D "m-ahb", + "s-ahb"; + #address-cells =3D <2>; + #size-cells =3D <2>; + iommus =3D <&apps_smmu 0x43 0x0>; + dma-coherent; + status =3D "disabled"; + + i2c16: i2c@b80000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0xb80000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP3_S0_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c16_data_clk>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 0 &clk_virt SLAVE_QUP_C= ORE_3 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_3 0>, + <&aggre2_noc MASTER_QUP_3 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + dmas =3D <&gpi_dma3 0 0 QCOM_GPI_I2C>, + <&gpi_dma3 1 0 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; + + spi16: spi@b80000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0xb80000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP3_S0_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi16_data_clk>, <&qup_spi16_cs>; + pinctrl-names =3D "default"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 0 &clk_virt SLAVE_QUP_C= ORE_3 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_3 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + dmas =3D <&gpi_dma3 0 0 QCOM_GPI_SPI>, + <&gpi_dma3 1 0 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; + }; + + uart16: serial@b80000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0xb80000 0x0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP3_S0_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart16_cts>, <&qup_uart16_rts>, + <&qup_uart16_tx>, <&qup_uart16_rx>; + pinctrl-names =3D "default"; + interrupts =3D ; + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 0 &clk_virt SLAVE_QUP_C= ORE_3 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_3 0>; + interconnect-names =3D "qup-core", + "qup-config"; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&qup_opp_table>; + status =3D "disabled"; + }; + }; + + config_noc: interconnect@14c0000 { + compatible =3D "qcom,qcs8300-config-noc"; + reg =3D <0x0 0x014c0000 0x0 0x13080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + system_noc: interconnect@1680000 { + compatible =3D "qcom,qcs8300-system-noc"; + reg =3D <0x0 0x01680000 0x0 0x15080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16c0000 { + compatible =3D "qcom,qcs8300-aggre1-noc"; + reg =3D <0x0 0x016c0000 0x0 0x17080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible =3D "qcom,qcs8300-aggre2-noc"; + reg =3D <0x0 0x01700000 0x0 0x1a080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + pcie_anoc: interconnect@1760000 { + compatible =3D "qcom,qcs8300-pcie-anoc"; + reg =3D <0x0 0x01760000 0x0 0xc080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + gpdsp_anoc: interconnect@1780000 { + compatible =3D "qcom,qcs8300-gpdsp-anoc"; + reg =3D <0x0 0x01780000 0x0 0xd080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@17a0000 { + compatible =3D "qcom,qcs8300-mmss-noc"; + reg =3D <0x0 0x017a0000 0x0 0x40000>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + ufs_mem_hc: ufs@1d84000 { + compatible =3D "qcom,qcs8300-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; + reg =3D <0x0 0x01d84000 0x0 0x3000>; + interrupts =3D ; + phys =3D <&ufs_mem_phy>; + phy-names =3D "ufsphy"; + lanes-per-direction =3D <2>; + #reset-cells =3D <1>; + resets =3D <&gcc GCC_UFS_PHY_BCR>; + reset-names =3D "rst"; + + power-domains =3D <&gcc GCC_UFS_PHY_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; + + iommus =3D <&apps_smmu 0x100 0x0>; + dma-coherent; + + interconnects =3D <&aggre1_noc MASTER_UFS_MEM 0 + &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 + &config_noc SLAVE_UFS_MEM_CFG 0>; + interconnect-names =3D "ufs-ddr", + "cpu-ufs"; + + clocks =3D <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names =3D "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + freq-table-hz =3D <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + status =3D "disabled"; + }; + + ufs_mem_phy: phy@1d87000 { + compatible =3D "qcom,qcs8300-qmp-ufs-phy", "qcom,sa8775p-qmp-ufs-phy"; + reg =3D <0x0 0x01d87000 0x0 0xe10>; + /* + * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It + * enables the CXO clock to eDP *and* UFS PHY. + */ + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; + clock-names =3D "ref", + "ref_aux", + "qref"; + power-domains =3D <&gcc GCC_UFS_PHY_GDSC>; + + resets =3D <&ufs_mem_hc 0>; + reset-names =3D "ufsphy"; + + #phy-cells =3D <0>; + status =3D "disabled"; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x0 0x01f40000 0x0 0x20000>; + #hwlock-cells =3D <1>; + }; + + tcsr: syscon@1fc0000 { + compatible =3D "qcom,qcs8300-tcsr", "syscon"; + reg =3D <0x0 0x1fc0000 0x0 0x30000>; + }; + + remoteproc_adsp: remoteproc@3000000 { + compatible =3D "qcom,qcs8300-adsp-pas", "qcom,sa8775p-adsp-pas"; + reg =3D <0x0 0x3000000 0x0 0x00100>; + + interrupts-extended =3D <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; clock-names =3D "xo"; =20 power-domains =3D <&rpmhpd RPMHPD_LCX>, @@ -950,11 +2118,630 @@ #interrupt-cells =3D <2>; wakeup-parent =3D <&pdc>; =20 - qup_uart7_default: qup-uart7-state { - /* TX, RX */ - pins =3D "gpio43", "gpio44"; + qup_i2c0_data_clk: qup-i2c0-data-clk-state { + pins =3D "gpio17", "gpio18"; + function =3D "qup0_se0"; + }; + + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + pins =3D "gpio19", "gpio20"; + function =3D "qup0_se1"; + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk-state { + pins =3D "gpio33", "gpio34"; + function =3D "qup0_se2"; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + pins =3D "gpio25", "gpio26"; + function =3D "qup0_se3"; + }; + + qup_i2c4_data_clk: qup-i2c4-data-clk-state { + pins =3D "gpio29", "gpio30"; + function =3D "qup0_se4"; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk-state { + pins =3D "gpio21", "gpio22"; + function =3D "qup0_se5"; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk-state { + pins =3D "gpio80", "gpio81"; + function =3D "qup0_se6"; + }; + + qup_i2c8_data_clk: qup-i2c8-data-clk-state { + pins =3D "gpio37", "gpio38"; + function =3D "qup1_se0"; + }; + + qup_i2c9_data_clk: qup-i2c9-data-clk-state { + pins =3D "gpio39", "gpio40"; + function =3D "qup1_se1"; + }; + + qup_i2c10_data_clk: qup-i2c10-data-clk-state { + pins =3D "gpio84", "gpio85"; + function =3D "qup1_se2"; + }; + + qup_i2c11_data_clk: qup-i2c11-data-clk-state { + pins =3D "gpio41", "gpio42"; + function =3D "qup1_se3"; + }; + + qup_i2c12_data_clk: qup-i2c12-data-clk-state { + pins =3D "gpio45", "gpio46"; + function =3D "qup1_se4"; + }; + + qup_i2c13_data_clk: qup-i2c13-data-clk-state { + pins =3D "gpio49", "gpio50"; + function =3D "qup1_se5"; + }; + + qup_i2c14_data_clk: qup-i2c14-data-clk-state { + pins =3D "gpio89", "gpio90"; + function =3D "qup1_se6"; + }; + + qup_i2c15_data_clk: qup-i2c15-data-clk-state { + pins =3D "gpio91", "gpio92"; + function =3D "qup1_se7"; + }; + + qup_i2c16_data_clk: qup-i2c16-data-clk-state { + pins =3D "gpio10", "gpio11"; + function =3D "qup2_se0"; + }; + + qup_spi0_data_clk: qup-spi0-data-clk-state { + pins =3D "gpio17", "gpio18", "gpio19"; + function =3D "qup0_se0"; + }; + + qup_spi0_cs: qup-spi0-cs-state { + pins =3D "gpio20"; + function =3D "qup0_se0"; + }; + + qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { + pins =3D "gpio20"; + function =3D "gpio"; + }; + + qup_spi1_data_clk: qup-spi1-data-clk-state { + pins =3D "gpio19", "gpio20", "gpio17"; + function =3D "qup0_se1"; + }; + + qup_spi1_cs: qup-spi1-cs-state { + pins =3D "gpio18"; + function =3D "qup0_se1"; + }; + + qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { + pins =3D "gpio18"; + function =3D "gpio"; + }; + + qup_spi2_data_clk: qup-spi2-data-clk-state { + pins =3D "gpio33", "gpio34", "gpio35"; + function =3D "qup0_se2"; + }; + + qup_spi2_cs: qup-spi2-cs-state { + pins =3D "gpio36"; + function =3D "qup0_se2"; + }; + + qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { + pins =3D "gpio36"; + function =3D "gpio"; + }; + + qup_spi3_data_clk: qup-spi3-data-clk-state { + pins =3D "gpio25", "gpio26", "gpio27"; + function =3D "qup0_se3"; + }; + + qup_spi3_cs: qup-spi3-cs-state { + pins =3D "gpio28"; + function =3D "qup0_se3"; + }; + + qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { + pins =3D "gpio28"; + function =3D "gpio"; + }; + + qup_spi4_data_clk: qup-spi4-data-clk-state { + pins =3D "gpio29", "gpio30", "gpio31"; + function =3D "qup0_se4"; + }; + + qup_spi4_cs: qup-spi4-cs-state { + pins =3D "gpio32"; + function =3D "qup0_se4"; + }; + + qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { + pins =3D "gpio32"; + function =3D "gpio"; + }; + + qup_spi5_data_clk: qup-spi5-data-clk-state { + pins =3D "gpio21", "gpio22", "gpio23"; + function =3D "qup0_se5"; + }; + + qup_spi5_cs: qup-spi5-cs-state { + pins =3D "gpio24"; + function =3D "qup0_se5"; + }; + + qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { + pins =3D "gpio24"; + function =3D "gpio"; + }; + + qup_spi6_data_clk: qup-spi6-data-clk-state { + pins =3D "gpio80", "gpio81", "gpio82"; + function =3D "qup0_se6"; + }; + + qup_spi6_cs: qup-spi6-cs-state { + pins =3D "gpio83"; + function =3D "qup0_se6"; + }; + + qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { + pins =3D "gpio83"; + function =3D "gpio"; + }; + + qup_spi8_data_clk: qup-spi8-data-clk-state { + pins =3D "gpio37", "gpio38", "gpio39"; + function =3D "qup1_se0"; + }; + + qup_spi8_cs: qup-spi8-cs-state { + pins =3D "gpio40"; + function =3D "qup1_se0"; + }; + + qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { + pins =3D "gpio40"; + function =3D "gpio"; + }; + + qup_spi9_data_clk: qup-spi9-data-clk-state { + pins =3D "gpio39", "gpio40", "gpio37"; + function =3D "qup1_se1"; + }; + + qup_spi9_cs: qup-spi9-cs-state { + pins =3D "gpio38"; + function =3D "qup1_se1"; + }; + + qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { + pins =3D "gpio38"; + function =3D "gpio"; + }; + + qup_spi10_data_clk: qup-spi10-data-clk-state { + pins =3D "gpio84", "gpio85", "gpio86"; + function =3D "qup1_se2"; + }; + + qup_spi10_cs: qup-spi10-cs-state { + pins =3D "gpio87"; + function =3D "qup1_se2"; + }; + + qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { + pins =3D "gpio87"; + function =3D "gpio"; + }; + + qup_spi12_data_clk: qup-spi12-data-clk-state { + pins =3D "gpio45", "gpio46", "gpio47"; + function =3D "qup1_se4"; + }; + + qup_spi12_cs: qup-spi12-cs-state { + pins =3D "gpio48"; + function =3D "qup1_se4"; + }; + + qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { + pins =3D "gpio48"; + function =3D "gpio"; + }; + + qup_spi13_data_clk: qup-spi13-data-clk-state { + pins =3D "gpio49", "gpio50", "gpio51"; + function =3D "qup1_se5"; + }; + + qup_spi13_cs: qup-spi13-cs-state { + pins =3D "gpio52"; + function =3D "qup1_se5"; + }; + + qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { + pins =3D "gpio52"; + function =3D "gpio"; + }; + + qup_spi14_data_clk: qup-spi14-data-clk-state { + pins =3D "gpio89", "gpio90", "gpio91"; + function =3D "qup1_se6"; + }; + + qup_spi14_cs: qup-spi14-cs-state { + pins =3D "gpio92"; + function =3D "qup1_se6"; + }; + + qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { + pins =3D "gpio92"; + function =3D "gpio"; + }; + + qup_spi15_data_clk: qup-spi15-data-clk-state { + pins =3D "gpio91", "gpio92", "gpio89"; + function =3D "qup1_se7"; + }; + + qup_spi15_cs: qup-spi15-cs-state { + pins =3D "gpio90"; + function =3D "qup1_se7"; + }; + + qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { + pins =3D "gpio90"; + function =3D "gpio"; + }; + + qup_spi16_data_clk: qup-spi16-data-clk-state { + pins =3D "gpio10", "gpio11", "gpio12"; + function =3D "qup2_se0"; + }; + + qup_spi16_cs: qup-spi16-cs-state { + pins =3D "gpio13"; + function =3D "qup2_se0"; + }; + + qup_spi16_cs_gpio: qup-spi16-cs-gpio-state { + pins =3D "gpio13"; + function =3D "gpio"; + }; + + qup_uart0_cts: qup-uart0-cts-state { + pins =3D "gpio17"; + function =3D "qup0_se0"; + }; + + qup_uart0_rts: qup-uart0-rts-state { + pins =3D "gpio18"; + function =3D "qup0_se0"; + }; + + qup_uart0_tx: qup-uart0-tx-state { + pins =3D "gpio19"; + function =3D "qup0_se0"; + }; + + qup_uart0_rx: qup-uart0-rx-state { + pins =3D "gpio20"; + function =3D "qup0_se0"; + }; + + qup_uart1_cts: qup-uart1-cts-state { + pins =3D "gpio19"; + function =3D "qup0_se1"; + }; + + qup_uart1_rts: qup-uart1-rts-state { + pins =3D "gpio20"; + function =3D "qup0_se1"; + }; + + qup_uart1_tx: qup-uart1-tx-state { + pins =3D "gpio17"; + function =3D "qup0_se1"; + }; + + qup_uart1_rx: qup-uart1-rx-state { + pins =3D "gpio18"; + function =3D "qup0_se1"; + }; + + qup_uart2_cts: qup-uart2-cts-state { + pins =3D "gpio33"; + function =3D "qup0_se2"; + }; + + qup_uart2_rts: qup-uart2-rts-state { + pins =3D "gpio34"; + function =3D "qup0_se2"; + }; + + qup_uart2_tx: qup-uart2-tx-state { + pins =3D "gpio35"; + function =3D "qup0_se2"; + }; + + qup_uart2_rx: qup-uart2-rx-state { + pins =3D "gpio36"; + function =3D "qup0_se2"; + }; + + qup_uart3_cts: qup-uart3-cts-state { + pins =3D "gpio25"; + function =3D "qup0_se3"; + }; + + qup_uart3_rts: qup-uart3-rts-state { + pins =3D "gpio26"; + function =3D "qup0_se3"; + }; + + qup_uart3_tx: qup-uart3-tx-state { + pins =3D "gpio27"; + function =3D "qup0_se3"; + }; + + qup_uart3_rx: qup-uart3-rx-state { + pins =3D "gpio28"; + function =3D "qup0_se3"; + }; + + qup_uart4_cts: qup-uart4-cts-state { + pins =3D "gpio29"; + function =3D "qup0_se4"; + }; + + qup_uart4_rts: qup-uart4-rts-state { + pins =3D "gpio30"; + function =3D "qup0_se4"; + }; + + qup_uart4_tx: qup-uart4-tx-state { + pins =3D "gpio31"; + function =3D "qup0_se4"; + }; + + qup_uart4_rx: qup-uart4-rx-state { + pins =3D "gpio32"; + function =3D "qup0_se4"; + }; + + qup_uart5_cts: qup-uart5-cts-state { + pins =3D "gpio21"; + function =3D "qup0_se5"; + }; + + qup_uart5_rts: qup-uart5-rts-state { + pins =3D "gpio22"; + function =3D "qup0_se5"; + }; + + qup_uart5_tx: qup-uart5-tx-state { + pins =3D "gpio23"; + function =3D "qup0_se5"; + }; + + qup_uart5_rx: qup-uart5-rx-state { + pins =3D "gpio23"; + function =3D "qup0_se5"; + }; + + qup_uart6_cts: qup-uart6-cts-state { + pins =3D "gpio80"; + function =3D "qup0_se6"; + }; + + qup_uart6_rts: qup-uart6-rts-state { + pins =3D "gpio81"; + function =3D "qup0_se6"; + }; + + qup_uart6_tx: qup-uart6-tx-state { + pins =3D "gpio82"; + function =3D "qup0_se6"; + }; + + qup_uart6_rx: qup-uart6-rx-state { + pins =3D "gpio83"; + function =3D "qup0_se6"; + }; + + qup_uart7_tx: qup-uart7-tx-state { + pins =3D "gpio43"; + function =3D "qup0_se7"; + }; + + qup_uart7_rx: qup-uart7-rx-state { + pins =3D "gpio44"; function =3D "qup0_se7"; }; + + qup_uart8_cts: qup-uart8-cts-state { + pins =3D "gpio37"; + function =3D "qup1_se0"; + }; + + qup_uart8_rts: qup-uart8-rts-state { + pins =3D "gpio38"; + function =3D "qup1_se0"; + }; + + qup_uart8_tx: qup-uart8-tx-state { + pins =3D "gpio39"; + function =3D "qup1_se0"; + }; + + qup_uart8_rx: qup-uart8-rx-state { + pins =3D "gpio40"; + function =3D "qup1_se0"; + }; + + qup_uart9_cts: qup-uart9-cts-state { + pins =3D "gpio39"; + function =3D "qup1_se1"; + }; + + qup_uart9_rts: qup-uart9-rts-state { + pins =3D "gpio40"; + function =3D "qup1_se1"; + }; + + qup_uart9_tx: qup-uart9-tx-state { + pins =3D "gpio37"; + function =3D "qup1_se1"; + }; + + qup_uart9_rx: qup-uart9-rx-state { + pins =3D "gpio38"; + function =3D "qup1_se1"; + }; + + qup_uart10_cts: qup-uart10-cts-state { + pins =3D "gpio84"; + function =3D "qup1_se2"; + }; + + qup_uart10_rts: qup-uart10-rts-state { + pins =3D "gpio84"; + function =3D "qup1_se2"; + }; + + qup_uart10_tx: qup-uart10-tx-state { + pins =3D "gpio85"; + function =3D "qup1_se2"; + }; + + qup_uart10_rx: qup-uart10-rx-state { + pins =3D "gpio87"; + function =3D "qup1_se2"; + }; + + qup_uart11_tx: qup-uart11-tx-state { + pins =3D "gpio41"; + function =3D "qup1_se3"; + }; + + qup_uart11_rx: qup-uart11-rx-state { + pins =3D "gpio42"; + function =3D "qup1_se3"; + }; + + qup_uart12_cts: qup-uart12-cts-state { + pins =3D "gpio45"; + function =3D "qup1_se4"; + }; + + qup_uart12_rts: qup-uart12-rts-state { + pins =3D "gpio46"; + function =3D "qup1_se4"; + }; + + qup_uart12_tx: qup-uart12-tx-state { + pins =3D "gpio47"; + function =3D "qup1_se4"; + }; + + qup_uart12_rx: qup-uart12-rx-state { + pins =3D "gpio48"; + function =3D "qup1_se4"; + }; + + qup_uart13_cts: qup-uart13-cts-state { + pins =3D "gpio49"; + function =3D "qup1_se5"; + }; + + qup_uart13_rts: qup-uart13-rts-state { + pins =3D "gpio50"; + function =3D "qup1_se5"; + }; + + qup_uart13_tx: qup-uart13-tx-state { + pins =3D "gpio51"; + function =3D "qup1_se5"; + }; + + qup_uart13_rx: qup-uart13-rx-state { + pins =3D "gpio52"; + function =3D "qup1_se5"; + }; + + qup_uart14_cts: qup-uart14-cts-state { + pins =3D "gpio89"; + function =3D "qup1_se6"; + }; + + qup_uart14_rts: qup-uart14-rts-state { + pins =3D "gpio90"; + function =3D "qup1_se6"; + }; + + qup_uart14_tx: qup-uart14-tx-state { + pins =3D "gpio91"; + function =3D "qup1_se6"; + }; + + qup_uart14_rx: qup-uart14-rx-state { + pins =3D "gpio92"; + function =3D "qup1_se6"; + }; + + qup_uart15_cts: qup-uart15-cts-state { + pins =3D "gpio91"; + function =3D "qup1_se7"; + }; + + qup_uart15_rts: qup-uart15-rts-state { + pins =3D "gpio92"; + function =3D "qup1_se7"; + }; + + qup_uart15_tx: qup-uart15-tx-state { + pins =3D "gpio89"; + function =3D "qup1_se7"; + }; + + qup_uart15_rx: qup-uart15-rx-state { + pins =3D "gpio90"; + function =3D "qup1_se7"; + }; + + qup_uart16_cts: qup-uart16-cts-state { + pins =3D "gpio10"; + function =3D "qup2_se0"; + }; + + qup_uart16_rts: qup-uart16-rts-state { + pins =3D "gpio11"; + function =3D "qup2_se0"; + }; + + qup_uart16_tx: qup-uart16-tx-state { + pins =3D "gpio12"; + function =3D "qup2_se0"; + }; + + qup_uart16_rx: qup-uart16-rx-state { + pins =3D "gpio13"; + function =3D "qup2_se0"; + }; }; =20 sram: sram@146d8000 { --=20 2.17.1