From nobody Wed Nov 27 17:45:45 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E66DF150997 for ; Wed, 9 Oct 2024 03:46:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728445618; cv=none; b=Av2m8vTeWsdZU1j9JSYLrNYsyZMDtLBUoa7R4VuWVNdD3tB8x/hwTtcyILb4jWdBQJecGbU2Gn59y1+XNWgJkRtF1srGlj74HQA50ORLWo4mTGbhP0DrXcbJ6c9WqqE5TJyTCpHoUxC/Zj7Dc+Jr4PBqkriFPaZITcFKDMB1Kh0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728445618; c=relaxed/simple; bh=3w2tvschrTijM5svhf76ExJt8xal5C0gJlHw2hDd0I8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=LTPjU3yEu3KSYFA/1AfRIqIpPa1N7PYOMeVMRLvYtPXZ+DM04/NItBL4ld8hoW6+GfLyXXrXURel4F8w/auW66hjzb08GNpv2OrdE3Cn9NxJZtBXuewoHw71bCf0QMLh/fwqp0SYk0dozTQSa13EE2veqP3IN5SQc145NI2t2oA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=XSvHia//; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="XSvHia//" X-UUID: 1c96522485f111ef8b96093e013ec31c-20241009 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=jNf8esuPFXdj1SzZwNlUle77CExMPeToTH21H8ouLYo=; b=XSvHia//1WANEiQuyBmFckMe4xBMCnx2qNINMgJwFf4yueMyc2dH2QtLeeqaYXhJbNBn/l7y2hIQyDHd+/BJFxZaXKzPUXRrIn3DLctMv6umpIbvRRQeqPKe8lvx041dtYhK1ansTbGABxzRq0fvnsYjNatfPAmWffA9Yf+KmXQ=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.41,REQID:08fe941d-fd72-4112-b98b-19824cfab9cb,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:6dc6a47,CLOUDID:31c38226-5902-4533-af4f-d0904aa89b3c,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES :1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_ULN,TF_CID_SPAM_SNR X-UUID: 1c96522485f111ef8b96093e013ec31c-20241009 Received: from mtkmbs09n1.mediatek.inc [(172.21.101.35)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 316013556; Wed, 09 Oct 2024 11:46:48 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 9 Oct 2024 11:46:46 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 9 Oct 2024 11:46:46 +0800 From: Jason-JH.Lin To: Adam Thiede , Yassine Oudjana , Chun-Kuang Hu , AngeloGioacchino Del Regno CC: Shawn Sung , Alper Nebi Yasak , , , , , "Jason-JH . Lin" , Singo Chang , "Nancy Lin" , Subject: [PATCH v11 1/5] drm/mediatek: ovl: Fix XRGB format breakage for blend_modes unsupported SoCs Date: Wed, 9 Oct 2024 11:46:42 +0800 Message-ID: <20241009034646.13143-2-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20241009034646.13143-1-jason-jh.lin@mediatek.com> References: <20241009034646.13143-1-jason-jh.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--4.798000-8.000000 X-TMASE-MatchedRID: X679DjmVMOn2fv0LTPfvM4dlc1JaOB1TUAjrAJWsTe/KP6Yywb5aNnv7 Io91rBfwD2EF2wJcjhdx0DfvHApiHUIjaJSsaV6qY1bQMCMvmn6eEP0DdJrullxTR00Ss4P62ft v/5jXki/ZoTly3PGW4GlSWihAdtZ+j2hRzH1UwuAURSScn+QSXt0H8LFZNFG7CKFCmhdu5cUi5y 5vykNUv9NYWU6hQo6nyU+stpPw3NyDgLduq9LPWKW+UzY9s8NAqCsLjdN80t/JgECrPZSGt/5fz FTJ/+DJcVSyL/LZfpwXRoPmWO3jekxwdkPqCq7vDEyN+J8hd+jCS9WgDXVPCp6oP1a0mRIj X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--4.798000-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 8EF844DF62ED7CF5483EBEC09019DF7B7F35AF7A6138F71D1EFF490F66F76CD22000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" OVL_CON_AEN is for alpha blending enable. For the SoC that is supported the blend_modes, OVL_CON_AEN will always enabled to use constant alpha and then use the ignore_pixel_alpha bit to do the alpha blending for XRGB8888 format. Note that ignore pixel alpha bit is not supported if the SoC is not supported the blend_modes. So it will break the original setting of XRGB8888 format for the blend_modes unsupported SoCs, such as MT8173. To fix the downgrade issue, enable alpha blending only when a valid blend_mode or has_alpha is set. Fixes: bc46eb5d5d77 ("drm/mediatek: Support DRM plane alpha in OVL") Signed-off-by: Jason-JH.Lin Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 89b439dcf3a6..047cd1796a51 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -473,8 +473,14 @@ void mtk_ovl_layer_config(struct device *dev, unsigned= int idx, =20 con =3D ovl_fmt_convert(ovl, fmt, blend_mode); if (state->base.fb) { - con |=3D OVL_CON_AEN; con |=3D state->base.alpha & OVL_CON_ALPHA; + + /* + * For blend_modes supported SoCs, always enable alpha blending. + * For blend_modes unsupported SoCs, enable alpha blending when has_alph= a is set. + */ + if (blend_mode || state->base.fb->format->has_alpha) + con |=3D OVL_CON_AEN; } =20 /* CONST_BLD must be enabled for XRGB formats although the alpha channel --=20 2.43.0 From nobody Wed Nov 27 17:45:45 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BCFDD10FF for ; Wed, 9 Oct 2024 03:46:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728445615; cv=none; b=ntWuPT60IX8UufgXTc6oxKWt8kR6Zlpv5boKGiaDPXjgQ5P9UygkzT+aPsVtymR0K0Rjwcm9TrJPCy3OEjI0Ib2i/0gI+8UqhEP338tOSDmWzBatWFL4mwm3b4SVHHoAfooHAfJ+oLqn+FWi20n0l8MP6t+aVO31yX0r3kZnOYA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728445615; c=relaxed/simple; bh=cWUbYayEOXjXIfFfU8pWcE/o8kS4ldo4BvR+pBzKIYU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=EsR9csWzyKD4G/ZqYEKVuk3sANFtHx7ZsBUBUObxNIVPt9UvAXoIORtEDt7km/ZhmG+3q6xb5RUpAxLpmHSvWfkebhV746pJj0xBh2i6usmBFrG7hEG2NnhLTC0RvYbVkAhDSWb72GFJBlWxXe3Qo41WXqlUeMpuxuNeAmPGIVA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=uQKQ8pHw; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="uQKQ8pHw" X-UUID: 1c88ff5285f111ef88ecadb115cee93b-20241009 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=47Q10FQD37kvBYq5NBMe/5HrBX25A4BKbucRKWZR9Y4=; b=uQKQ8pHwF9MgOuODw6HILEgn9HDgNr5T4snjRuYTE1gzLCT80O5FDNpdwTIYvv5qbUe02Sx14yCNxC7We1ZUPYksjqOmcV/fHxHHsn36A4nKnByNqD/EvcwE+mp10TNCYrNARYUA13dGEPIinCsIwyO+aUB090qR10py5LoZh+4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.41,REQID:f71c7060-7ed9-41ee-acbd-a58548aee831,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:6dc6a47,CLOUDID:10a8f940-8751-41b2-98dd-475503d45150,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES :1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: 1c88ff5285f111ef88ecadb115cee93b-20241009 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 897258336; Wed, 09 Oct 2024 11:46:48 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 9 Oct 2024 11:46:47 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 9 Oct 2024 11:46:47 +0800 From: Jason-JH.Lin To: Adam Thiede , Yassine Oudjana , Chun-Kuang Hu , AngeloGioacchino Del Regno CC: Shawn Sung , Alper Nebi Yasak , , , , , "Jason-JH . Lin" , Singo Chang , Nancy Lin , Subject: [PATCH v11 2/5] drm/mediatek: ovl: Refine ignore_pixel_alpha comment and placement Date: Wed, 9 Oct 2024 11:46:43 +0800 Message-ID: <20241009034646.13143-3-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20241009034646.13143-1-jason-jh.lin@mediatek.com> References: <20241009034646.13143-1-jason-jh.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Refine the comment for ignore_pixel_alpha flag and move it to if(state->fb) statement to make it less conditional. Signed-off-by: Jason-JH.Lin Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu Tested-by: Chen-Yu Tsai --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 047cd1796a51..0d3a9c5e8d26 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -481,16 +481,16 @@ void mtk_ovl_layer_config(struct device *dev, unsigne= d int idx, */ if (blend_mode || state->base.fb->format->has_alpha) con |=3D OVL_CON_AEN; - } =20 - /* CONST_BLD must be enabled for XRGB formats although the alpha channel - * can be ignored, or OVL will still read the value from memory. - * For RGB888 related formats, whether CONST_BLD is enabled or not won't - * affect the result. Therefore we use !has_alpha as the condition. - */ - if ((state->base.fb && !state->base.fb->format->has_alpha) || - blend_mode =3D=3D DRM_MODE_BLEND_PIXEL_NONE) - ignore_pixel_alpha =3D OVL_CONST_BLEND; + /* + * Although the alpha channel can be ignored, CONST_BLD must be enabled + * for XRGB format, otherwise OVL will still read the value from memory. + * For RGB888 related formats, whether CONST_BLD is enabled or not won't + * affect the result. Therefore we use !has_alpha as the condition. + */ + if (blend_mode =3D=3D DRM_MODE_BLEND_PIXEL_NONE || !state->base.fb->form= at->has_alpha) + ignore_pixel_alpha =3D OVL_CONST_BLEND; + } =20 if (pending->rotation & DRM_MODE_REFLECT_Y) { con |=3D OVL_CON_VIRT_FLIP; --=20 2.43.0 From nobody Wed Nov 27 17:45:45 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06E5476048 for ; Wed, 9 Oct 2024 03:46:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728445616; cv=none; b=ai6EI3XAit4wmo97GD3S1rcZYllBnTYtVnp37RmjRsHvUDEgNdiFblsmJJ4dpKQOIP0XUCURfxfJOsyLVysGYgoPmSW1wT0MEbhBpVIU8lZ7KDF6uHVnkRkk9X2uRg0Lns1NAuoDQLMdlaiVqdCaUgkg1jaT+BLpzGYhDXzS8JA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728445616; c=relaxed/simple; bh=kKt6YICJ6tQD7S1l9bVSjIvW2jL+BpNfVsffcMpQTMs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ne4Z/G1RadoJS1JKfltgzWih5B8tRWTtgt0LK1XxvwMqFERIM5GlZyRN8PPvyZfcUUz7sbO+jIQ/15KfvWI7sDgLjbXjfv0qOgUQ105m+4sKpuzRRQ3jszowanae+HcOt++4SqvgWn+VAzFdx0vJZGJw4JZbtTHz264Ttom7pGE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=oAGx7rT9; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="oAGx7rT9" X-UUID: 1d06f7f485f111ef8b96093e013ec31c-20241009 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=oqlp+hC1+rn6mVdWdXR2LN/CqTCqC5lEUqhZ8cUD4OI=; b=oAGx7rT9mLDb/NY13oPRpvA1wwmebFi/Zh/KBtQzGEO6B4hNIZ/OmbKsglaU2zMfDDuuyXRHKllIP/4CET/LmbWKoW7+ic3FNDlvAGew2JVDBwSxgyevUw6feERfjZ/VOJlv7bCfNjMueccX2wDLnxd44TRMNV+YtX1nf3oqryg=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.41,REQID:5183fba0-9d15-4bbe-a56b-19bc8a2aa51c,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:6dc6a47,CLOUDID:0d72f764-444a-4b47-a99a-591ade3b04b2,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES :1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: 1d06f7f485f111ef8b96093e013ec31c-20241009 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1618659979; Wed, 09 Oct 2024 11:46:49 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 9 Oct 2024 11:46:47 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 9 Oct 2024 11:46:47 +0800 From: Jason-JH.Lin To: Adam Thiede , Yassine Oudjana , Chun-Kuang Hu , AngeloGioacchino Del Regno CC: Shawn Sung , Alper Nebi Yasak , , , , , "Jason-JH . Lin" , Singo Chang , "Nancy Lin" , Subject: [PATCH v11 3/5] drm/mediatek: ovl: Remove the color format comment for ovl_fmt_convert() Date: Wed, 9 Oct 2024 11:46:44 +0800 Message-ID: <20241009034646.13143-4-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20241009034646.13143-1-jason-jh.lin@mediatek.com> References: <20241009034646.13143-1-jason-jh.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--3.679400-8.000000 X-TMASE-MatchedRID: JqvUv0YB5EcxgGuH6sDPS8u00lnG8+PW4+ZcrqvCDkFcKZwALwMGsyc/ xZYu98DINdSJDUY9JRESqo3ZUfrHh25/NyTKlG694pdq9sdj8LVaNaxZBRbNWi8zQZ2rR/Opl12 4J4jWEmtRY9f7h2Xyki1nQIsbRW6GSJvHZYIIxMieAiCmPx4NwBnUJ0Ek6yhjxEHRux+uk8ifEz J5hPndGVq6wMyJqZhvNqiXCKftsUJWCAG9E8h5zJ99RML1VXr4mL69iLkCQJ1h881CAW22/TF6c AEfHrzia3prxka/F+M8fwGD9FLhvHmVKZusLp922v9OjYWA2uMMswg45VMfPadst5iAforfVlxr 1FJij9s= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--3.679400-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: FF68AA1BB74E71C70A2BE84749CA8EB0F84B94363C9B5A4B3B201A7973343AA92000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since we changed MACROs to be consistent with DRM input color format naming, the comment for ovl_fmt_conver() is no longer needed. Fixes: 9f428b95ac89 ("drm/mediatek: Add new color format MACROs in OVL") Signed-off-by: Jason-JH.Lin Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 0d3a9c5e8d26..1ccb700858cf 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -389,11 +389,6 @@ void mtk_ovl_layer_off(struct device *dev, unsigned in= t idx, static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int= fmt, unsigned int blend_mode) { - /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX" - * is defined in mediatek HW data sheet. - * The alphabet order in XXX is no relation to data - * arrangement in memory. - */ switch (fmt) { default: case DRM_FORMAT_RGB565: --=20 2.43.0 From nobody Wed Nov 27 17:45:45 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2E1344C8F for ; Wed, 9 Oct 2024 03:46:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728445616; cv=none; b=NaT/GCSJJbNDn3H4STyU/ewRk1g1grAmj7JIocFi2ikeqmBMFGImk/Hnccgot08DmrcNRObNXU7+oGVloLQrDJiShsbaingSEEsyjDruk1OmvCaou8viKKIjs7SfT5i0y2KtqKgj2lLhovHl8IeFCf49G4ccVB9fj+2EN95Su/8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728445616; c=relaxed/simple; bh=Tst+5L/0B57AO/r684wWd6eD2nFF+PIpQxvY4GGn9Dc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=JUsbeJdPuVk+z9fVUsZo3GT0zW4rPqbUJ4K2VCcdiPKcf16S/Nu9CxGkDPfeo366TY6vm7PdBNPIWrgQ7VLTb37D0IpnzqpFDXgkxtQcVxgn984Zkdn1pe+oZurtsXI29XDd8gFYNn2yz5Cxuw/CNfVNTu00Vgn0HgBCpNs+ypk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=sdPz4L+I; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="sdPz4L+I" X-UUID: 1d0af0a285f111ef8b96093e013ec31c-20241009 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=4I/AeCAq+Hpl0MXyN7V8FHQ2+3NBTc6bczzM6kzFk50=; b=sdPz4L+IulyOGvuXKZ44g2pYW4dUDspDLBLikyMRlcvNQvkLcGEWYc7oiQyMYYn6ZayU90nSFYSMu79QvMK7l6OlOqTQDIndze2Tb+Q8jPHNF+cFEh4RhvAH+C2A/vUVI9tKnKE/lcnQC1wm/4YjjsI/JaKat02WUbJT9vQL88k=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.41,REQID:c69bfd15-a4bb-4567-9214-859f8ac23d18,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:6dc6a47,CLOUDID:22a8f940-8751-41b2-98dd-475503d45150,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES :1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: 1d0af0a285f111ef8b96093e013ec31c-20241009 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 648087479; Wed, 09 Oct 2024 11:46:49 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 9 Oct 2024 11:46:47 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 9 Oct 2024 11:46:47 +0800 From: Jason-JH.Lin To: Adam Thiede , Yassine Oudjana , Chun-Kuang Hu , AngeloGioacchino Del Regno CC: Shawn Sung , Alper Nebi Yasak , , , , , "Jason-JH . Lin" , Singo Chang , "Nancy Lin" , Subject: [PATCH v11 4/5] drm/mediatek: ovl: Add blend_modes to driver data Date: Wed, 9 Oct 2024 11:46:45 +0800 Message-ID: <20241009034646.13143-5-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20241009034646.13143-1-jason-jh.lin@mediatek.com> References: <20241009034646.13143-1-jason-jh.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--11.742200-8.000000 X-TMASE-MatchedRID: PIIqySEg3TIzP1+hKLmUcMu00lnG8+PWIaLR+2xKRDLb6Y+fnTZULz94 HX24gqtC170RpEE9+Ch41slfouzT+EIjaJSsaV6q9Jn/ZrGuc8HSL+EVfOJR07FRmrhHzmfvR+m RDHa7QqxsMMavja2AExKqjdlR+seHLVayL7k7olyQOktEo73GFArefVId6fzVCqIJhrrDy28j7P LDbldk2nqqxcrRKidevws8hDIFFaPGWQHDiYaPQNF8NCC76P7lS8T7akvAZuebKItl61J/yZ+in TK0bC9eKrauXd3MZDXu282lqx9QkRwU5Kg3aRB1xs5/VGEFZEg3L6DvyWRHENmgQRUe+/9l X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--11.742200-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 6559183837046EBD708A579C3BBA0B896C90332D6566301B44ACC9C25E53A8D02000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" OVL_CON_CLRFMT_MAN is a configuration for extending color format settings of DISP_REG_OVL_CON(n). It will change some of the original color format settings. Take the settings of (3 << 12) for example. - If OVL_CON_CLRFMT_MAN =3D 0 means OVL_CON_CLRFMT_RGBA8888. - If OVL_CON_CLRFMT_MAN =3D 1 means OVL_CON_CLRFMT_PARGB8888. Since previous SoCs did not support OVL_CON_CLRFMT_MAN, this means that the SoC does not support the premultiplied color format. It will break the original color format setting of MT8173. Therefore, the blend_modes is added to the driver data and then mtk_ovl_fmt_convert() will check the blend_modes to see if pre-multiplied is supported in the current platform. If it is not supported, use coverage mode to set it to the supported color formats to solve the degradation problem. Fixes: a3f7f7ef4bfe ("drm/mediatek: Support "Pre-multiplied" blending in OV= L") Signed-off-by: Jason-JH.Lin Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu Tested-by: Chen-Yu Tsai --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 34 ++++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 1ccb700858cf..fab23b1904bd 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -146,6 +146,7 @@ struct mtk_disp_ovl_data { bool fmt_rgb565_is_0; bool smi_id_en; bool supports_afbc; + const u32 blend_modes; const u32 *formats; size_t num_formats; bool supports_clrfmt_ext; @@ -386,9 +387,27 @@ void mtk_ovl_layer_off(struct device *dev, unsigned in= t idx, DISP_REG_OVL_RDMA_CTRL(idx)); } =20 -static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int= fmt, - unsigned int blend_mode) +static unsigned int mtk_ovl_fmt_convert(struct mtk_disp_ovl *ovl, + struct mtk_plane_state *state) { + unsigned int fmt =3D state->pending.format; + unsigned int blend_mode =3D DRM_MODE_BLEND_COVERAGE; + + /* + * For the platforms where OVL_CON_CLRFMT_MAN is defined in the hardware = data sheet + * and supports premultiplied color formats, such as OVL_CON_CLRFMT_PARGB= 8888. + * + * Check blend_modes in the driver data to see if premultiplied mode is s= upported. + * If not, use coverage mode instead to set it to the supported color for= mats. + * + * Current DRM assumption is that alpha is default premultiplied, so the = bitmask of + * blend_modes must include BIT(DRM_MODE_BLEND_PREMULTI). Otherwise, mtk_= plane_init() + * will get an error return from drm_plane_create_blend_mode_property() a= nd + * state->base.pixel_blend_mode should not be used. + */ + if (ovl->data->blend_modes & BIT(DRM_MODE_BLEND_PREMULTI)) + blend_mode =3D state->base.pixel_blend_mode; + switch (fmt) { default: case DRM_FORMAT_RGB565: @@ -466,7 +485,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned = int idx, return; } =20 - con =3D ovl_fmt_convert(ovl, fmt, blend_mode); + con =3D mtk_ovl_fmt_convert(ovl, state); if (state->base.fb) { con |=3D state->base.alpha & OVL_CON_ALPHA; =20 @@ -664,6 +683,9 @@ static const struct mtk_disp_ovl_data mt8192_ovl_driver= _data =3D { .layer_nr =3D 4, .fmt_rgb565_is_0 =3D true, .smi_id_en =3D true, + .blend_modes =3D BIT(DRM_MODE_BLEND_PREMULTI) | + BIT(DRM_MODE_BLEND_COVERAGE) | + BIT(DRM_MODE_BLEND_PIXEL_NONE), .formats =3D mt8173_formats, .num_formats =3D ARRAY_SIZE(mt8173_formats), }; @@ -674,6 +696,9 @@ static const struct mtk_disp_ovl_data mt8192_ovl_2l_dri= ver_data =3D { .layer_nr =3D 2, .fmt_rgb565_is_0 =3D true, .smi_id_en =3D true, + .blend_modes =3D BIT(DRM_MODE_BLEND_PREMULTI) | + BIT(DRM_MODE_BLEND_COVERAGE) | + BIT(DRM_MODE_BLEND_PIXEL_NONE), .formats =3D mt8173_formats, .num_formats =3D ARRAY_SIZE(mt8173_formats), }; @@ -685,6 +710,9 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver= _data =3D { .fmt_rgb565_is_0 =3D true, .smi_id_en =3D true, .supports_afbc =3D true, + .blend_modes =3D BIT(DRM_MODE_BLEND_PREMULTI) | + BIT(DRM_MODE_BLEND_COVERAGE) | + BIT(DRM_MODE_BLEND_PIXEL_NONE), .formats =3D mt8195_formats, .num_formats =3D ARRAY_SIZE(mt8195_formats), .supports_clrfmt_ext =3D true, --=20 2.43.0 From nobody Wed Nov 27 17:45:45 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B8E914B970 for ; Wed, 9 Oct 2024 03:46:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728445619; cv=none; b=eUVlBEVj2tB3qp6ibAi+Qq93m4R15BniEt3I1IMtkW+JYSi2/r6HLscAlBn8/6iSERPIQ7aFISdVyUUv17hvGkfczfWnmJ6CW0hmW7+MqGo+F66CZcD/XPcBEYcfo2Jr7igk4PnfiF+PETZc2H8cA+ZfV7wk6YCFPDy5ZZnssXs= ARC-Message-Signature: i=1; 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Wed, 09 Oct 2024 11:46:48 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 9 Oct 2024 11:46:47 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 9 Oct 2024 11:46:47 +0800 From: Jason-JH.Lin To: Adam Thiede , Yassine Oudjana , Chun-Kuang Hu , AngeloGioacchino Del Regno CC: Shawn Sung , Alper Nebi Yasak , , , , , "Jason-JH . Lin" , Singo Chang , Nancy Lin , Subject: [PATCH v11 5/5] drm/mediatek: Add blend_modes to mtk_plane_init() for different SoCs Date: Wed, 9 Oct 2024 11:46:46 +0800 Message-ID: <20241009034646.13143-6-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20241009034646.13143-1-jason-jh.lin@mediatek.com> References: <20241009034646.13143-1-jason-jh.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since some SoCs support premultiplied pixel formats but some do not, the blend_modes parameter is added to mtk_plane_init(), which is obtained from the mtk_ddp_comp_get_blend_modes function implemented in different blending supported components. The blending supported components can use driver data to set the blend mode capabilities for different SoCs. Signed-off-by: Jason-JH.Lin Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu Tested-by: Chen-Yu Tsai --- drivers/gpu/drm/mediatek/mtk_crtc.c | 1 + drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 2 ++ drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 10 ++++++++++ drivers/gpu/drm/mediatek/mtk_disp_drv.h | 2 ++ drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 7 +++++++ drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 7 +++++++ drivers/gpu/drm/mediatek/mtk_ethdr.c | 7 +++++++ drivers/gpu/drm/mediatek/mtk_ethdr.h | 1 + drivers/gpu/drm/mediatek/mtk_plane.c | 15 +++++++-------- drivers/gpu/drm/mediatek/mtk_plane.h | 4 ++-- 10 files changed, 46 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek= /mtk_crtc.c index 175b00e5a253..b65f196f2015 100644 --- a/drivers/gpu/drm/mediatek/mtk_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_crtc.c @@ -913,6 +913,7 @@ static int mtk_crtc_init_comp_planes(struct drm_device = *drm_dev, BIT(pipe), mtk_crtc_plane_type(mtk_crtc->layer_nr, num_planes), mtk_ddp_comp_supported_rotations(comp), + mtk_ddp_comp_get_blend_modes(comp), mtk_ddp_comp_get_formats(comp), mtk_ddp_comp_get_num_formats(comp), i); if (ret) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.c index be66d94be361..edc6417639e6 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -363,6 +363,7 @@ static const struct mtk_ddp_comp_funcs ddp_ovl =3D { .layer_config =3D mtk_ovl_layer_config, .bgclr_in_on =3D mtk_ovl_bgclr_in_on, .bgclr_in_off =3D mtk_ovl_bgclr_in_off, + .get_blend_modes =3D mtk_ovl_get_blend_modes, .get_formats =3D mtk_ovl_get_formats, .get_num_formats =3D mtk_ovl_get_num_formats, }; @@ -416,6 +417,7 @@ static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = =3D { .disconnect =3D mtk_ovl_adaptor_disconnect, .add =3D mtk_ovl_adaptor_add_comp, .remove =3D mtk_ovl_adaptor_remove_comp, + .get_blend_modes =3D mtk_ovl_adaptor_get_blend_modes, .get_formats =3D mtk_ovl_adaptor_get_formats, .get_num_formats =3D mtk_ovl_adaptor_get_num_formats, .mode_valid =3D mtk_ovl_adaptor_mode_valid, diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.h index ecf6dc283cd7..39720b27f4e9 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h @@ -80,6 +80,7 @@ struct mtk_ddp_comp_funcs { void (*ctm_set)(struct device *dev, struct drm_crtc_state *state); struct device * (*dma_dev_get)(struct device *dev); + u32 (*get_blend_modes)(struct device *dev); const u32 *(*get_formats)(struct device *dev); size_t (*get_num_formats)(struct device *dev); void (*connect)(struct device *dev, struct device *mmsys_dev, unsigned in= t next); @@ -266,6 +267,15 @@ static inline struct device *mtk_ddp_comp_dma_dev_get(= struct mtk_ddp_comp *comp) return comp->dev; } =20 +static inline +u32 mtk_ddp_comp_get_blend_modes(struct mtk_ddp_comp *comp) +{ + if (comp->funcs && comp->funcs->get_blend_modes) + return comp->funcs->get_blend_modes(comp->dev); + + return 0; +} + static inline const u32 *mtk_ddp_comp_get_formats(struct mtk_ddp_comp *comp) { diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/medi= atek/mtk_disp_drv.h index 082ac18fe04a..04154db9085c 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -103,6 +103,7 @@ void mtk_ovl_register_vblank_cb(struct device *dev, void mtk_ovl_unregister_vblank_cb(struct device *dev); void mtk_ovl_enable_vblank(struct device *dev); void mtk_ovl_disable_vblank(struct device *dev); +u32 mtk_ovl_get_blend_modes(struct device *dev); const u32 *mtk_ovl_get_formats(struct device *dev); size_t mtk_ovl_get_num_formats(struct device *dev); =20 @@ -131,6 +132,7 @@ void mtk_ovl_adaptor_start(struct device *dev); void mtk_ovl_adaptor_stop(struct device *dev); unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev); struct device *mtk_ovl_adaptor_dma_dev_get(struct device *dev); +u32 mtk_ovl_adaptor_get_blend_modes(struct device *dev); const u32 *mtk_ovl_adaptor_get_formats(struct device *dev); size_t mtk_ovl_adaptor_get_num_formats(struct device *dev); enum drm_mode_status mtk_ovl_adaptor_mode_valid(struct device *dev, diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index fab23b1904bd..9786ce94de0e 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -215,6 +215,13 @@ void mtk_ovl_disable_vblank(struct device *dev) writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN); } =20 +u32 mtk_ovl_get_blend_modes(struct device *dev) +{ + struct mtk_disp_ovl *ovl =3D dev_get_drvdata(dev); + + return ovl->data->blend_modes; +} + const u32 *mtk_ovl_get_formats(struct device *dev) { struct mtk_disp_ovl *ovl =3D dev_get_drvdata(dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index c6768210b08b..bf2546c4681a 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -400,6 +400,13 @@ void mtk_ovl_adaptor_disable_vblank(struct device *dev) mtk_ethdr_disable_vblank(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0= ]); } =20 +u32 mtk_ovl_adaptor_get_blend_modes(struct device *dev) +{ + struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); + + return mtk_ethdr_get_blend_modes(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTO= R_ETHDR0]); +} + const u32 *mtk_ovl_adaptor_get_formats(struct device *dev) { struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediate= k/mtk_ethdr.c index d1d9cf8b10e1..0f22e7d337cb 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -145,6 +145,13 @@ static irqreturn_t mtk_ethdr_irq_handler(int irq, void= *dev_id) return IRQ_HANDLED; } =20 +u32 mtk_ethdr_get_blend_modes(struct device *dev) +{ + return BIT(DRM_MODE_BLEND_PREMULTI) | + BIT(DRM_MODE_BLEND_COVERAGE) | + BIT(DRM_MODE_BLEND_PIXEL_NONE); +} + void mtk_ethdr_layer_config(struct device *dev, unsigned int idx, struct mtk_plane_state *state, struct cmdq_pkt *cmdq_pkt) diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.h b/drivers/gpu/drm/mediate= k/mtk_ethdr.h index 81af9edea3f7..a72aeee46829 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.h +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.h @@ -13,6 +13,7 @@ void mtk_ethdr_clk_disable(struct device *dev); void mtk_ethdr_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); +u32 mtk_ethdr_get_blend_modes(struct device *dev); void mtk_ethdr_layer_config(struct device *dev, unsigned int idx, struct mtk_plane_state *state, struct cmdq_pkt *cmdq_pkt); diff --git a/drivers/gpu/drm/mediatek/mtk_plane.c b/drivers/gpu/drm/mediate= k/mtk_plane.c index 7d2cb4e0fafa..8a48b3b0a956 100644 --- a/drivers/gpu/drm/mediatek/mtk_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_plane.c @@ -320,8 +320,8 @@ static const struct drm_plane_helper_funcs mtk_plane_he= lper_funcs =3D { =20 int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane, unsigned long possible_crtcs, enum drm_plane_type type, - unsigned int supported_rotations, const u32 *formats, - size_t num_formats, unsigned int plane_idx) + unsigned int supported_rotations, const u32 blend_modes, + const u32 *formats, size_t num_formats, unsigned int plane_idx) { int err; =20 @@ -366,12 +366,11 @@ int mtk_plane_init(struct drm_device *dev, struct drm= _plane *plane, if (err) DRM_ERROR("failed to create property: alpha\n"); =20 - err =3D drm_plane_create_blend_mode_property(plane, - BIT(DRM_MODE_BLEND_PREMULTI) | - BIT(DRM_MODE_BLEND_COVERAGE) | - BIT(DRM_MODE_BLEND_PIXEL_NONE)); - if (err) - DRM_ERROR("failed to create property: blend_mode\n"); + if (blend_modes) { + err =3D drm_plane_create_blend_mode_property(plane, blend_modes); + if (err) + DRM_ERROR("failed to create property: blend_mode\n"); + } =20 drm_plane_helper_add(plane, &mtk_plane_helper_funcs); =20 diff --git a/drivers/gpu/drm/mediatek/mtk_plane.h b/drivers/gpu/drm/mediate= k/mtk_plane.h index 5b177eac67b7..3b13b89989c7 100644 --- a/drivers/gpu/drm/mediatek/mtk_plane.h +++ b/drivers/gpu/drm/mediatek/mtk_plane.h @@ -48,6 +48,6 @@ to_mtk_plane_state(struct drm_plane_state *state) =20 int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane, unsigned long possible_crtcs, enum drm_plane_type type, - unsigned int supported_rotations, const u32 *formats, - size_t num_formats, unsigned int plane_idx); + unsigned int supported_rotations, const u32 blend_modes, + const u32 *formats, size_t num_formats, unsigned int plane_idx); #endif --=20 2.43.0