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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-13-76d4f5d413bf@linaro.org> References: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> In-Reply-To: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728463820; l=5496; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=81jK3N0j+q+DAMnsIs+UuOUU0xKWIcMiivwpFJMyey8=; b=T2DDlAeki79IVTctGUrvaj5XGACyxwdgxLwVCSDMiyi7MaCokffcNiEXMdg9z8ampm5Okjoid qYQVV0H1p1TBiQAtOoEekEoUnh5BEej73xKINai11HinJq+tccjEGZy X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Support SSPP assignment for quad-pipe case with unified method. The first 2 pipes can share a set of mixer config and enable multi-rect mode if condition is met. It is also the case for the later 2 pipes. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 85 +++++++++++++++------------= ---- 1 file changed, 42 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index 480a1b46aba72..23de2ca6fabb0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -999,7 +999,7 @@ static int dpu_plane_atomic_check_pipes(struct drm_plan= e *plane, pipe =3D &pstate->pipe[i]; pipe_cfg =3D &pstate->pipe_cfg[i]; if (!pipe_cfg->valid || !pipe->sspp) - break; + continue; DPU_DEBUG_PLANE(pdpu, "pipe %d is in use, validate it\n", i); ret =3D dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, &crtc_state->adjusted_mode, @@ -1154,13 +1154,10 @@ static int dpu_plane_virtual_assign_resources(struc= t drm_crtc *crtc, struct dpu_kms *dpu_kms =3D _dpu_plane_get_kms(plane); struct dpu_rm_sspp_requirements reqs; struct dpu_plane_state *pstate; - struct dpu_sw_pipe *pipe; - struct dpu_sw_pipe *r_pipe; - struct dpu_sw_pipe_cfg *pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg; + struct dpu_plane *pdpu =3D to_dpu_plane(plane); const struct msm_format *fmt; uint32_t max_linewidth; - int i; + int i, lm_num, lmcfg_id, lmcfg_num; =20 if (plane_state->crtc) crtc_state =3D drm_atomic_get_new_crtc_state(state, @@ -1168,12 +1165,6 @@ static int dpu_plane_virtual_assign_resources(struct= drm_crtc *crtc, =20 pstate =3D to_dpu_plane_state(plane_state); =20 - /* loop below code for another pair later */ - pipe =3D &pstate->pipe[0]; - r_pipe =3D &pstate->pipe[1]; - pipe_cfg =3D &pstate->pipe_cfg[0]; - r_pipe_cfg =3D &pstate->pipe_cfg[1]; - for (i =3D 0; i < PIPES_PER_PLANE; i++) pstate->pipe[i].sspp =3D NULL; =20 @@ -1189,41 +1180,49 @@ static int dpu_plane_virtual_assign_resources(struc= t drm_crtc *crtc, =20 max_linewidth =3D dpu_kms->catalog->caps->max_linewidth; =20 - pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &req= s); - if (!pipe->sspp) - return -ENODEV; - - if (drm_rect_width(&r_pipe_cfg->src_rect) =3D=3D 0) { - pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; - - r_pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; - - r_pipe->sspp =3D NULL; - } else { - if (dpu_plane_is_multirect_parallel_capable(pipe, pipe_cfg, fmt, max_lin= ewidth) && - dpu_plane_is_multirect_parallel_capable(r_pipe, r_pipe_cfg, fmt, max= _linewidth) && - (test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) || - test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features))) { - r_pipe->sspp =3D pipe->sspp; + lm_num =3D dpu_crtc_get_lm_num(crtc_state); + lmcfg_num =3D (lm_num + 1) / 2; + for (lmcfg_id =3D 0; lmcfg_id < lmcfg_num; lmcfg_id++) { + for (i =3D lmcfg_id * PIPES_PER_LM_PAIR; i < (lmcfg_id + 1) * PIPES_PER_= LM_PAIR; i++) { + struct dpu_sw_pipe *pipe =3D &pstate->pipe[i]; + struct dpu_sw_pipe *r_pipe =3D &pstate->pipe[i + 1]; + struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg[i]; + struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->pipe_cfg[i + 1]; =20 - pipe->multirect_index =3D DPU_SSPP_RECT_0; - pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_PARALLEL; + if (!pipe_cfg->valid) + break; =20 - r_pipe->multirect_index =3D DPU_SSPP_RECT_1; - r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_PARALLEL; - } else { - /* multirect is not possible, use two SSPP blocks */ - r_pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, = &reqs); - if (!r_pipe->sspp) + pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &r= eqs); + if (!pipe->sspp) return -ENODEV; =20 - pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; - - r_pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + /* + * If current pipe is the first pipe in pipe pair, check + * multi-rect opportunity for the 2nd pipe in the pair. + * SSPP multi-rect mode cross mixer pairs is not supported. + */ + if (!(i % 2) && + r_pipe_cfg->valid && + drm_rect_width(&r_pipe_cfg->src_rect) !=3D 0 && + dpu_plane_is_multirect_parallel_capable(pipe, pipe_cfg, fmt, max_li= newidth) && + dpu_plane_is_multirect_parallel_capable(r_pipe, r_pipe_cfg, fmt, ma= x_linewidth) && + (test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) || + test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features))) { + pipe->multirect_index =3D DPU_SSPP_RECT_0; + pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_PARALLEL; + + DPU_DEBUG_PLANE(pdpu, "allocating sspp_%d for pipe %d and set pipe %d = as multi-rect\n", + pipe->sspp->idx - SSPP_NONE, i, i + 1); + r_pipe->sspp =3D pipe->sspp; + r_pipe->multirect_index =3D DPU_SSPP_RECT_1; + r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_PARALLEL; + i++; + } else { + pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; + pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + DPU_DEBUG_PLANE(pdpu, "allocating sspp_%d for pipe %d.\n", + pipe->sspp->idx - SSPP_NONE, i); + } } } =20 --=20 2.34.1