From nobody Wed Nov 27 14:32:38 2024 Received: from mail-pj1-f47.google.com (mail-pj1-f47.google.com [209.85.216.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88C2918E023 for ; Wed, 9 Oct 2024 08:50:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728463832; cv=none; b=PqT0B7NOsZzRjkw/5GCcAeg99zOmWKNPyO1L8r9cOxNGvoSPOm5Ne+bcrWTKNk2p05FbxD0eAWYSas3MslxruWRUSPNOkXvKAo1/a29H9h+T42hJ67ZZlT1UbVcaZf7CSNb03WXv+PuJmFLmAHZM3OGuvciFfyMaxGMk9BBpF8Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728463832; c=relaxed/simple; bh=AOnvev//l48K9poLpI3b2jyK6oiNPwqIXWbViweShqc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Ys9CUBHSl0e7EyY/zIQRajLkScrAMCAVtph88/cqEHpHKAuMTfivQWJRKMbsC0cAONt0Qr8BKhZKyLjcxnlguJQ1X5Yj9v3D4b6Yb3jl2kUup1BmW0z/l8HFwIY+KZnAsMwTlSSOL/fRYiQD++a/MMoIBWM1fmOjw1JAUUDTHTc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=e2u4kKfZ; arc=none smtp.client-ip=209.85.216.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="e2u4kKfZ" Received: by mail-pj1-f47.google.com with SMTP id 98e67ed59e1d1-2e0946f9a8eso4536571a91.1 for ; Wed, 09 Oct 2024 01:50:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728463830; x=1729068630; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=c7bIuQoomWT/rx9ticSN25UJS+k6AR92dNlVIMn4xi0=; b=e2u4kKfZuBliioggdDtrXMdMyJ8fU22MxCvqohdZJTgX2t/2fCghwRDNetylRT1+5E 17BP5gfcc1Q1Z0b39w1VnVDTNny6h0VpbkRMJLj20OhazKVRQS4p6te/aBUoXQo5yN1h rSDRKddOhE22TrYCG2NmTuyb9ZADj9WKCiQdmxDqor1XT5+mWS4AR5gxLC5VEgdQNJTB ypobbUpVaAhNkFlYVNIeLCEyGHGq36USGo0DddRffBlrZ0RRgkg0DwaGLJfJ2ZX1PHg8 si+U6VdVEzb7PALKo5z39XrlhBAJG0PRZ9HcWIyJbXhQ6JEkEbs/QUVDtO94+iXbbf0y fagg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728463830; x=1729068630; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c7bIuQoomWT/rx9ticSN25UJS+k6AR92dNlVIMn4xi0=; b=aJVheIgGmfgJfD5Ti0LRMa2o5OWL45s8k2k40kXJZRCc3lk+DsxQypamLgXI0lPtN5 8A0jA36Lz56iKJg4DxkiuSvOAZlvHx/kVDCrbWtemwH96haDo+VMIPpmIJR7Z9BhCy1y 225v617CafA4Cp0Us7ej3dhI3Dh9Mp8w6Vg1JtCy9lW7CLW+FHOooihDUDhxyhQpqkY+ 7eF2qPUaIqO7e5+ijEu4E0tVNWm5XvjDfcujG4llc73MvErLqj7v1THzCvO4vcLV7Lm/ L5tava3q1zG+hs1TLeug9tz7EYWWYqYHJwz3QcTLvgXW9PcAuRgWM9AXTznxRWE9+wRX BPMg== X-Forwarded-Encrypted: i=1; AJvYcCUl6rChLfkRnJYWJH5m0fVXJYM/LMPbTOPCVqG43yXOBPtDhePilFnkhoRQC9x+Zi0Cp69h3dEuysZYeCQ=@vger.kernel.org X-Gm-Message-State: AOJu0Yzpcb3gx7zxLJLE8xXvHgBu1C7kbYCPvIEv79Qi2uD7M2y9Mzx/ U327kyUraCpehEzR9teKlHG1iWFMnjlH+iKzggJsi9XmYWooFKyyEgrBULb/42HqL4aqQQD038z BIpIIJw== X-Google-Smtp-Source: AGHT+IESUTwygnYBSZdBsUDXgtACJ/v1ab4RJl/GTGW8J3oCmqBYI3AAq2s4v5mchDc9OY7NZ7CVOQ== X-Received: by 2002:a17:90a:cb01:b0:2e2:9314:2785 with SMTP id 98e67ed59e1d1-2e2a21ef23cmr2286037a91.5.1728463829841; Wed, 09 Oct 2024 01:50:29 -0700 (PDT) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2abad236esm898157a91.10.2024.10.09.01.50.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 01:50:29 -0700 (PDT) From: Jun Nie Date: Wed, 09 Oct 2024 16:50:14 +0800 Subject: [PATCH v2 01/14] drm/msm/dpu: polish log for resource allocation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-1-76d4f5d413bf@linaro.org> References: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> In-Reply-To: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728463820; l=1834; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=AOnvev//l48K9poLpI3b2jyK6oiNPwqIXWbViweShqc=; b=ZoaNma48RD560N7Wpt6QTcmjBW200b4i9cEzu0XKgwNwqPVL8i7T69/tEfkxovejkPIu+Mr28 li84Bu4qOo4AR+M+tDz5CECNYXgVmRhxQvGYnbyCwDuNNtvMOBsqH7e X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Add resource allocation type info. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/d= isp/dpu1/dpu_rm.c index 15b42a6683639..2b03ab907c2bc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -778,6 +778,21 @@ void dpu_rm_release_all_sspp(struct dpu_global_state *= global_state, ARRAY_SIZE(global_state->sspp_to_crtc_id), crtc_id); } =20 +static char *dpu_hw_blk_type_name[] =3D { + [DPU_HW_BLK_TOP] =3D "TOP", + [DPU_HW_BLK_SSPP] =3D "SSPP", + [DPU_HW_BLK_LM] =3D "LM", + [DPU_HW_BLK_CTL] =3D "CTL", + [DPU_HW_BLK_PINGPONG] =3D "pingpong", + [DPU_HW_BLK_INTF] =3D "INTF", + [DPU_HW_BLK_WB] =3D "WB", + [DPU_HW_BLK_DSPP] =3D "DSPP", + [DPU_HW_BLK_MERGE_3D] =3D "merge_3d", + [DPU_HW_BLK_DSC] =3D "DSC", + [DPU_HW_BLK_CDM] =3D "CDM", + [DPU_HW_BLK_MAX] =3D "none", +}; + int dpu_rm_get_assigned_resources(struct dpu_rm *rm, struct dpu_global_state *global_state, uint32_t enc_id, enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size) @@ -828,13 +843,13 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm, continue; =20 if (num_blks =3D=3D blks_size) { - DPU_ERROR("More than %d resources assigned to enc %d\n", - blks_size, enc_id); + DPU_ERROR("More than %d %s assigned to enc %d\n", + blks_size, dpu_hw_blk_type_name[type], enc_id); break; } if (!hw_blks[i]) { - DPU_ERROR("Allocated resource %d unavailable to assign to enc %d\n", - type, enc_id); + DPU_ERROR("%s unavailable to assign to enc %d\n", + dpu_hw_blk_type_name[type], enc_id); break; } blks[num_blks++] =3D hw_blks[i]; --=20 2.34.1 From nobody Wed Nov 27 14:32:38 2024 Received: from mail-pj1-f49.google.com (mail-pj1-f49.google.com [209.85.216.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D768818E34C for ; Wed, 9 Oct 2024 08:50:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728463837; cv=none; b=Zf3VwMZRwgxXzBDh1XbyYoNHD07mJzMpQV/s8DRjyVZ9ioB7Fbtk6aPxfoZ+ahlcKhlNlzTro4NYyxCySRzRXyAsC6ItFFjkSo0lrTapWnvK5GKFKum0vBkcr7pWr1Dwmx3cl6eD2F78ea/ZgreDQ9LnHia7VPF0E/vftYZCir0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728463837; c=relaxed/simple; bh=VkIAGwnZaBvIGk9O/Pd26yOaUH9F6U5Y+Vxq/wNMgsM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sDDt3kzHWbmVGStxpwbXo7jDHdPuS8cb6J6VrGfubvCMN6w9y/6uiA3pc7rMfMBkYLlgCOw9Q2r2qQ3pmZMkcYTjXM7lGisEFHD9q57+HviVgUmlnDiLNpZvZwdMf6DzJv0T4Ysk2YS7xFH1xM5YDk45250AN5VaiV7Xy5kd0uc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=JpH1P2PG; arc=none smtp.client-ip=209.85.216.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="JpH1P2PG" Received: by mail-pj1-f49.google.com with SMTP id 98e67ed59e1d1-2e09f67bc39so5465278a91.1 for ; Wed, 09 Oct 2024 01:50:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728463834; x=1729068634; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=rQUSJNvwZ/PY6GUH9AC1To+F9Rww7eBYxG8hGTmYBHA=; b=JpH1P2PGdhrv7UrLZEdbm2BgzHw+CU/c0HDvdb1VNCMWvjJONhFgGc81CWy1V3yWCH eqMhvL2+4VIjSaK4KgybfEJoApyDl57KGxHuMw1AirVORJOOp4XALhsD0fy77npElBxj LZvi0GF4HsSxkct8gIdKv3xJXBGb8pFGrC9sWhJtNCGP7pSj6uZ+u/04KeuqBAxQEG85 l9O0ZUNnbwRroR3s3SU2ZGB8EzDvTYD0rKVlIMBOOBF1XjDT71rPu5YzJcaPZ9MOKRdv 5GTZAdcdQidEDuseDvK5f6I9dIcuLrl0U6372+E0hw+JNA7IV90qsnXr0GkIL9/GwJho vXpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728463834; x=1729068634; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rQUSJNvwZ/PY6GUH9AC1To+F9Rww7eBYxG8hGTmYBHA=; b=ouVfmsFefyc3uBW0MMr6WYeE61qlnTvrkTl5joHQ47BXKlPUnuT9/ceD/10BohLe3J FJchZEQZyTMrb5hdkANg6JbU2UUWNdjYQLyOCP2Q6i7jXDGauyLoiKigEgxdZjKlLOCm jihu8UbCSP9IsmioUxel3LU9rTJzZHav7V5WJCWxObx1G4p9sfETs55FhsBQFFTibHaD UD0aQxZBZQjuGduRjdltYFKMPcQHt5hEpFF6EveEai4i63rXnB38dtZUrAIoK7CNomcF dRnAGODP0sPwubN15aR0M2K1i3xzmDaWVIh7v+03eULjAuyHzuncZWDgmXtexAU5moP2 1D8A== X-Forwarded-Encrypted: i=1; AJvYcCU04AlV/coL6KkvSNpC2Xkt9RUZ2CjRbM0mFHaDP5GDxITdT6foVvqvNIkTw66erpwJpTDIi9siEiZhS1c=@vger.kernel.org X-Gm-Message-State: AOJu0Yw4Af1vadaI0x72WpIwXI9x2PDmzWJq2570W4I3hU6Uqb7AMWE9 9Zh3QPqQkyETaCCJucvI/y7R+mLKg8smGzMQR6X87G4qV1fJP9+zoEwCTIZ9ZLc= X-Google-Smtp-Source: AGHT+IELZNGpZl+o9brSMTMV2R5qjLAQnLo4r4MZsTmntvKCuRTaaBljTAzcdiFMnYwOHsV1z7J9Aw== X-Received: by 2002:a17:90b:1104:b0:2e2:9522:279e with SMTP id 98e67ed59e1d1-2e2a25247e0mr2199871a91.31.1728463834283; Wed, 09 Oct 2024 01:50:34 -0700 (PDT) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2abad236esm898157a91.10.2024.10.09.01.50.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 01:50:34 -0700 (PDT) From: Jun Nie Date: Wed, 09 Oct 2024 16:50:15 +0800 Subject: [PATCH v2 02/14] drm/msm/dpu: decide right side per last bit Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-2-76d4f5d413bf@linaro.org> References: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> In-Reply-To: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728463820; l=1407; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=VkIAGwnZaBvIGk9O/Pd26yOaUH9F6U5Y+Vxq/wNMgsM=; b=aojPxprQ0psdASS4m8/E0MCuQj6okV8Fejiw7zVz4jm03ih52aCBaafWdJ/sa3xxRnZyuiX6W CVGfU1DgFG7D5QOSOi+332+U+ccsaaKBjtPHPV9UyH4D/pH/Nk9Dih0 X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= decide right side of a pair per last bit, in case of multiple mixer pairs. Signed-off-by: Jun Nie Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 7d0fff9472441..3e0e6e9757da5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -369,11 +369,10 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc= _mixer *mixer, static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc) { struct dpu_crtc_state *crtc_state; - int lm_idx, lm_horiz_position; + int lm_idx; =20 crtc_state =3D to_dpu_crtc_state(crtc->state); =20 - lm_horiz_position =3D 0; for (lm_idx =3D 0; lm_idx < crtc_state->num_mixers; lm_idx++) { const struct drm_rect *lm_roi =3D &crtc_state->lm_bounds[lm_idx]; struct dpu_hw_mixer *hw_lm =3D crtc_state->mixers[lm_idx].hw_lm; @@ -384,7 +383,7 @@ static void _dpu_crtc_program_lm_output_roi(struct drm_= crtc *crtc) =20 cfg.out_width =3D drm_rect_width(lm_roi); cfg.out_height =3D drm_rect_height(lm_roi); - cfg.right_mixer =3D lm_horiz_position++; + cfg.right_mixer =3D lm_idx & 0x1; cfg.flags =3D 0; hw_lm->ops.setup_mixer_out(hw_lm, &cfg); } --=20 2.34.1 From nobody Wed Nov 27 14:32:38 2024 Received: from mail-pj1-f48.google.com (mail-pj1-f48.google.com [209.85.216.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB82C18E37A for ; Wed, 9 Oct 2024 08:50:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728463841; cv=none; b=FWYyeaV8DrNZH3we4mK7d3+78uh3Kw+3a8J7Gjrpl+O+QEzl08Wq3W0VxcCd1SZx76SSKaUpCqW44MlgrAT15JV0u9SLH7EOMdHBOohkkzLNkEbRK3iAlCQwuqXZE2+KXXT9HoQm4EzhkMw7uujsY5H5Jn60Joapj9jOkxNUWSU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728463841; c=relaxed/simple; bh=WThdm3+r0o6lcg95hlJxNuerWQ1yzvjO0VMSK/DVslE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gvLsoFBoYUyjNnAPqbZ4B9LbfHW3w01wSmAg83PbbFUHnlOk+ricTy33/tDxOVtIEMi9LMHCsZCzJBCLn1+sLrJibzJaFqMA4PZ9w9LyPnGi4nHwc5hwzTdOFmvPoMy8V5jTTr3zNeRpAf5l5bmS1XKsBMLlj2e70yleWDzgzBQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=SUcVFI8R; arc=none smtp.client-ip=209.85.216.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="SUcVFI8R" Received: by mail-pj1-f48.google.com with SMTP id 98e67ed59e1d1-2e28d7d44dbso1195739a91.2 for ; Wed, 09 Oct 2024 01:50:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728463839; x=1729068639; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=E/voAymQ+FLo0K2rDmsz5j/XLkoeZJYYbnZfE87o5mA=; b=SUcVFI8RWgoKWqNI2Jz1eWMyUiaUg3SMN0/WD4l+ptSl1PCRjZUZU1TVCBAY7qVUSy SFMluSCR/PIlhn/it2AJmvFYKKGo1iijipmaVHg46Grx1KMH2liFY6Fw/dtTCGWujNOr k2+UG1WGJzwGg9fddhnT1KScN69OLCqOqWgHaOi1GtUg5OFykbUTMXdXAZz1ZC6YRZkb oOhK0ITnXifUwOnFXHiPKanqFes0kw4uH3ZBYbouw9uziTLv8ggTqiRHbAZE+b9kFCWN rGqNHG5kg2sC+NQFvUIrVuCPT0fSmB5oR/45K+Aeguv7WwpfnYg6eZqnSMbmlQNv8/hK 9zrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728463839; x=1729068639; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E/voAymQ+FLo0K2rDmsz5j/XLkoeZJYYbnZfE87o5mA=; b=Td2FFaF275j30f1hT5J5c9XawCxwKVPcYcsLUm4sACVJgizD04jy34cOW1n/sgwbPd rFFi5DQGfKrJcHxD8V8Dei//dNB7c3yaqd8oS+4ZKyN1OcGNkNEpe5HbRs6+wx+Dxx65 Pe7c4DlIaezxPV+2Tt0EK2dOJS+r6SiAGggC9dKf5CG6YtDuC3u1KevcjWpC9lj49joD x2ZgbTsa6XoSu+nccXhuCj1bWuzqQq9xOK6h7J8t/xkxFKGaFvfNMOM7ortTp1kMyW29 wjO/nvg4zgWtpZgafNGOluvuE/ghLfHmlqnL14MuUUgisCjQu5ZcIsB1aaTILw73duH5 SSyg== X-Forwarded-Encrypted: i=1; AJvYcCXGipJHt2jLNc+aAms1eh6uLi+SQQUWnXQNq88w0651syO8r/SigXL512hbBItYsPE4bTlPxzOiF6xIFx0=@vger.kernel.org X-Gm-Message-State: AOJu0YyWew1q/+pB1uCNqpdxn7X9r+p2+3OBfriD+dOL5guDGNdKxwKd PymQiX9zG4JeNJNUFASbL84mQLrMQTFENbuij/I7pwBbxYu7QjorELYwo5Q1IIQ= X-Google-Smtp-Source: AGHT+IGLdVPxQWHieF+9EHa8/WCKnJVudcn9L6wpuGsElJdCrsUD5SxSB2GtYHpHGZh8Ho+Hcyh1Xw== X-Received: by 2002:a17:90a:3489:b0:2e2:9a2a:d218 with SMTP id 98e67ed59e1d1-2e2a21ef24bmr2165076a91.2.1728463839143; Wed, 09 Oct 2024 01:50:39 -0700 (PDT) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2abad236esm898157a91.10.2024.10.09.01.50.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 01:50:38 -0700 (PDT) From: Jun Nie Date: Wed, 09 Oct 2024 16:50:16 +0800 Subject: [PATCH v2 03/14] drm/msm/dpu: fix mixer number counter on allocation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-3-76d4f5d413bf@linaro.org> References: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> In-Reply-To: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728463820; l=1237; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=WThdm3+r0o6lcg95hlJxNuerWQ1yzvjO0VMSK/DVslE=; b=XyWO3HZGDntoWFWpltwc8jk91TUGcI9j/DmmGgwXf1vPYLP+Lq3fLNGmynRO2WPSmNAdXF8VD e+84dPuuD53B+CK0+Zi+DNVJEJHL2kkrA5b3HQ84N4bqC1gD7g3BBDq X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Add the case to reserve multiple pairs mixers for high resolution. Current code only supports one pair of mixer usage case. To support quad-pipe usage case, two pairs of mixers are needed. Current code resets number of mixer on failure of pair's peer test and retry on another pair. If two pairs are needed, the failure on the test of 2nd pair results clearing to the 1st pair. This patch only clear the bit for the 2nd pair allocation before retry on another pair. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/d= isp/dpu1/dpu_rm.c index 2b03ab907c2bc..5c9bb64df7930 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -306,7 +306,11 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, if (!rm->mixer_blks[i]) continue; =20 - lm_count =3D 0; + /* + * Clear the last bit to drop the previous primary mixer if + * fail to find its peer. + */ + lm_count &=3D 0xfe; lm_idx[lm_count] =3D i; =20 if (!_dpu_rm_check_lm_and_get_connected_blks(rm, global_state, --=20 2.34.1 From nobody Wed Nov 27 14:32:38 2024 Received: from mail-pg1-f177.google.com (mail-pg1-f177.google.com [209.85.215.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4A50156242 for ; Wed, 9 Oct 2024 08:50:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728463847; cv=none; b=UbovleGAMFDn3SNLnYFWqC+9oMtY27gIX6erAmWWDHDYYu8Gw0c36GEoHmkWgBa2+4T9OJw5L0Wgdvs9O5Jk75VyLhf4dEhFWsrHCxj0eq4KMTWQAknZSz6mSSIgQZzqZgyIXi0Fbwc2uv+XASoJHp5Rnr9EY4iHeS2z3V5xTiM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728463847; c=relaxed/simple; bh=KJa8UFj1F4L8nQh4hIiMMrUpybEXZ51VO2/k9KJv3XQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EU8jjeSDWfSGAPeXkwlh/ebLx23tchvalbYNKnm9IB9zbZN+JCPj2XsUAz2ojrpfGzOz4hqCEJnU5QUWxYlHE4Um6LNHI6pDTUv2rwiTfBV0KAPnbkkcUDx0NRmd1mlWZGhlu7Q4hk8RT9JWSes46q4gNFOia9Vgd2+WmMFiq4Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=nZqJrlOP; arc=none smtp.client-ip=209.85.215.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="nZqJrlOP" Received: by mail-pg1-f177.google.com with SMTP id 41be03b00d2f7-7d4fa972cbeso4843097a12.2 for ; Wed, 09 Oct 2024 01:50:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728463845; x=1729068645; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=gFxoZp5lvl8L75KXTXnmIeC5GQOmgq4jA/ny4+kC/hI=; b=nZqJrlOP4quDRS9EsEEFnZiFAHihOIUy5SnQDPzae19Bgf+Jlx/1WYcaqa+qfbGy1T pcnI5LJeDcAgFbZsYrCcmjLA7O6Nm3rmXxL8AnWfJiFGyVH0AqKfKui+SPda0Lce+kgK 1bVLxafnNpYUHbfhxpYWKUVjPo87jh28FVkHna3IQMKZtk4rXzOXJ3/w9wc3ALoAi+91 1DThl2BNR4kJI/y3RGc/2S27fkcNLezdbMP5bPLRbx8JSArY140PjAqMAZgUpEOsEOC8 tF7cqaSZo72/UxNlwnX6ndHlTUg8WSf7I/731CVq6wNpkzxBa0MufHR0l5ZRwpoMaFyy hDeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728463845; x=1729068645; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gFxoZp5lvl8L75KXTXnmIeC5GQOmgq4jA/ny4+kC/hI=; b=HW+G3Cb7CepYU8Zxvh6cWklLuMHZIhQbyE8xudO/9X/FmkxuTUu70nVkRjoVfKqtXc JhqD9ew5hPZWU/kIuNSmyeZW5DiAOBjKM/FmLtvRW28coZVCMuCWLy9vdy2UGZnBGl3k 97HVD6xuiOzAVmoqNomPIypsU3ofNjMLzHDrnERQ43tuOMOzenFTtjOoLbvKeZddQKVt 43kNhDTI0CkDiUgq5tWjgi4wRklc0VKqJty5qPOO0r0mjNz8LKHyDnepM60KcYAYzcSX ej/6NyoMaU7pQsTsE1DK0ETtKDicL//Gh1t7TrxOZM2xW+cc7nVr3M1ZH12DFTwyzUB3 vnXQ== X-Forwarded-Encrypted: i=1; AJvYcCXluiv+5Uqekp/CQWsvGctoX4j0Dwyd3C4+RckDAGmfum8VUhcoX/tqBsRoFAyAj9YNY7YvchgK5PJryOE=@vger.kernel.org X-Gm-Message-State: AOJu0Yzbh+4rI46OI0Cs6BtkzeAcSogJc8+CwQi8G6aPCg1cuLYMUGLw Mfdco7pq9OddNwkHkwKdXNwLzwuDVi26x39lSmxLLU2KnnxNX95iYnaNFm+io5s= X-Google-Smtp-Source: AGHT+IER5m8hOoH/Wws+QEssyk0f1aSKzdwJ8U1bUR/9WTE+/Czt6Ufxweg/byCCtqaNnoKEwDNiVQ== X-Received: by 2002:a17:90a:f0d1:b0:2e2:abab:c450 with SMTP id 98e67ed59e1d1-2e2ababc590mr1412105a91.11.1728463844828; Wed, 09 Oct 2024 01:50:44 -0700 (PDT) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2abad236esm898157a91.10.2024.10.09.01.50.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 01:50:44 -0700 (PDT) From: Jun Nie Date: Wed, 09 Oct 2024 16:50:17 +0800 Subject: [PATCH v2 04/14] drm/msm/dpu: switch RM to use crtc_id rather than enc_id for allocation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-4-76d4f5d413bf@linaro.org> References: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> In-Reply-To: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728463820; l=25681; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=KJa8UFj1F4L8nQh4hIiMMrUpybEXZ51VO2/k9KJv3XQ=; b=Ii9UtPVf6NHG4/sGXzCHJ9n8R3KY/21OqwzXDuPHQEe48KWIvavFH4PFOBQg5RFXaGv6BEMxC LZpHhkxlsxtDUn35atXgn0Bscm1l+J0WFIhkSL0++unKwMxl03gSN/w X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Up to now the driver has been using encoder to allocate hardware resources. Switch it to use CRTC id so that mixer number can be known in dpu_plane_virtual_assign_resources() via CRTC id for sspp alloation. Because the mixer allocation is done in drm_atomic_helper_check_modeset() as part of CRTC operation. While the sspp assignment is in drm_atomic_helper_check_planes() call tree. So CRTC is more central than encoder. Siwtching the id achieves above goal. Co-developed-by: Dmitry Baryshkov Signed-off-by: Dmitry Baryshkov Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 18 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 12 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 189 ++++++++++++++----------= ---- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 19 ++- 4 files changed, 116 insertions(+), 122 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index e8400b494687c..bd2509985c4d0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -687,11 +687,11 @@ static int dpu_encoder_virt_atomic_check( * Dont allocate when active is false. */ if (drm_atomic_crtc_needs_modeset(crtc_state)) { - dpu_rm_release(global_state, drm_enc); + dpu_rm_release(global_state, crtc_state->crtc); =20 if (!crtc_state->active_changed || crtc_state->enable) ret =3D dpu_rm_reserve(&dpu_kms->rm, global_state, - drm_enc, crtc_state, topology); + crtc_state->crtc, topology); } =20 trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags); @@ -1125,14 +1125,14 @@ static void dpu_encoder_virt_atomic_mode_set(struct= drm_encoder *drm_enc, =20 /* Query resource that have been reserved in atomic check step. */ num_pp =3D dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_PINGPONG, hw_pp, + drm_enc->crtc, DPU_HW_BLK_PINGPONG, hw_pp, ARRAY_SIZE(hw_pp)); num_ctl =3D dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); + drm_enc->crtc, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); num_lm =3D dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); + drm_enc->crtc, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_DSPP, hw_dspp, + drm_enc->crtc, DPU_HW_BLK_DSPP, hw_dspp, ARRAY_SIZE(hw_dspp)); =20 for (i =3D 0; i < MAX_CHANNELS_PER_ENC; i++) @@ -1140,7 +1140,7 @@ static void dpu_encoder_virt_atomic_mode_set(struct d= rm_encoder *drm_enc, : NULL; =20 num_dsc =3D dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_DSC, + drm_enc->crtc, DPU_HW_BLK_DSC, hw_dsc, ARRAY_SIZE(hw_dsc)); for (i =3D 0; i < num_dsc; i++) { dpu_enc->hw_dsc[i] =3D to_dpu_hw_dsc(hw_dsc[i]); @@ -1154,7 +1154,7 @@ static void dpu_encoder_virt_atomic_mode_set(struct d= rm_encoder *drm_enc, struct dpu_hw_blk *hw_cdm =3D NULL; =20 dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_CDM, + drm_enc->crtc, DPU_HW_BLK_CDM, &hw_cdm, 1); dpu_enc->cur_master->hw_cdm =3D hw_cdm ? to_dpu_hw_cdm(hw_cdm) : NULL; } @@ -2030,7 +2030,7 @@ static void dpu_encoder_helper_reset_mixers(struct dp= u_encoder_phys *phys_enc) global_state =3D dpu_kms_get_existing_global_state(phys_enc->dpu_kms); =20 num_lm =3D dpu_rm_get_assigned_resources(&phys_enc->dpu_kms->rm, global_s= tate, - phys_enc->parent->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); + phys_enc->parent->crtc, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); =20 for (i =3D 0; i < num_lm; i++) { hw_mixer[i] =3D to_dpu_hw_mixer(hw_lm[i]); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.h index 1952576600575..4f0fa1596b414 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -134,12 +134,12 @@ struct dpu_global_state { =20 struct dpu_rm *rm; =20 - uint32_t pingpong_to_enc_id[PINGPONG_MAX - PINGPONG_0]; - uint32_t mixer_to_enc_id[LM_MAX - LM_0]; - uint32_t ctl_to_enc_id[CTL_MAX - CTL_0]; - uint32_t dspp_to_enc_id[DSPP_MAX - DSPP_0]; - uint32_t dsc_to_enc_id[DSC_MAX - DSC_0]; - uint32_t cdm_to_enc_id; + uint32_t pingpong_to_crtc_id[PINGPONG_MAX - PINGPONG_0]; + uint32_t mixer_to_crtc_id[LM_MAX - LM_0]; + uint32_t ctl_to_crtc_id[CTL_MAX - CTL_0]; + uint32_t dspp_to_crtc_id[DSPP_MAX - DSPP_0]; + uint32_t dsc_to_crtc_id[DSC_MAX - DSC_0]; + uint32_t cdm_to_crtc_id; =20 uint32_t sspp_to_crtc_id[SSPP_MAX - SSPP_NONE]; }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/d= isp/dpu1/dpu_rm.c index 5c9bb64df7930..a6e1eb888f6c8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -21,9 +21,9 @@ =20 =20 static inline bool reserved_by_other(uint32_t *res_map, int idx, - uint32_t enc_id) + uint32_t crtc_id) { - return res_map[idx] && res_map[idx] !=3D enc_id; + return res_map[idx] && res_map[idx] !=3D crtc_id; } =20 /** @@ -225,7 +225,7 @@ static int _dpu_rm_get_lm_peer(struct dpu_rm *rm, int p= rimary_idx) * pingpong * @rm: dpu resource manager handle * @global_state: resources shared across multiple kms objects - * @enc_id: encoder id requesting for allocation + * @crtc_id: crtc id requesting for allocation * @lm_idx: index of proposed layer mixer in rm->mixer_blks[], function ch= ecks * if lm, and all other hardwired blocks connected to the lm (pp) is * available and appropriate @@ -239,14 +239,14 @@ static int _dpu_rm_get_lm_peer(struct dpu_rm *rm, int= primary_idx) */ static bool _dpu_rm_check_lm_and_get_connected_blks(struct dpu_rm *rm, struct dpu_global_state *global_state, - uint32_t enc_id, int lm_idx, int *pp_idx, int *dspp_idx, + uint32_t crtc_id, int lm_idx, int *pp_idx, int *dspp_idx, struct dpu_rm_requirements *reqs) { const struct dpu_lm_cfg *lm_cfg; int idx; =20 /* Already reserved? */ - if (reserved_by_other(global_state->mixer_to_enc_id, lm_idx, enc_id)) { + if (reserved_by_other(global_state->mixer_to_crtc_id, lm_idx, crtc_id)) { DPU_DEBUG("lm %d already reserved\n", lm_idx + LM_0); return false; } @@ -258,7 +258,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(str= uct dpu_rm *rm, return false; } =20 - if (reserved_by_other(global_state->pingpong_to_enc_id, idx, enc_id)) { + if (reserved_by_other(global_state->pingpong_to_crtc_id, idx, crtc_id)) { DPU_DEBUG("lm %d pp %d already reserved\n", lm_cfg->id, lm_cfg->pingpong); return false; @@ -274,7 +274,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(str= uct dpu_rm *rm, return false; } =20 - if (reserved_by_other(global_state->dspp_to_enc_id, idx, enc_id)) { + if (reserved_by_other(global_state->dspp_to_crtc_id, idx, crtc_id)) { DPU_DEBUG("lm %d dspp %d already reserved\n", lm_cfg->id, lm_cfg->dspp); return false; @@ -286,7 +286,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(str= uct dpu_rm *rm, =20 static int _dpu_rm_reserve_lms(struct dpu_rm *rm, struct dpu_global_state *global_state, - uint32_t enc_id, + uint32_t crtc_id, struct dpu_rm_requirements *reqs) =20 { @@ -314,7 +314,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, lm_idx[lm_count] =3D i; =20 if (!_dpu_rm_check_lm_and_get_connected_blks(rm, global_state, - enc_id, i, &pp_idx[lm_count], + crtc_id, i, &pp_idx[lm_count], &dspp_idx[lm_count], reqs)) { continue; } @@ -333,7 +333,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, continue; =20 if (!_dpu_rm_check_lm_and_get_connected_blks(rm, - global_state, enc_id, j, + global_state, crtc_id, j, &pp_idx[lm_count], &dspp_idx[lm_count], reqs)) { continue; @@ -350,13 +350,16 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, } =20 for (i =3D 0; i < lm_count; i++) { - global_state->mixer_to_enc_id[lm_idx[i]] =3D enc_id; - global_state->pingpong_to_enc_id[pp_idx[i]] =3D enc_id; - global_state->dspp_to_enc_id[dspp_idx[i]] =3D - reqs->topology.num_dspp ? enc_id : 0; + global_state->mixer_to_crtc_id[lm_idx[i]] =3D crtc_id; + global_state->pingpong_to_crtc_id[pp_idx[i]] =3D crtc_id; + global_state->dspp_to_crtc_id[dspp_idx[i]] =3D + reqs->topology.num_dspp ? crtc_id : 0; =20 - trace_dpu_rm_reserve_lms(lm_idx[i] + LM_0, enc_id, + trace_dpu_rm_reserve_lms(lm_idx[i] + LM_0, crtc_id, pp_idx[i] + PINGPONG_0); + + DPU_DEBUG("reserve lm[%d]:%d, pp_idx[%d]:%d, dspp[%d]:%d for crtc_id %d\= n", + i, lm_idx[i], i, pp_idx[i], i, dspp_idx[i], crtc_id); } =20 return 0; @@ -365,7 +368,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, static int _dpu_rm_reserve_ctls( struct dpu_rm *rm, struct dpu_global_state *global_state, - uint32_t enc_id, + uint32_t crtc_id, const struct msm_display_topology *top) { int ctl_idx[MAX_BLOCKS]; @@ -389,7 +392,7 @@ static int _dpu_rm_reserve_ctls( =20 if (!rm->ctl_blks[j]) continue; - if (reserved_by_other(global_state->ctl_to_enc_id, j, enc_id)) + if (reserved_by_other(global_state->ctl_to_crtc_id, j, crtc_id)) continue; =20 ctl =3D to_dpu_hw_ctl(rm->ctl_blks[j]); @@ -413,8 +416,8 @@ static int _dpu_rm_reserve_ctls( return -ENAVAIL; =20 for (i =3D 0; i < ARRAY_SIZE(ctl_idx) && i < num_ctls; i++) { - global_state->ctl_to_enc_id[ctl_idx[i]] =3D enc_id; - trace_dpu_rm_reserve_ctls(i + CTL_0, enc_id); + global_state->ctl_to_crtc_id[ctl_idx[i]] =3D crtc_id; + trace_dpu_rm_reserve_ctls(i + CTL_0, crtc_id); } =20 return 0; @@ -422,12 +425,12 @@ static int _dpu_rm_reserve_ctls( =20 static int _dpu_rm_pingpong_next_index(struct dpu_global_state *global_sta= te, int start, - uint32_t enc_id) + uint32_t crtc_id) { int i; =20 for (i =3D start; i < (PINGPONG_MAX - PINGPONG_0); i++) { - if (global_state->pingpong_to_enc_id[i] =3D=3D enc_id) + if (global_state->pingpong_to_crtc_id[i] =3D=3D crtc_id) return i; } =20 @@ -448,7 +451,7 @@ static int _dpu_rm_pingpong_dsc_check(int dsc_idx, int = pp_idx) =20 static int _dpu_rm_dsc_alloc(struct dpu_rm *rm, struct dpu_global_state *global_state, - uint32_t enc_id, + uint32_t crtc_id, const struct msm_display_topology *top) { int num_dsc =3D 0; @@ -461,10 +464,10 @@ static int _dpu_rm_dsc_alloc(struct dpu_rm *rm, if (!rm->dsc_blks[dsc_idx]) continue; =20 - if (reserved_by_other(global_state->dsc_to_enc_id, dsc_idx, enc_id)) + if (reserved_by_other(global_state->dsc_to_crtc_id, dsc_idx, crtc_id)) continue; =20 - pp_idx =3D _dpu_rm_pingpong_next_index(global_state, pp_idx, enc_id); + pp_idx =3D _dpu_rm_pingpong_next_index(global_state, pp_idx, crtc_id); if (pp_idx < 0) return -ENAVAIL; =20 @@ -472,7 +475,7 @@ static int _dpu_rm_dsc_alloc(struct dpu_rm *rm, if (ret) return -ENAVAIL; =20 - global_state->dsc_to_enc_id[dsc_idx] =3D enc_id; + global_state->dsc_to_crtc_id[dsc_idx] =3D crtc_id; num_dsc++; pp_idx++; } @@ -488,7 +491,7 @@ static int _dpu_rm_dsc_alloc(struct dpu_rm *rm, =20 static int _dpu_rm_dsc_alloc_pair(struct dpu_rm *rm, struct dpu_global_state *global_state, - uint32_t enc_id, + uint32_t crtc_id, const struct msm_display_topology *top) { int num_dsc =3D 0; @@ -503,11 +506,11 @@ static int _dpu_rm_dsc_alloc_pair(struct dpu_rm *rm, continue; =20 /* consective dsc index to be paired */ - if (reserved_by_other(global_state->dsc_to_enc_id, dsc_idx, enc_id) || - reserved_by_other(global_state->dsc_to_enc_id, dsc_idx + 1, enc_id)) + if (reserved_by_other(global_state->dsc_to_crtc_id, dsc_idx, crtc_id) || + reserved_by_other(global_state->dsc_to_crtc_id, dsc_idx + 1, crtc_id= )) continue; =20 - pp_idx =3D _dpu_rm_pingpong_next_index(global_state, pp_idx, enc_id); + pp_idx =3D _dpu_rm_pingpong_next_index(global_state, pp_idx, crtc_id); if (pp_idx < 0) return -ENAVAIL; =20 @@ -517,7 +520,7 @@ static int _dpu_rm_dsc_alloc_pair(struct dpu_rm *rm, continue; } =20 - pp_idx =3D _dpu_rm_pingpong_next_index(global_state, pp_idx + 1, enc_id); + pp_idx =3D _dpu_rm_pingpong_next_index(global_state, pp_idx + 1, crtc_id= ); if (pp_idx < 0) return -ENAVAIL; =20 @@ -527,8 +530,8 @@ static int _dpu_rm_dsc_alloc_pair(struct dpu_rm *rm, continue; } =20 - global_state->dsc_to_enc_id[dsc_idx] =3D enc_id; - global_state->dsc_to_enc_id[dsc_idx + 1] =3D enc_id; + global_state->dsc_to_crtc_id[dsc_idx] =3D crtc_id; + global_state->dsc_to_crtc_id[dsc_idx + 1] =3D crtc_id; num_dsc +=3D 2; pp_idx++; /* start for next pair */ } @@ -544,11 +547,9 @@ static int _dpu_rm_dsc_alloc_pair(struct dpu_rm *rm, =20 static int _dpu_rm_reserve_dsc(struct dpu_rm *rm, struct dpu_global_state *global_state, - struct drm_encoder *enc, + uint32_t crtc_id, const struct msm_display_topology *top) { - uint32_t enc_id =3D enc->base.id; - if (!top->num_dsc || !top->num_intf) return 0; =20 @@ -558,22 +559,22 @@ static int _dpu_rm_reserve_dsc(struct dpu_rm *rm, * 2) DSC pair starts from even index, such as index(0,1), (2,3), etc * 3) even PINGPONG connects to even DSC * 4) odd PINGPONG connects to odd DSC - * 5) pair: encoder +--> pp_idx_0 --> dsc_idx_0 + * 5) pair: crtc +--> pp_idx_0 --> dsc_idx_0 * +--> pp_idx_1 --> dsc_idx_1 */ =20 /* num_dsc should be either 1, 2 or 4 */ if (top->num_dsc > top->num_intf) /* merge mode */ - return _dpu_rm_dsc_alloc_pair(rm, global_state, enc_id, top); + return _dpu_rm_dsc_alloc_pair(rm, global_state, crtc_id, top); else - return _dpu_rm_dsc_alloc(rm, global_state, enc_id, top); + return _dpu_rm_dsc_alloc(rm, global_state, crtc_id, top); =20 return 0; } =20 static int _dpu_rm_reserve_cdm(struct dpu_rm *rm, struct dpu_global_state *global_state, - struct drm_encoder *enc) + uint32_t crtc_id) { /* try allocating only one CDM block */ if (!rm->cdm_blk) { @@ -581,12 +582,12 @@ static int _dpu_rm_reserve_cdm(struct dpu_rm *rm, return -EIO; } =20 - if (global_state->cdm_to_enc_id) { + if (global_state->cdm_to_crtc_id) { DPU_ERROR("CDM_0 is already allocated\n"); return -EIO; } =20 - global_state->cdm_to_enc_id =3D enc->base.id; + global_state->cdm_to_crtc_id =3D crtc_id; =20 return 0; } @@ -594,30 +595,30 @@ static int _dpu_rm_reserve_cdm(struct dpu_rm *rm, static int _dpu_rm_make_reservation( struct dpu_rm *rm, struct dpu_global_state *global_state, - struct drm_encoder *enc, + uint32_t crtc_id, struct dpu_rm_requirements *reqs) { int ret; =20 - ret =3D _dpu_rm_reserve_lms(rm, global_state, enc->base.id, reqs); + ret =3D _dpu_rm_reserve_lms(rm, global_state, crtc_id, reqs); if (ret) { DPU_ERROR("unable to find appropriate mixers\n"); return ret; } =20 - ret =3D _dpu_rm_reserve_ctls(rm, global_state, enc->base.id, + ret =3D _dpu_rm_reserve_ctls(rm, global_state, crtc_id, &reqs->topology); if (ret) { DPU_ERROR("unable to find appropriate CTL\n"); return ret; } =20 - ret =3D _dpu_rm_reserve_dsc(rm, global_state, enc, &reqs->topology); + ret =3D _dpu_rm_reserve_dsc(rm, global_state, crtc_id, &reqs->topology); if (ret) return ret; =20 if (reqs->topology.needs_cdm) { - ret =3D _dpu_rm_reserve_cdm(rm, global_state, enc); + ret =3D _dpu_rm_reserve_cdm(rm, global_state, crtc_id); if (ret) { DPU_ERROR("unable to find CDM blk\n"); return ret; @@ -628,7 +629,7 @@ static int _dpu_rm_make_reservation( } =20 static int _dpu_rm_populate_requirements( - struct drm_encoder *enc, + struct drm_crtc *crtc, struct dpu_rm_requirements *reqs, struct msm_display_topology req_topology) { @@ -642,66 +643,59 @@ static int _dpu_rm_populate_requirements( } =20 static void _dpu_rm_clear_mapping(uint32_t *res_mapping, int cnt, - uint32_t enc_id) + uint32_t crtc_id) { int i; =20 for (i =3D 0; i < cnt; i++) { - if (res_mapping[i] =3D=3D enc_id) + if (res_mapping[i] =3D=3D crtc_id) res_mapping[i] =3D 0; } } =20 void dpu_rm_release(struct dpu_global_state *global_state, - struct drm_encoder *enc) + struct drm_crtc *crtc) { - _dpu_rm_clear_mapping(global_state->pingpong_to_enc_id, - ARRAY_SIZE(global_state->pingpong_to_enc_id), enc->base.id); - _dpu_rm_clear_mapping(global_state->mixer_to_enc_id, - ARRAY_SIZE(global_state->mixer_to_enc_id), enc->base.id); - _dpu_rm_clear_mapping(global_state->ctl_to_enc_id, - ARRAY_SIZE(global_state->ctl_to_enc_id), enc->base.id); - _dpu_rm_clear_mapping(global_state->dsc_to_enc_id, - ARRAY_SIZE(global_state->dsc_to_enc_id), enc->base.id); - _dpu_rm_clear_mapping(global_state->dspp_to_enc_id, - ARRAY_SIZE(global_state->dspp_to_enc_id), enc->base.id); - _dpu_rm_clear_mapping(&global_state->cdm_to_enc_id, 1, enc->base.id); + uint32_t crtc_id =3D crtc->base.id; + + _dpu_rm_clear_mapping(global_state->pingpong_to_crtc_id, + ARRAY_SIZE(global_state->pingpong_to_crtc_id), crtc_id); + _dpu_rm_clear_mapping(global_state->mixer_to_crtc_id, + ARRAY_SIZE(global_state->mixer_to_crtc_id), crtc_id); + _dpu_rm_clear_mapping(global_state->ctl_to_crtc_id, + ARRAY_SIZE(global_state->ctl_to_crtc_id), crtc_id); + _dpu_rm_clear_mapping(global_state->dsc_to_crtc_id, + ARRAY_SIZE(global_state->dsc_to_crtc_id), crtc_id); + _dpu_rm_clear_mapping(global_state->dspp_to_crtc_id, + ARRAY_SIZE(global_state->dspp_to_crtc_id), crtc_id); } =20 int dpu_rm_reserve( struct dpu_rm *rm, struct dpu_global_state *global_state, - struct drm_encoder *enc, - struct drm_crtc_state *crtc_state, + struct drm_crtc *crtc, struct msm_display_topology topology) { struct dpu_rm_requirements reqs; int ret; =20 - /* Check if this is just a page-flip */ - if (!drm_atomic_crtc_needs_modeset(crtc_state)) - return 0; - if (IS_ERR(global_state)) { DPU_ERROR("failed to global state\n"); return PTR_ERR(global_state); } =20 - DRM_DEBUG_KMS("reserving hw for enc %d crtc %d\n", - enc->base.id, crtc_state->crtc->base.id); + DRM_DEBUG_KMS("reserving hw for crtc %d\n", crtc->base.id); =20 - ret =3D _dpu_rm_populate_requirements(enc, &reqs, topology); + ret =3D _dpu_rm_populate_requirements(crtc, &reqs, topology); if (ret) { DPU_ERROR("failed to populate hw requirements\n"); return ret; } =20 - ret =3D _dpu_rm_make_reservation(rm, global_state, enc, &reqs); + ret =3D _dpu_rm_make_reservation(rm, global_state, crtc->base.id, &reqs); if (ret) DPU_ERROR("failed to reserve hw resources: %d\n", ret); =20 - - return ret; } =20 @@ -798,42 +792,43 @@ static char *dpu_hw_blk_type_name[] =3D { }; =20 int dpu_rm_get_assigned_resources(struct dpu_rm *rm, - struct dpu_global_state *global_state, uint32_t enc_id, + struct dpu_global_state *global_state, struct drm_crtc *crtc, enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size) { + uint32_t crtc_id =3D crtc->base.id; struct dpu_hw_blk **hw_blks; - uint32_t *hw_to_enc_id; + uint32_t *hw_to_crtc_id; int i, num_blks, max_blks; =20 switch (type) { case DPU_HW_BLK_PINGPONG: hw_blks =3D rm->pingpong_blks; - hw_to_enc_id =3D global_state->pingpong_to_enc_id; + hw_to_crtc_id =3D global_state->pingpong_to_crtc_id; max_blks =3D ARRAY_SIZE(rm->pingpong_blks); break; case DPU_HW_BLK_LM: hw_blks =3D rm->mixer_blks; - hw_to_enc_id =3D global_state->mixer_to_enc_id; + hw_to_crtc_id =3D global_state->mixer_to_crtc_id; max_blks =3D ARRAY_SIZE(rm->mixer_blks); break; case DPU_HW_BLK_CTL: hw_blks =3D rm->ctl_blks; - hw_to_enc_id =3D global_state->ctl_to_enc_id; + hw_to_crtc_id =3D global_state->ctl_to_crtc_id; max_blks =3D ARRAY_SIZE(rm->ctl_blks); break; case DPU_HW_BLK_DSPP: hw_blks =3D rm->dspp_blks; - hw_to_enc_id =3D global_state->dspp_to_enc_id; + hw_to_crtc_id =3D global_state->dspp_to_crtc_id; max_blks =3D ARRAY_SIZE(rm->dspp_blks); break; case DPU_HW_BLK_DSC: hw_blks =3D rm->dsc_blks; - hw_to_enc_id =3D global_state->dsc_to_enc_id; + hw_to_crtc_id =3D global_state->dsc_to_crtc_id; max_blks =3D ARRAY_SIZE(rm->dsc_blks); break; case DPU_HW_BLK_CDM: hw_blks =3D &rm->cdm_blk; - hw_to_enc_id =3D &global_state->cdm_to_enc_id; + hw_to_crtc_id =3D &global_state->cdm_to_crtc_id; max_blks =3D 1; break; default: @@ -843,17 +838,17 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm, =20 num_blks =3D 0; for (i =3D 0; i < max_blks; i++) { - if (hw_to_enc_id[i] !=3D enc_id) + if (hw_to_crtc_id[i] !=3D crtc_id) continue; =20 if (num_blks =3D=3D blks_size) { - DPU_ERROR("More than %d %s assigned to enc %d\n", - blks_size, dpu_hw_blk_type_name[type], enc_id); + DPU_ERROR("More than %d resources assigned to crtc %d\n", + blks_size, crtc_id); break; } if (!hw_blks[i]) { - DPU_ERROR("%s unavailable to assign to enc %d\n", - dpu_hw_blk_type_name[type], enc_id); + DPU_ERROR("%s unavailable to assign to crtc %d\n", + dpu_hw_blk_type_name[type], crtc_id); break; } blks[num_blks++] =3D hw_blks[i]; @@ -883,38 +878,38 @@ void dpu_rm_print_state(struct drm_printer *p, =20 drm_puts(p, "resource mapping:\n"); drm_puts(p, "\tpingpong=3D"); - for (i =3D 0; i < ARRAY_SIZE(global_state->pingpong_to_enc_id); i++) + for (i =3D 0; i < ARRAY_SIZE(global_state->pingpong_to_crtc_id); i++) dpu_rm_print_state_helper(p, rm->pingpong_blks[i], - global_state->pingpong_to_enc_id[i]); + global_state->pingpong_to_crtc_id[i]); drm_puts(p, "\n"); =20 drm_puts(p, "\tmixer=3D"); - for (i =3D 0; i < ARRAY_SIZE(global_state->mixer_to_enc_id); i++) + for (i =3D 0; i < ARRAY_SIZE(global_state->mixer_to_crtc_id); i++) dpu_rm_print_state_helper(p, rm->mixer_blks[i], - global_state->mixer_to_enc_id[i]); + global_state->mixer_to_crtc_id[i]); drm_puts(p, "\n"); =20 drm_puts(p, "\tctl=3D"); - for (i =3D 0; i < ARRAY_SIZE(global_state->ctl_to_enc_id); i++) + for (i =3D 0; i < ARRAY_SIZE(global_state->ctl_to_crtc_id); i++) dpu_rm_print_state_helper(p, rm->ctl_blks[i], - global_state->ctl_to_enc_id[i]); + global_state->ctl_to_crtc_id[i]); drm_puts(p, "\n"); =20 drm_puts(p, "\tdspp=3D"); - for (i =3D 0; i < ARRAY_SIZE(global_state->dspp_to_enc_id); i++) + for (i =3D 0; i < ARRAY_SIZE(global_state->dspp_to_crtc_id); i++) dpu_rm_print_state_helper(p, rm->dspp_blks[i], - global_state->dspp_to_enc_id[i]); + global_state->dspp_to_crtc_id[i]); drm_puts(p, "\n"); =20 drm_puts(p, "\tdsc=3D"); - for (i =3D 0; i < ARRAY_SIZE(global_state->dsc_to_enc_id); i++) + for (i =3D 0; i < ARRAY_SIZE(global_state->dsc_to_crtc_id); i++) dpu_rm_print_state_helper(p, rm->dsc_blks[i], - global_state->dsc_to_enc_id[i]); + global_state->dsc_to_crtc_id[i]); drm_puts(p, "\n"); =20 drm_puts(p, "\tcdm=3D"); dpu_rm_print_state_helper(p, rm->cdm_blk, - global_state->cdm_to_enc_id); + global_state->cdm_to_crtc_id); drm_puts(p, "\n"); =20 drm_puts(p, "\tsspp=3D"); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/d= isp/dpu1/dpu_rm.h index c51c5a9255ce6..720e2c64effbf 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -68,26 +68,25 @@ int dpu_rm_init(struct drm_device *dev, * HW blocks can then be accessed through dpu_rm_get_* functions. * HW Reservations should be released via dpu_rm_release_hw. * @rm: DPU Resource Manager handle - * @drm_enc: DRM Encoder handle - * @crtc_state: Proposed Atomic DRM CRTC State handle + * @crtc: DRM CRTC handle * @topology: Pointer to topology info for the display * @Return: 0 on Success otherwise -ERROR */ -int dpu_rm_reserve(struct dpu_rm *rm, +int dpu_rm_reserve( + struct dpu_rm *rm, struct dpu_global_state *global_state, - struct drm_encoder *drm_enc, - struct drm_crtc_state *crtc_state, + struct drm_crtc *crtc, struct msm_display_topology topology); =20 /** - * dpu_rm_reserve - Given the encoder for the display chain, release any + * dpu_rm_reserve - Given the crtc for the display chain, release any * HW blocks previously reserved for that use case. * @rm: DPU Resource Manager handle - * @enc: DRM Encoder handle + * @crtc: DRM CRTC handle * @Return: 0 on Success otherwise -ERROR */ void dpu_rm_release(struct dpu_global_state *global_state, - struct drm_encoder *enc); + struct drm_crtc *crtc); =20 /** * dpu_rm_reserve_sspp - Reserve the required SSPP for the provided CRTC @@ -111,10 +110,10 @@ void dpu_rm_release_all_sspp(struct dpu_global_state = *global_state, struct drm_crtc *crtc); =20 /** - * Get hw resources of the given type that are assigned to this encoder. + * Get hw resources of the given type that are assigned to this crtc. */ int dpu_rm_get_assigned_resources(struct dpu_rm *rm, - struct dpu_global_state *global_state, uint32_t enc_id, + struct dpu_global_state *global_state, struct drm_crtc *crtc, enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size); =20 /** --=20 2.34.1 From nobody Wed Nov 27 14:32:38 2024 Received: from mail-pg1-f181.google.com (mail-pg1-f181.google.com [209.85.215.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A15418EFD6 for ; Wed, 9 Oct 2024 08:50:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728463853; cv=none; b=VYukxy+dVLFsEkiPSogVoFuMUPLdia3hIwi2fWCqqMZnaUvaRji3IFEpw6uXqEPgM3vJEkKH+EWeEfSlhjBBXUlnsIiNsNyNaCjZKpGKXWaI/nVsewlI+9qr4uj55xWCMSyMG1RzHe7SENO8Yw0tDwx1Jpr5cBx5lpDwf9b5zI0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728463853; c=relaxed/simple; bh=opSjxUTcPLTf/RJF/yohmnhWqOovHSpTlisf/okttJs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QeWglr7PknGiR409hHYFv2wbKaS8+A7PbvODGM3UHj7y9E9RZpE3783Lc8+APmcDjwibsGNjnNdZZVFSH7EoRbkeX3gk797SegjDbduwJIY/OgjXbbUK6X75/RSkWQC9edcEFYMl4tnyLnxaOSFoekzSzy6HinQyx7g1yOFCoNg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=GrF5owYC; arc=none smtp.client-ip=209.85.215.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="GrF5owYC" Received: by mail-pg1-f181.google.com with SMTP id 41be03b00d2f7-7e9ff6fb4c6so5154746a12.3 for ; Wed, 09 Oct 2024 01:50:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728463850; x=1729068650; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=IJDRx4c02GV86ldvKHRV1BWPMQm206AuMFT5TG5pzZk=; b=GrF5owYCfoYUJBAcd2v76X4PLdM85fJJvh7GHdNWQPUbvSqDBZS34vmfwgQ6NEjbGu VeG6KkZTvmbiM1T4N8wk/JmSuV27X/FoA1V3IA928NkNsd1MhWZG9q8scJsCv07lb2Pd 16km8Pv1061V7S7ZPjTbZRs7Qv2icIwvLUBOCS9ys6ra9TKWNk8N3Nevs5lySRGxKGlu cqtbsWhMwG5OpD/YBHsp9G5uWu+v2LvrTQ8rQ00yHGyVB+SNLwLDl9n5OpwuMMOImHSd w+CkmDJaQ2OUrqUpZRA8IzTNAOSqUqKJALQeUykH+vpgckU2wJIKQVtnVnYyWT+6NleI lsPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728463850; x=1729068650; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IJDRx4c02GV86ldvKHRV1BWPMQm206AuMFT5TG5pzZk=; b=f4KxkL+KgH0dGDbhu24ycycPc7RH7emEh6jJFhl6MC3dwJTeaDm5KeR9LNI5Z4CoUa HqoRkITbL40B9RngUPtUK0brMRTrgCYZnWD1dHWJQbkFIWvEPE/A1n+uRYlUdTuiCTnQ FKhXz7Ax8d5ErpooiqOkHZTSUTxGCBNvkIqniPKYmaMIl81am5adXJ4jBO0Tc3AFhauf 7oKMsJ+my5LScJwIRVh44rf3u5tRmtZWEITsMKy1pKQ+ryKp+NOk9AE7yIb6/wsLyOjV GwkDfj+muSyGPoKBVu4LuN81rz+1XGtHQ6vMxSxthA/7sHL2ygAWg1hGvfPILki/XhBe deJQ== X-Forwarded-Encrypted: i=1; AJvYcCXiOEgfjTjKjm9b3i7QjVVYYjeCUPnFCtcQ5JvFJV2HRqhwUHEywQAP4emm+REviTmZMampX4lRk4GIaks=@vger.kernel.org X-Gm-Message-State: AOJu0YyJdlIP0W4ogAvWGkxyfSD4QnAcf/24ZL2zLqSFrRxvFHh3pgDE H5b/wJ2Hx6FEYLOSMjgm9KRFxO3C8G4ADk0bvX+8gTJeZXSyD2Wxuaz7gSRtYvY= X-Google-Smtp-Source: AGHT+IF+L9jruoxAxge2I9Ue+gETiz0ghYX4QgsAWI8h/xKj1ECDICKwUX5gMAamzfVQ4Q+dxnHnXA== X-Received: by 2002:a17:90a:348c:b0:2e2:af04:8b64 with SMTP id 98e67ed59e1d1-2e2af048bb1mr1177331a91.7.1728463850333; Wed, 09 Oct 2024 01:50:50 -0700 (PDT) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2abad236esm898157a91.10.2024.10.09.01.50.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 01:50:50 -0700 (PDT) From: Jun Nie Date: Wed, 09 Oct 2024 16:50:18 +0800 Subject: [PATCH v2 05/14] drm/msm/dpu: handle pipes as array Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-5-76d4f5d413bf@linaro.org> References: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> In-Reply-To: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728463820; l=18729; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=opSjxUTcPLTf/RJF/yohmnhWqOovHSpTlisf/okttJs=; b=GJVfYJ44MnX9Zte1yJNawKCyG2T7ZoiGDT+QdS1St4HAN9VNcf3Rcs+olwHjbskGfePd+1axT Q08J7fKuc/DC4n5CxRyPbDpJXOkB1HmcIl4X3Ev1lrIMHPIFmS9/UIT X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Store pipes in array with removing dedicated r_pipe. There are 2 pipes in a drm plane at most currently. While 4 pipes are needed for new usage case. This change generalize the handling to pipe pair and ease handling to another pipe pair later. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 34 +++--- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 167 ++++++++++++++++----------= ---- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 12 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 10 +- 4 files changed, 111 insertions(+), 112 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 3e0e6e9757da5..9656b1df0f122 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -411,7 +411,7 @@ static void _dpu_crtc_blend_setup_pipe(struct drm_crtc = *crtc, =20 trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane), state, to_dpu_plane_state(state), stage_idx, - format->pixel_format, + format->pixel_format, pipe, modifier); =20 DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d multirect_idx= %d\n", @@ -442,7 +442,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, const struct msm_format *format; struct dpu_hw_ctl *ctl =3D mixer->lm_ctl; =20 - uint32_t lm_idx; + uint32_t lm_idx, i; bool bg_alpha_enable =3D false; DECLARE_BITMAP(fetch_active, SSPP_MAX); =20 @@ -463,20 +463,15 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_cr= tc *crtc, if (pstate->stage =3D=3D DPU_STAGE_BASE && format->alpha_enable) bg_alpha_enable =3D true; =20 - set_bit(pstate->pipe.sspp->idx, fetch_active); - _dpu_crtc_blend_setup_pipe(crtc, plane, - mixer, cstate->num_mixers, - pstate->stage, - format, fb ? fb->modifier : 0, - &pstate->pipe, 0, stage_cfg); - - if (pstate->r_pipe.sspp) { - set_bit(pstate->r_pipe.sspp->idx, fetch_active); + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + if (!pstate->pipe[i].sspp) + continue; + set_bit(pstate->pipe[i].sspp->idx, fetch_active); _dpu_crtc_blend_setup_pipe(crtc, plane, mixer, cstate->num_mixers, pstate->stage, format, fb ? fb->modifier : 0, - &pstate->r_pipe, 1, stage_cfg); + &pstate->pipe[i], i, stage_cfg); } =20 /* blend config update */ @@ -1387,15 +1382,12 @@ static int _dpu_debugfs_status_show(struct seq_file= *s, void *data) seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n", state->crtc_x, state->crtc_y, state->crtc_w, state->crtc_h); - seq_printf(s, "\tsspp[0]:%s\n", - pstate->pipe.sspp->cap->name); - seq_printf(s, "\tmultirect[0]: mode: %d index: %d\n", - pstate->pipe.multirect_mode, pstate->pipe.multirect_index); - if (pstate->r_pipe.sspp) { - seq_printf(s, "\tsspp[1]:%s\n", - pstate->r_pipe.sspp->cap->name); - seq_printf(s, "\tmultirect[1]: mode: %d index: %d\n", - pstate->r_pipe.multirect_mode, pstate->r_pipe.multirect_index); + if (pstate->pipe[i].sspp) { + seq_printf(s, "\tsspp[%d]:%s\n", + i, pstate->pipe[i].sspp->cap->name); + seq_printf(s, "\tmultirect[%d]: mode: %d index: %d\n", + i, pstate->pipe[i].multirect_mode, + pstate->pipe[i].multirect_index); } =20 seq_puts(s, "\n"); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index 4df7cfed4d230..e7006fb8c7734 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -429,7 +429,7 @@ static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp= *pipe_hw, uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v, unsigned int rotation) { - uint32_t i; + int i; bool inline_rotation =3D rotation & DRM_MODE_ROTATE_90; =20 /* @@ -619,6 +619,7 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdp= u, struct msm_drm_private *priv =3D plane->dev->dev_private; struct dpu_plane_state *pstate =3D to_dpu_plane_state(plane->state); u32 fill_color =3D (color & 0xFFFFFF) | ((alpha & 0xFF) << 24); + int i; =20 DPU_DEBUG_PLANE(pdpu, "\n"); =20 @@ -632,12 +633,12 @@ static void _dpu_plane_color_fill(struct dpu_plane *p= dpu, return; =20 /* update sspp */ - _dpu_plane_color_fill_pipe(pstate, &pstate->pipe, &pstate->pipe_cfg.dst_r= ect, - fill_color, fmt); - - if (pstate->r_pipe.sspp) - _dpu_plane_color_fill_pipe(pstate, &pstate->r_pipe, &pstate->r_pipe_cfg.= dst_rect, - fill_color, fmt); + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + if (pstate->pipe[i].sspp) + _dpu_plane_color_fill_pipe(pstate, &pstate->pipe[i], + &pstate->pipe_cfg[i].dst_rect, + fill_color, fmt); + } } =20 static int dpu_plane_prepare_fb(struct drm_plane *plane, @@ -808,8 +809,8 @@ static int dpu_plane_atomic_check_nopipe(struct drm_pla= ne *plane, struct dpu_kms *kms =3D _dpu_plane_get_kms(&pdpu->base); u64 max_mdp_clk_rate =3D kms->perf.max_core_clk_rate; struct dpu_plane_state *pstate =3D to_dpu_plane_state(new_plane_state); - struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->r_pipe_cfg; + struct dpu_sw_pipe_cfg *pipe_cfg; + struct dpu_sw_pipe_cfg *r_pipe_cfg; struct drm_rect fb_rect =3D { 0 }; uint32_t max_linewidth; =20 @@ -834,6 +835,9 @@ static int dpu_plane_atomic_check_nopipe(struct drm_pla= ne *plane, return -EINVAL; } =20 + /* move the assignment here, to ease handling to another pairs later */ + pipe_cfg =3D &pstate->pipe_cfg[0]; + r_pipe_cfg =3D &pstate->pipe_cfg[1]; /* state->src is 16.16, src_rect is not */ drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src); =20 @@ -916,11 +920,11 @@ static int dpu_plane_atomic_check_pipes(struct drm_pl= ane *plane, drm_atomic_get_new_plane_state(state, plane); struct dpu_plane *pdpu =3D to_dpu_plane(plane); struct dpu_plane_state *pstate =3D to_dpu_plane_state(new_plane_state); - struct dpu_sw_pipe *pipe =3D &pstate->pipe; - struct dpu_sw_pipe *r_pipe =3D &pstate->r_pipe; const struct msm_format *fmt; - struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->r_pipe_cfg; + struct dpu_sw_pipe *pipe =3D &pstate->pipe[0]; + struct dpu_sw_pipe *r_pipe =3D &pstate->pipe[1]; + struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg[0]; + struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->pipe_cfg[1]; uint32_t supported_rotations; const struct dpu_sspp_cfg *pipe_hw_caps; const struct dpu_sspp_sub_blks *sblk; @@ -975,10 +979,10 @@ static int dpu_plane_atomic_check(struct drm_plane *p= lane, struct dpu_plane *pdpu =3D to_dpu_plane(plane); struct dpu_plane_state *pstate =3D to_dpu_plane_state(new_plane_state); struct dpu_kms *dpu_kms =3D _dpu_plane_get_kms(plane); - struct dpu_sw_pipe *pipe =3D &pstate->pipe; - struct dpu_sw_pipe *r_pipe =3D &pstate->r_pipe; - struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->r_pipe_cfg; + struct dpu_sw_pipe *pipe =3D &pstate->pipe[0]; + struct dpu_sw_pipe *r_pipe =3D &pstate->pipe[1]; + struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg[0]; + struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->pipe_cfg[1]; const struct drm_crtc_state *crtc_state =3D NULL; =20 if (new_plane_state->crtc) @@ -1056,7 +1060,7 @@ static int dpu_plane_virtual_atomic_check(struct drm_= plane *plane, drm_atomic_get_old_plane_state(state, plane); struct dpu_plane_state *pstate =3D to_dpu_plane_state(plane_state); struct drm_crtc_state *crtc_state; - int ret; + int ret, i; =20 if (plane_state->crtc) crtc_state =3D drm_atomic_get_new_crtc_state(state, @@ -1071,8 +1075,8 @@ static int dpu_plane_virtual_atomic_check(struct drm_= plane *plane, * resources are freed by dpu_crtc_assign_plane_resources(), * but clean them here. */ - pstate->pipe.sspp =3D NULL; - pstate->r_pipe.sspp =3D NULL; + for (i =3D 0; i < PIPES_PER_STAGE; i++) + pstate->pipe[i].sspp =3D NULL; =20 return 0; } @@ -1110,19 +1114,22 @@ static int dpu_plane_virtual_assign_resources(struc= t drm_crtc *crtc, struct dpu_sw_pipe_cfg *r_pipe_cfg; const struct msm_format *fmt; uint32_t max_linewidth; + int i; =20 if (plane_state->crtc) crtc_state =3D drm_atomic_get_new_crtc_state(state, plane_state->crtc); =20 pstate =3D to_dpu_plane_state(plane_state); - pipe =3D &pstate->pipe; - r_pipe =3D &pstate->r_pipe; - pipe_cfg =3D &pstate->pipe_cfg; - r_pipe_cfg =3D &pstate->r_pipe_cfg; =20 - pipe->sspp =3D NULL; - r_pipe->sspp =3D NULL; + /* loop below code for another pair later */ + pipe =3D &pstate->pipe[0]; + r_pipe =3D &pstate->pipe[1]; + pipe_cfg =3D &pstate->pipe_cfg[0]; + r_pipe_cfg =3D &pstate->pipe_cfg[1]; + + for (i =3D 0; i < PIPES_PER_STAGE; i++) + pstate->pipe[i].sspp =3D NULL; =20 if (!plane_state->fb) return -EINVAL; @@ -1228,6 +1235,7 @@ void dpu_plane_flush(struct drm_plane *plane) { struct dpu_plane *pdpu; struct dpu_plane_state *pstate; + int i; =20 if (!plane || !plane->state) { DPU_ERROR("invalid plane\n"); @@ -1248,8 +1256,8 @@ void dpu_plane_flush(struct drm_plane *plane) /* force 100% alpha */ _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); else { - dpu_plane_flush_csc(pdpu, &pstate->pipe); - dpu_plane_flush_csc(pdpu, &pstate->r_pipe); + for (i =3D 0; i < PIPES_PER_STAGE; i++) + dpu_plane_flush_csc(pdpu, &pstate->pipe[i]); } =20 /* flag h/w flush complete */ @@ -1349,20 +1357,16 @@ static void dpu_plane_sspp_atomic_update(struct drm= _plane *plane) struct dpu_plane *pdpu =3D to_dpu_plane(plane); struct drm_plane_state *state =3D plane->state; struct dpu_plane_state *pstate =3D to_dpu_plane_state(state); - struct dpu_sw_pipe *pipe =3D &pstate->pipe; - struct dpu_sw_pipe *r_pipe =3D &pstate->r_pipe; struct drm_crtc *crtc =3D state->crtc; struct drm_framebuffer *fb =3D state->fb; bool is_rt_pipe; const struct msm_format *fmt =3D msm_framebuffer_format(fb); - struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->r_pipe_cfg; struct dpu_kms *kms =3D _dpu_plane_get_kms(&pdpu->base); struct msm_gem_address_space *aspace =3D kms->base.aspace; struct dpu_hw_fmt_layout layout; bool layout_valid =3D false; - int ret; + int ret, i; =20 ret =3D dpu_format_populate_layout(aspace, fb, &layout); if (ret) @@ -1381,12 +1385,12 @@ static void dpu_plane_sspp_atomic_update(struct drm= _plane *plane) crtc->base.id, DRM_RECT_ARG(&state->dst), &fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt)); =20 - dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt, - drm_mode_vrefresh(&crtc->mode), - layout_valid ? &layout : NULL); - - if (r_pipe->sspp) { - dpu_plane_sspp_update_pipe(plane, r_pipe, r_pipe_cfg, fmt, + /* move the assignment here, to ease handling to another pairs later */ + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + if (!pstate->pipe[i].sspp) + continue; + dpu_plane_sspp_update_pipe(plane, &pstate->pipe[i], + &pstate->pipe_cfg[i], fmt, drm_mode_vrefresh(&crtc->mode), layout_valid ? &layout : NULL); } @@ -1394,15 +1398,17 @@ static void dpu_plane_sspp_atomic_update(struct drm= _plane *plane) if (pstate->needs_qos_remap) pstate->needs_qos_remap =3D false; =20 - pstate->plane_fetch_bw =3D _dpu_plane_calc_bw(pdpu->catalog, fmt, - &crtc->mode, pipe_cfg); - - pstate->plane_clk =3D _dpu_plane_calc_clk(&crtc->mode, pipe_cfg); - - if (r_pipe->sspp) { - pstate->plane_fetch_bw +=3D _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc= ->mode, r_pipe_cfg); + pstate->plane_fetch_bw =3D 0; + pstate->plane_clk =3D 0; + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + if (!pstate->pipe[i].sspp) + continue; + pstate->plane_fetch_bw +=3D _dpu_plane_calc_bw(pdpu->catalog, fmt, + &crtc->mode, &pstate->pipe_cfg[i]); =20 - pstate->plane_clk =3D max(pstate->plane_clk, _dpu_plane_calc_clk(&crtc->= mode, r_pipe_cfg)); + pstate->plane_clk =3D max(pstate->plane_clk, + _dpu_plane_calc_clk(&crtc->mode, + &pstate->pipe_cfg[i])); } } =20 @@ -1410,17 +1416,24 @@ static void _dpu_plane_atomic_disable(struct drm_pl= ane *plane) { struct drm_plane_state *state =3D plane->state; struct dpu_plane_state *pstate =3D to_dpu_plane_state(state); - struct dpu_sw_pipe *r_pipe =3D &pstate->r_pipe; + struct dpu_sw_pipe *pipe; + int i; + + for (i =3D 0; i < PIPES_PER_STAGE; i +=3D 1) { + pipe =3D &pstate->pipe[i]; + if (!pipe->sspp) + continue; =20 - trace_dpu_plane_disable(DRMID(plane), false, - pstate->pipe.multirect_mode); + trace_dpu_plane_disable(DRMID(plane), false, + pstate->pipe[i].multirect_mode); =20 - if (r_pipe->sspp) { - r_pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + if (pipe->sspp && pipe->multirect_index =3D=3D DPU_SSPP_RECT_1) { + pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; + pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; =20 - if (r_pipe->sspp->ops.setup_multirect) - r_pipe->sspp->ops.setup_multirect(r_pipe); + if (pipe->sspp->ops.setup_multirect) + pipe->sspp->ops.setup_multirect(pipe); + } } =20 pstate->pending =3D true; @@ -1515,30 +1528,26 @@ static void dpu_plane_atomic_print_state(struct drm= _printer *p, const struct drm_plane_state *state) { const struct dpu_plane_state *pstate =3D to_dpu_plane_state(state); - const struct dpu_sw_pipe *pipe =3D &pstate->pipe; - const struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg; - const struct dpu_sw_pipe *r_pipe =3D &pstate->r_pipe; - const struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->r_pipe_cfg; + const struct dpu_sw_pipe *pipe; + const struct dpu_sw_pipe_cfg *pipe_cfg; + int i; =20 drm_printf(p, "\tstage=3D%d\n", pstate->stage); =20 - if (pipe->sspp) { - drm_printf(p, "\tsspp[0]=3D%s\n", pipe->sspp->cap->name); - drm_printf(p, "\tmultirect_mode[0]=3D%s\n", dpu_get_multirect_mode(pipe-= >multirect_mode)); - drm_printf(p, "\tmultirect_index[0]=3D%s\n", + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + pipe =3D &pstate->pipe[i]; + if (!pipe->sspp) + continue; + pipe_cfg =3D &pstate->pipe_cfg[i]; + drm_printf(p, "\tsspp[%d]=3D%s\n", i, pipe->sspp->cap->name); + drm_printf(p, "\tmultirect_mode[%d]=3D%s\n", i, + dpu_get_multirect_mode(pipe->multirect_mode)); + drm_printf(p, "\tmultirect_index[%d]=3D%s\n", i, dpu_get_multirect_index(pipe->multirect_index)); - drm_printf(p, "\tsrc[0]=3D" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->s= rc_rect)); - drm_printf(p, "\tdst[0]=3D" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->d= st_rect)); - } - - if (r_pipe->sspp) { - drm_printf(p, "\tsspp[1]=3D%s\n", r_pipe->sspp->cap->name); - drm_printf(p, "\tmultirect_mode[1]=3D%s\n", - dpu_get_multirect_mode(r_pipe->multirect_mode)); - drm_printf(p, "\tmultirect_index[1]=3D%s\n", - dpu_get_multirect_index(r_pipe->multirect_index)); - drm_printf(p, "\tsrc[1]=3D" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg-= >src_rect)); - drm_printf(p, "\tdst[1]=3D" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg-= >dst_rect)); + drm_printf(p, "\tsrc[%d]=3D" DRM_RECT_FMT "\n", i, + DRM_RECT_ARG(&pipe_cfg->src_rect)); + drm_printf(p, "\tdst[%d]=3D" DRM_RECT_FMT "\n", i, + DRM_RECT_ARG(&pipe_cfg->dst_rect)); } } =20 @@ -1576,14 +1585,16 @@ void dpu_plane_danger_signal_ctrl(struct drm_plane = *plane, bool enable) struct dpu_plane *pdpu =3D to_dpu_plane(plane); struct dpu_plane_state *pstate =3D to_dpu_plane_state(plane->state); struct dpu_kms *dpu_kms =3D _dpu_plane_get_kms(plane); + int i; =20 if (!pdpu->is_rt_pipe) return; =20 pm_runtime_get_sync(&dpu_kms->pdev->dev); - _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, enable); - if (pstate->r_pipe.sspp) - _dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, enable); + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + if (pstate->pipe[i].sspp) + _dpu_plane_set_qos_ctrl(plane, &pstate->pipe[i], enable); + } pm_runtime_put_sync(&dpu_kms->pdev->dev); } #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.h index e225d5baceb09..39945e0d1b851 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -18,10 +18,8 @@ * struct dpu_plane_state: Define dpu extension of drm plane state object * @base: base drm plane state object * @aspace: pointer to address space for input/output buffers - * @pipe: software pipe description - * @r_pipe: software pipe description of the second pipe - * @pipe_cfg: software pipe configuration - * @r_pipe_cfg: software pipe configuration for the second pipe + * @pipe: software pipe description array + * @pipe_cfg: software pipe configuration array * @stage: assigned by crtc blender * @needs_qos_remap: qos remap settings need to be updated * @multirect_index: index of the rectangle of SSPP @@ -34,10 +32,8 @@ struct dpu_plane_state { struct drm_plane_state base; struct msm_gem_address_space *aspace; - struct dpu_sw_pipe pipe; - struct dpu_sw_pipe r_pipe; - struct dpu_sw_pipe_cfg pipe_cfg; - struct dpu_sw_pipe_cfg r_pipe_cfg; + struct dpu_sw_pipe pipe[PIPES_PER_STAGE]; + struct dpu_sw_pipe_cfg pipe_cfg[PIPES_PER_STAGE]; enum dpu_stage stage; bool needs_qos_remap; bool pending; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_trace.h index 5307cbc2007c5..cb24ad2a6d8d3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h @@ -651,9 +651,9 @@ TRACE_EVENT(dpu_crtc_setup_mixer, TP_PROTO(uint32_t crtc_id, uint32_t plane_id, struct drm_plane_state *state, struct dpu_plane_state *pstate, uint32_t stage_idx, uint32_t pixel_format, - uint64_t modifier), + struct dpu_sw_pipe *pipe, uint64_t modifier), TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx, - pixel_format, modifier), + pixel_format, pipe, modifier), TP_STRUCT__entry( __field( uint32_t, crtc_id ) __field( uint32_t, plane_id ) @@ -676,9 +676,9 @@ TRACE_EVENT(dpu_crtc_setup_mixer, __entry->dst_rect =3D drm_plane_state_dest(state); __entry->stage_idx =3D stage_idx; __entry->stage =3D pstate->stage; - __entry->sspp =3D pstate->pipe.sspp->idx; - __entry->multirect_idx =3D pstate->pipe.multirect_index; - __entry->multirect_mode =3D pstate->pipe.multirect_mode; + __entry->sspp =3D pipe->sspp->idx; + __entry->multirect_idx =3D pipe->multirect_index; + __entry->multirect_mode =3D pipe->multirect_mode; __entry->pixel_format =3D pixel_format; __entry->modifier =3D modifier; ), --=20 2.34.1 From nobody Wed Nov 27 14:32:38 2024 Received: from mail-pj1-f41.google.com (mail-pj1-f41.google.com [209.85.216.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F99B19048A for ; Wed, 9 Oct 2024 08:50:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728463858; cv=none; b=OiF2LMNfX8I5tPwrzTelY4MMtjE6GUO+qRC4VwUbdGbSbxYR8RRwUbpYgv3lz+txZRHRl8sHwLsnML7u6I8kigtuYkEvsO5WUAjRaRgeWl4roh5Yzy/H2JEDfCEjGobozEYh5GPGBA5oPCk7Xvf2XmwgznvH/EyNMzQoOVW/fSo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728463858; c=relaxed/simple; bh=ovrZzR71sqoQXwvbNAWE38q7w2iPdZWZ4+becN2ufi8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mkRQVN2J7mcA7T++SIGybx7k6YoguT2sW9ChoSMPUYbTswv4jS6E39WqLQszffElO/LamegX5BtxSfmteLxPHlzN5fR+kYN4S+E1WzYDwBzL9F0pViuwaWJ5FUSzR2rXl0Qx3plvgClFbknL/dsyDH7OoLJu9gVWDGJPuDh3jWg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=LkGo6+wW; arc=none smtp.client-ip=209.85.216.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="LkGo6+wW" Received: by mail-pj1-f41.google.com with SMTP id 98e67ed59e1d1-2e18856feb4so5569470a91.3 for ; Wed, 09 Oct 2024 01:50:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728463856; x=1729068656; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=cVj8AtzhXJ6vFkOcgklF/XoM8iIzrnBxQKfkQbnsapY=; b=LkGo6+wWcI1jWDK42mpCxJ9AyDTy2CA0X94fCq30wBD9lo1rd7o7+sknQ7QSS3YDsC L/yErZgoiK9P7otwUFdsScW8H/bAqkMFCgrJkKWtccMwjtKusJmkxN4wRrTWiAs4veyd MzTx2/BD8BDiaNi90JUzuphAJb4x1nZuIy6KSxdpGDcOOCQ/PuDZcXmp1QCjQFEwwdUn aNgGm70H+duXDmfbH1edG7+ZPVhhGmqC0d70xjyfdgo9lo7z6gDHIoQ/PjgZp5neUFPY EKiyWn/7nINKHRIKgN9RBoCK9U+cyY6bGKUHSpC4TtC5wIqZ3EBtt9FYmnBgWLM7FdEU S4Fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728463856; x=1729068656; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cVj8AtzhXJ6vFkOcgklF/XoM8iIzrnBxQKfkQbnsapY=; b=Uqj6CP5qgSkoaPfQc4EEUS17F14+08EQ/0mN3MnhnhP0XrQqbKNDD5wBo6n07BTQ+Q zBWHKyfiJzuFXO4sSmU62un8jcjnxVc+izy+ok2cldVMk/ouZa8tfD34lDXaHWkkzzOe fKW+b4J4FfR65zyVo7rOWSCTGt+zLqxDLRvlZyR2+BAcCVbKDgZImVehjyH4IuTI8J3w 93JtJhTqNW9zLmf0IsU498WI/LD5g2wxhe0HVthtF5qpldFx38E1wSuh2qQmDDXeRaZL 70Iiv1oAkGXYaN4w1EsbXZUPRO1IiFwbeGz2gCSGIwVm62arpYoEkE5jjuI6CF+0OoB4 FsKw== X-Forwarded-Encrypted: i=1; AJvYcCXil7qx86I3OPWeZ65Btsp1PiNYjpToQq2gCC+GwTeWA/Ra7hnmW84TtmjLgxoxRhIHiEE73pdVhy+xpdc=@vger.kernel.org X-Gm-Message-State: AOJu0YwHIzzRHKsB8fcrTSY2OSn0+Sfyr8+IZGzOySbsSCg9dmXsQaua +WxxUuAImZDIpJAVzU7MU8BVznSsDqo3qRDpwMBcZdUE6sUOXC6isc0+JB/x4SU= X-Google-Smtp-Source: AGHT+IEnEA+z9bRuIkWot3brQ2ilEwLd/yjDCjTrK0Iel1blGAiCM+EGqb8DDhJHM9w7m1IUfCusbw== X-Received: by 2002:a17:90a:3f87:b0:2d9:dd4a:6a95 with SMTP id 98e67ed59e1d1-2e2a2525ff5mr2151987a91.25.1728463856505; Wed, 09 Oct 2024 01:50:56 -0700 (PDT) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2abad236esm898157a91.10.2024.10.09.01.50.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 01:50:56 -0700 (PDT) From: Jun Nie Date: Wed, 09 Oct 2024 16:50:19 +0800 Subject: [PATCH v2 06/14] drm/msm/dpu: split PIPES_PER_STAGE definition per plane and mixer Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-6-76d4f5d413bf@linaro.org> References: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> In-Reply-To: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728463820; l=6669; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=ovrZzR71sqoQXwvbNAWE38q7w2iPdZWZ4+becN2ufi8=; b=ZM+3VwG25eltKqRvgmaKTxC2WylhQoCWcvNm0tMhI8u/6sa+5cYA1ch23F9Upi+dT/uH8cxvV Xh905twqT3zDZgwes1P+TA6CI7BFNj3W3PU6iL0pAQHFcYeH8sngfM8 X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Split PIPES_PER_STAGE definition per plane and mixer pair. Because there are more than 2 pipes in quad pipe case, while 2 pipes at most per mixer pair. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 3 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 18 +++++++++--------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 4 ++-- 6 files changed, 17 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 9656b1df0f122..43d9817cd858f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -463,7 +463,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, if (pstate->stage =3D=3D DPU_STAGE_BASE && format->alpha_enable) bg_alpha_enable =3D true; =20 - for (i =3D 0; i < PIPES_PER_STAGE; i++) { + for (i =3D 0; i < PIPES_PER_LM_PAIR; i++) { if (!pstate->pipe[i].sspp) continue; set_bit(pstate->pipe[i].sspp->idx, fetch_active); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.c index 602dfad127c2a..2e38f4db00c1e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -493,7 +493,7 @@ static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_c= tl *ctx, =20 if (test_bit(DPU_MIXER_SOURCESPLIT, &ctx->mixer_hw_caps->features)) - pipes_per_stage =3D PIPES_PER_STAGE; + pipes_per_stage =3D PIPES_PER_LM_PAIR; else pipes_per_stage =3D 1; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.h index 557ec9a924f81..e6e169094462f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h @@ -28,9 +28,9 @@ struct dpu_hw_ctl; * @multirect_index: index of the rectangle of SSPP. */ struct dpu_hw_stage_cfg { - enum dpu_sspp stage[DPU_STAGE_MAX][PIPES_PER_STAGE]; + enum dpu_sspp stage[DPU_STAGE_MAX][PIPES_PER_LM_PAIR]; enum dpu_sspp_multirect_index multirect_index - [DPU_STAGE_MAX][PIPES_PER_STAGE]; + [DPU_STAGE_MAX][PIPES_PER_LM_PAIR]; }; =20 /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_mdss.h index a2eff36a2224c..3277debe11689 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -32,7 +32,8 @@ #define DPU_MAX_PLANES 4 #endif =20 -#define PIPES_PER_STAGE 2 +#define PIPES_PER_PLANE 2 +#define PIPES_PER_LM_PAIR 2 #ifndef DPU_MAX_DE_CURVES #define DPU_MAX_DE_CURVES 3 #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index e7006fb8c7734..9a8fbeec2e1e8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -633,7 +633,7 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdp= u, return; =20 /* update sspp */ - for (i =3D 0; i < PIPES_PER_STAGE; i++) { + for (i =3D 0; i < PIPES_PER_PLANE; i++) { if (pstate->pipe[i].sspp) _dpu_plane_color_fill_pipe(pstate, &pstate->pipe[i], &pstate->pipe_cfg[i].dst_rect, @@ -1075,7 +1075,7 @@ static int dpu_plane_virtual_atomic_check(struct drm_= plane *plane, * resources are freed by dpu_crtc_assign_plane_resources(), * but clean them here. */ - for (i =3D 0; i < PIPES_PER_STAGE; i++) + for (i =3D 0; i < PIPES_PER_PLANE; i++) pstate->pipe[i].sspp =3D NULL; =20 return 0; @@ -1128,7 +1128,7 @@ static int dpu_plane_virtual_assign_resources(struct = drm_crtc *crtc, pipe_cfg =3D &pstate->pipe_cfg[0]; r_pipe_cfg =3D &pstate->pipe_cfg[1]; =20 - for (i =3D 0; i < PIPES_PER_STAGE; i++) + for (i =3D 0; i < PIPES_PER_PLANE; i++) pstate->pipe[i].sspp =3D NULL; =20 if (!plane_state->fb) @@ -1256,7 +1256,7 @@ void dpu_plane_flush(struct drm_plane *plane) /* force 100% alpha */ _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); else { - for (i =3D 0; i < PIPES_PER_STAGE; i++) + for (i =3D 0; i < PIPES_PER_PLANE; i++) dpu_plane_flush_csc(pdpu, &pstate->pipe[i]); } =20 @@ -1386,7 +1386,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_p= lane *plane) &fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt)); =20 /* move the assignment here, to ease handling to another pairs later */ - for (i =3D 0; i < PIPES_PER_STAGE; i++) { + for (i =3D 0; i < PIPES_PER_PLANE; i++) { if (!pstate->pipe[i].sspp) continue; dpu_plane_sspp_update_pipe(plane, &pstate->pipe[i], @@ -1400,7 +1400,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_p= lane *plane) =20 pstate->plane_fetch_bw =3D 0; pstate->plane_clk =3D 0; - for (i =3D 0; i < PIPES_PER_STAGE; i++) { + for (i =3D 0; i < PIPES_PER_PLANE; i++) { if (!pstate->pipe[i].sspp) continue; pstate->plane_fetch_bw +=3D _dpu_plane_calc_bw(pdpu->catalog, fmt, @@ -1419,7 +1419,7 @@ static void _dpu_plane_atomic_disable(struct drm_plan= e *plane) struct dpu_sw_pipe *pipe; int i; =20 - for (i =3D 0; i < PIPES_PER_STAGE; i +=3D 1) { + for (i =3D 0; i < PIPES_PER_PLANE; i +=3D 1) { pipe =3D &pstate->pipe[i]; if (!pipe->sspp) continue; @@ -1534,7 +1534,7 @@ static void dpu_plane_atomic_print_state(struct drm_p= rinter *p, =20 drm_printf(p, "\tstage=3D%d\n", pstate->stage); =20 - for (i =3D 0; i < PIPES_PER_STAGE; i++) { + for (i =3D 0; i < PIPES_PER_PLANE; i++) { pipe =3D &pstate->pipe[i]; if (!pipe->sspp) continue; @@ -1591,7 +1591,7 @@ void dpu_plane_danger_signal_ctrl(struct drm_plane *p= lane, bool enable) return; =20 pm_runtime_get_sync(&dpu_kms->pdev->dev); - for (i =3D 0; i < PIPES_PER_STAGE; i++) { + for (i =3D 0; i < PIPES_PER_PLANE; i++) { if (pstate->pipe[i].sspp) _dpu_plane_set_qos_ctrl(plane, &pstate->pipe[i], enable); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.h index 39945e0d1b851..5c1b3775dce55 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -32,8 +32,8 @@ struct dpu_plane_state { struct drm_plane_state base; struct msm_gem_address_space *aspace; - struct dpu_sw_pipe pipe[PIPES_PER_STAGE]; - struct dpu_sw_pipe_cfg pipe_cfg[PIPES_PER_STAGE]; + struct dpu_sw_pipe pipe[PIPES_PER_PLANE]; + struct dpu_sw_pipe_cfg pipe_cfg[PIPES_PER_PLANE]; enum dpu_stage stage; bool needs_qos_remap; bool pending; --=20 2.34.1 From nobody Wed Nov 27 14:32:38 2024 Received: from mail-pg1-f178.google.com (mail-pg1-f178.google.com [209.85.215.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C5CB191493 for ; Wed, 9 Oct 2024 08:51:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728463863; cv=none; b=U7/SA0H7hG0/T5bP70aI1MSVTEwGmvR/Fgaf9YzKiX3cfhh1qaFvYhEuRrT9Umya8bPI2/Z0MG4I3X4yf759FLUrPnAmKlyrMiacAdAt8JXXoo5PPqyMnWQNpshWYHQ+i8ge1yqkUHPJTFRa+ppUalTwv8jOxcdPYoSL79WL3ec= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728463863; c=relaxed/simple; bh=9RRYODS3A2d0Z0V8KOVcb66YQ53zyJFTZeiR1EUXh1U=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=iFQrqdRP8X9wUicEof0nTxNu8WxcMLR7IDbkOYpnhOFSfq6Hg/zJXDwy8JoXTbw9h+Sc9JFJxmSzWrX2uj/K7T+fX7GtRR9BBShd/NVc+1WpCYvR3fY2GoiTd3qNy1x4t/AErTx54oDeENq2eCz+Nyx/pNxULIxckkAk853RA+I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=H48P8Zx7; arc=none smtp.client-ip=209.85.215.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="H48P8Zx7" Received: by mail-pg1-f178.google.com with SMTP id 41be03b00d2f7-7db238d07b3so5577767a12.2 for ; Wed, 09 Oct 2024 01:51:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728463861; x=1729068661; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=1LPn0pitWd582eaxpygCPJ3KnkuQTc8TgGjrVLwJiU4=; b=H48P8Zx74UAMRXrhQWz07AO1Y0eNDJ3+Lzx/VHVMBfLrrxMjj6bZnBe/eAipQM81X1 4F67FVWU60/oO4WsJ2zG/VmC9GfF8pEyD6KrLOrZS+VZqZ+RdKGJ1FfDT3G8bT1EHhQ+ +Iyr09dZZD+jrW70/J+kbND8dZKm+648nVlVqmd4N3rhQl0oqpL0dNTnKzvYHueXffyG qgAj7lRS+h77V4MX7AGdk7HSSBo8sLwrpynq5jgMF7j3SWJDgoys/4IY3vrSbRQf6dgi EP3RstnK+3kSsWatRcoM2a2PxiTSNFkccz1gmS5y/t/Vey3vHasquWe48sdn1gp5sUBE 3bvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728463861; x=1729068661; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1LPn0pitWd582eaxpygCPJ3KnkuQTc8TgGjrVLwJiU4=; b=Z4O8Ro++Z9mwODAVRf0HO8U29oh7w97u2kBOBoMotYYMWW70QbasVKUupLvq6AcNdi rJ1Hk5PL6CTQYPntdKOKOCsBuJEdwoqE2A4PCdpQkP6r+tK7E8piOquIlk0+suuyp93B ZHBCJ9Bjwcu2wXTFTyxX9Rom7Bgtfnl+jPhV8GmomHOKoVUnfxRyafi6lRhrjvL0ANQZ J1oA7Foco/2uI8SZswk9NejVZ3agGvIF9ChiLXo8p5/SCMXfcbIWb349Bv0xAaK7Eq9J tCiegGrFjuah0Q2bB3QnC4TJTxomifNDuFz80BLPCS2OKPDeyT4CMCznRxDA1PVhrd7M 8rQQ== X-Forwarded-Encrypted: i=1; AJvYcCVoGsed9pxZMrl0ZEN4cp96wN5k2ildwLuEYuQE1IyTjzTj6NtUhX4oWuynhNx0nXglDwwknxiIJLcIIV0=@vger.kernel.org X-Gm-Message-State: AOJu0Ywl5R6o5v0CWGoSmOJtwcxjTSkqSNTso/oFbKnBN8fUjoiqrkFM uUHqOvEfZ8ak7c00R5vDIFcT2LVYpiHY3vdwnXWlJSRx/Vih5r3kORjEYoyrcgc= X-Google-Smtp-Source: AGHT+IEuBbVEOzp/44KTvogO+2Pwv6ey+PCRNhpJDBXR48nTEps9zZhOE/C5TsBcWU49Kk9eDonz1w== X-Received: by 2002:a05:6a21:4006:b0:1d4:fd63:95bc with SMTP id adf61e73a8af0-1d8a3be149bmr3557677637.9.1728463861596; Wed, 09 Oct 2024 01:51:01 -0700 (PDT) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2abad236esm898157a91.10.2024.10.09.01.50.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 01:51:01 -0700 (PDT) From: Jun Nie Date: Wed, 09 Oct 2024 16:50:20 +0800 Subject: [PATCH v2 07/14] drm/msm/dpu: bind correct pingpong for quad pipe Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-7-76d4f5d413bf@linaro.org> References: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> In-Reply-To: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728463820; l=1834; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=9RRYODS3A2d0Z0V8KOVcb66YQ53zyJFTZeiR1EUXh1U=; b=zI/fFfLWAz2Rx1/Bo0e+EbbQoShERiEAOqxWMBxb+PzQbh3DuBOpjimccwD4p8gsYHq+UnPTf qnLp6+iodCIDPeqPBs96CqtOwscwnDXQLGLGX3o192BuKvN1lM195gy X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= There are 2 interfaces and 4 pingpong in quad pipe. Map the 2nd interface to 3rd PP instead of the 2nd PP. Signed-off-by: Jun Nie Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index bd2509985c4d0..dfe282c607933 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1100,7 +1100,7 @@ static void dpu_encoder_virt_atomic_mode_set(struct d= rm_encoder *drm_enc, struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] =3D { NULL }; struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC]; - int num_lm, num_ctl, num_pp, num_dsc; + int num_lm, num_ctl, num_pp, num_dsc, num_pp_per_intf; unsigned int dsc_mask =3D 0; int i; =20 @@ -1171,9 +1171,14 @@ static void dpu_encoder_virt_atomic_mode_set(struct = drm_encoder *drm_enc, =20 cstate->num_dscs =3D num_dsc; cstate->num_mixers =3D num_lm; - dpu_enc->connector =3D conn_state->connector; =20 + /* + * There may be 4 PP and 2 INTF for quad pipe case, so INTF is not + * mapped to PP 1:1. Let's calculate the stride with pipe/INTF + */ + num_pp_per_intf =3D num_lm / dpu_enc->num_phys_encs; + for (i =3D 0; i < dpu_enc->num_phys_encs; i++) { struct dpu_encoder_phys *phys =3D dpu_enc->phys_encs[i]; struct dpu_hw_ctl *ctl0 =3D to_dpu_hw_ctl(hw_ctl[0]); @@ -1195,7 +1200,7 @@ static void dpu_encoder_virt_atomic_mode_set(struct d= rm_encoder *drm_enc, return; } =20 - phys->hw_pp =3D dpu_enc->hw_pp[i]; + phys->hw_pp =3D dpu_enc->hw_pp[num_pp_per_intf * i]; =20 phys->cached_mode =3D crtc_state->adjusted_mode; if (phys->ops.atomic_mode_set) --=20 2.34.1 From nobody Wed Nov 27 14:32:38 2024 Received: from mail-pj1-f49.google.com (mail-pj1-f49.google.com [209.85.216.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B6FF718FDA5 for ; Wed, 9 Oct 2024 08:51:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728463869; cv=none; b=NM6YyGHRWXP+Co35TpMYgRTIJBi/ujUSXhuwXrEsxFM83JFuKfghdw+m5WjpxmdzEvKr5RlhjzOOjDbE8fFivThLQU+tNRf03yzidfN7M6bTSG0o4sRzLOX/PxwT4ZcuzPrWYiJazE1tnNv43oC/0Msrqg0E81Q+wsAxmKBPbLo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728463869; c=relaxed/simple; bh=zBBzWdWsfyqBIiT9wbwcVNQEKc8lnnOJ9lwiSkj7ngI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=i1S3P4Pov+k+HkvslS0atpv9R6SUoHtB/uMli+5DUPpZqmkTTz8hSNTOVQpUnnrWU59JaWw+h04h59UoDPugyWSv66KQEVXqYTOPMM5sJb/45KmWrYpwWkpLxrYuIDjagj1iKiIn6g5wAHg4Cd++dO203CS+OmtKpTe5QgI3OaU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=kH+TOkgH; arc=none smtp.client-ip=209.85.216.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="kH+TOkgH" Received: by mail-pj1-f49.google.com with SMTP id 98e67ed59e1d1-2e109539aedso5474565a91.0 for ; Wed, 09 Oct 2024 01:51:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728463867; x=1729068667; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Xeuc89940OyZEzmfZGsShlcWun218secJztkD+/huVg=; b=kH+TOkgHtOBytMNN7smX3WjzUD7Yt7NiUvjkXLPuZDMqLVM9h4rxNo9U3uet9m1Ipv /5Yi7d8CjqGdiMFaX8JeJ/j7NJB5nGp32YBsPAGru4Z4YAXAhGkyip4vMrEs/UaxAdRr G02zWjK828/YEksgerytgm6sjb4pjY+ITEexNT4E6vbNRhUCP3JhalRuUeN9P58nNF1T Vw3B7SYRVZyxU1z9pVaEFCoECEX3vn/4SxlMvx2BFTyKBlcaANo14OZeTdAEFpci4Ypq Hz8IzjlO223DiDhQlbNcH7PIptPvp9AOqQrGHa8VTrH19zOuej7nzgSc9gU5rLL7srWs m18A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728463867; x=1729068667; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Xeuc89940OyZEzmfZGsShlcWun218secJztkD+/huVg=; b=Mom6u+Fb2+6PWIudITG8kC1NlJ7a/sLuEkaVOrdcz9mi6tGRwHQPORHMgM8pQfIM0s LN/dGN9n78br45GetDrlTGWVJ+KG5VKkO6U+GhdQQ+Ja40Pe7ZDpe8Dqo77OlHvId2DI FaYEUiW2oHZjISohgprT1ZOAfP6sTG7Vhg8tKw5PfgOv1M2WA4Cvh74g8v940tdcbhpp Ay0YLpenuhRKcRAWR+hLvENhsZRcVe6sdJ/+fAW3UU68x5ZyX1qLfSAG3e6uOL2Sf64n rAexcmKcUD+OoBxqLAlRVL9edcsndg+S3YXaJtTnKctHnqoX7HYBWmJiQVnoXAjcheKo n7JQ== X-Forwarded-Encrypted: i=1; AJvYcCVH9AqfglzbCPNZ9hXETG6qib5V4dV+5ru/UrewVtOQSV58MfqP3Sp7Z1HMdtsDgy+jO7vf9J9FtovPxM4=@vger.kernel.org X-Gm-Message-State: AOJu0YyPNuTtKmItcYivXAhqZhTHwzx08iEPaliaJKcApRAryBTLjbKw ytUY/b6GjOpfvvvBOrLty1je1pkLHzI7NSwG9uULecANC4C2wszNRmF+5m6Q9mWwAFbafggURJA y21KY/w== X-Google-Smtp-Source: AGHT+IF0F7RtB5DS5euGqhy7U7rhzvEMjBeGrvubLOfvxfogUs8BIv6homsplq8ODB4C0o2n6DXgtQ== X-Received: by 2002:a17:90b:1104:b0:2e2:9522:279e with SMTP id 98e67ed59e1d1-2e2a25247e0mr2201199a91.31.1728463867148; Wed, 09 Oct 2024 01:51:07 -0700 (PDT) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2abad236esm898157a91.10.2024.10.09.01.51.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 01:51:06 -0700 (PDT) From: Jun Nie Date: Wed, 09 Oct 2024 16:50:21 +0800 Subject: [PATCH v2 08/14] drm/msm/dpu: update mixer number info earlier Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-8-76d4f5d413bf@linaro.org> References: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> In-Reply-To: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728463820; l=1729; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=zBBzWdWsfyqBIiT9wbwcVNQEKc8lnnOJ9lwiSkj7ngI=; b=olKDHeGrWWSragjDEGtR+qG7l03ad9g8wQu7Scz79ICx2dg8oxIEAOpVwrukiQ+/+oPfeExdI 7EvMgTVIa78DCYbucqzqXSwayrVfw07ZG1dzLBNsZo+LiJkdMYaFHoI X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Update mixer number info earlier so that the plane nopipe check can have the info to clip the plane. Otherwise, the first nonpipe check will have mixer number as 0 and plane is not checked. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index dfe282c607933..68655c8817bf8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -638,6 +638,7 @@ static int dpu_encoder_virt_atomic_check( struct dpu_global_state *global_state; struct drm_framebuffer *fb; struct drm_dsc_config *dsc; + struct dpu_crtc_state *cstate; int ret =3D 0; =20 if (!drm_enc || !crtc_state || !conn_state) { @@ -662,6 +663,8 @@ static int dpu_encoder_virt_atomic_check( dsc =3D dpu_encoder_get_dsc_config(drm_enc); =20 topology =3D dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode, crtc_st= ate, dsc); + cstate =3D to_dpu_crtc_state(crtc_state); + cstate->num_mixers =3D topology.num_lm; =20 /* * Use CDM only for writeback or DP at the moment as other interfaces can= not handle it. @@ -1170,7 +1173,13 @@ static void dpu_encoder_virt_atomic_mode_set(struct = drm_encoder *drm_enc, } =20 cstate->num_dscs =3D num_dsc; - cstate->num_mixers =3D num_lm; + if (cstate->num_mixers !=3D num_lm) { + if (!cstate->num_mixers) + DPU_ERROR_ENC(dpu_enc, + "mixer number %d is not as expected %d\n", + num_lm, cstate->num_mixers); + cstate->num_mixers =3D num_lm; + } dpu_enc->connector =3D conn_state->connector; =20 /* --=20 2.34.1 From nobody Wed Nov 27 14:32:38 2024 Received: from mail-pj1-f46.google.com (mail-pj1-f46.google.com [209.85.216.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E11DB191F69 for ; Wed, 9 Oct 2024 08:51:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728463875; cv=none; b=klpOjZn1ZamY7bosrpiC42nVCQsn9794KP2u3fS1g8oyWh6WvpDu61GwmdBu90do3W/E5jvUPpOT2Rpgi4MUhMv7o7seZRTVfESzdSW72cXDpVlPkZ3vibADn+25abNiJ7FNnI0dsMKqwEwt9pyAATAVfuZfXl/uyiZVctHiNW8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728463875; c=relaxed/simple; bh=vJuCxGkGWnTz/P7Gtny2/1VxQGiyRWGiMV+/Rk64D/Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RTx2Uc+kKSRZOm24WsOlkng92NaOr0OFEeRaktJ+G0dz3Gp4UPgrNvrQ1TIb4Zxf/swVzk1m9Ouq6ZiN3usIxsWsh5YTbFR1jVqXdE1A4MNzPd0M3uaZ0gl2ny0iySOYyV1vVsTyFDU8gzx+XAqPflNL/D9F7JPjMfoOgKYxoP0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=mmn+WfhT; arc=none smtp.client-ip=209.85.216.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="mmn+WfhT" Received: by mail-pj1-f46.google.com with SMTP id 98e67ed59e1d1-2e28d7d44dbso1196153a91.2 for ; Wed, 09 Oct 2024 01:51:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728463873; x=1729068673; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=lGPiijXBHhXZLgDLI4yCnvpkLyy91sdQEmrQWlXpxFs=; b=mmn+WfhT7tJWr0iHkcixMCC5lSeeRAJHPIuWPJI5yxhBT8jWwHXZC9T1IF+qhHKTIB mpDiS7ASDre/q9Bz5ax8WEX0rTje8t6etTIVNB5mn+NtZnmXLrjAyWT1vu0Ju1WJhnZw lCk7wJ45UMZEBAizv12tVVH/brL0RDM4oOuV0ao1iLC+YYMr8tjxpYmSkfmoMEYGOV7O T1Nfzga2Kt4WodR8hjZOI2r+2pwl7LlPaJe5yEL1rEfqTa5RJBoG/wUhYwKPmEq9VdB5 aIb9pyFuVYPi3lfA8fvgtBNq+06vGpt/5PCh+Z36cMXLXvTL5qH250NfHNqx7GIMyrcW kIVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728463873; x=1729068673; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lGPiijXBHhXZLgDLI4yCnvpkLyy91sdQEmrQWlXpxFs=; b=gKXktvsGxijN2UiTedlXqWahGIxQcPp9Opkd5bpTU28xQirCxXXpWOZRSQ+JPwc83i jC96a4Qz8Fniopddu7k/HqgmnNUSZ4mP94j7RK7eSRBGDOYGi/4F9SOHfnvhZH+8uJfe 83KjaNi6+MBEKi6U2PjsdrvmNsord+y0OnMq9tr8vETXY5E8cK7RkDDFnhRo2xenUo+d HjY3hBoRYsd0Ibc7NV1H8dz4jntOeyk41VMengGvmuNOjtis4iV1QuNPMRWJH13DzPor 1qRKTB/hh4F72N+M3REqWQQMsptcBxlw+sqDsKKOJRD5b7Buu5Qom8g/4s+L1cMCHRWt iIKw== X-Forwarded-Encrypted: i=1; AJvYcCUu8DVvBQ48ESExLiJ8OJ3r5ddtfwe+HnlU5055jFmAC+oKbEXrvYGUvG4OBONFT/RDiWjkRhjyjqAdH30=@vger.kernel.org X-Gm-Message-State: AOJu0Yw6zn1EndYKR9sop+oidz7io+80sVAPffq6z1MNmNrgjbBMuNcT GFILtslOJiyIPE548yqbDoqvCvvccdgsO28fJLvVsxlSMnx4ra9UQ8Zl1gyiDU4= X-Google-Smtp-Source: AGHT+IHrjXqIDxYCqwvHmyuAo/2KaTwbzzxWXLOebacPfVE93Zx+pXmlthJkNcFwtHdZDvlnIGicew== X-Received: by 2002:a17:90b:4007:b0:2e0:970d:e37e with SMTP id 98e67ed59e1d1-2e2a246d989mr2280624a91.21.1728463873256; Wed, 09 Oct 2024 01:51:13 -0700 (PDT) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2abad236esm898157a91.10.2024.10.09.01.51.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 01:51:13 -0700 (PDT) From: Jun Nie Date: Wed, 09 Oct 2024 16:50:22 +0800 Subject: [PATCH v2 09/14] drm/msm/dpu: blend pipes per mixer pairs config Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-9-76d4f5d413bf@linaro.org> References: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> In-Reply-To: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728463820; l=3761; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=vJuCxGkGWnTz/P7Gtny2/1VxQGiyRWGiMV+/Rk64D/Y=; b=1MAjd3Jvkinq6GMa/Z1lrF4XLcay/hBv+mExg+EKDZlBZS5b9WsUnciLcQv8VCirNsVEuE42e uUJS17Cr/0cCekZocENT5LBgQ/bZiJecz/rUoIPmrKAEUZGAwKJUYSi X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Blend pipes by set of mixer pair config. The first 2 pipes are for left half screen with the first set of mixer pair config. And the later 2 pipes are for right in quad pipe case. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 38 ++++++++++++++++++-------= ---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 1 + 2 files changed, 25 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 43d9817cd858f..66f745399a602 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -442,7 +442,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, const struct msm_format *format; struct dpu_hw_ctl *ctl =3D mixer->lm_ctl; =20 - uint32_t lm_idx, i; + uint32_t lm_idx, lm_pair, i, pipe_idx; bool bg_alpha_enable =3D false; DECLARE_BITMAP(fetch_active, SSPP_MAX); =20 @@ -463,15 +463,20 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_cr= tc *crtc, if (pstate->stage =3D=3D DPU_STAGE_BASE && format->alpha_enable) bg_alpha_enable =3D true; =20 - for (i =3D 0; i < PIPES_PER_LM_PAIR; i++) { - if (!pstate->pipe[i].sspp) - continue; - set_bit(pstate->pipe[i].sspp->idx, fetch_active); - _dpu_crtc_blend_setup_pipe(crtc, plane, - mixer, cstate->num_mixers, - pstate->stage, - format, fb ? fb->modifier : 0, - &pstate->pipe[i], i, stage_cfg); + /* loop pipe per mixer pair */ + for (lm_pair =3D 0; lm_pair < PIPES_PER_PLANE / 2; lm_pair++) { + for (i =3D 0; i < PIPES_PER_LM_PAIR; i++) { + pipe_idx =3D i + lm_pair * PIPES_PER_LM_PAIR; + if (!pstate->pipe[pipe_idx].sspp) + continue; + set_bit(pstate->pipe[pipe_idx].sspp->idx, fetch_active); + _dpu_crtc_blend_setup_pipe(crtc, plane, + mixer, cstate->num_mixers, + pstate->stage, + format, fb ? fb->modifier : 0, + &pstate->pipe[pipe_idx], i, + &stage_cfg[lm_pair]); + } } =20 /* blend config update */ @@ -503,7 +508,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) struct dpu_crtc_mixer *mixer =3D cstate->mixers; struct dpu_hw_ctl *ctl; struct dpu_hw_mixer *lm; - struct dpu_hw_stage_cfg stage_cfg; + struct dpu_hw_stage_cfg stage_cfg[LM_PAIRS_PER_PLANE]; int i; =20 DRM_DEBUG_ATOMIC("%s\n", dpu_crtc->name); @@ -516,9 +521,9 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) } =20 /* initialize stage cfg */ - memset(&stage_cfg, 0, sizeof(struct dpu_hw_stage_cfg)); + memset(&stage_cfg, 0, sizeof(stage_cfg)); =20 - _dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, &stage_cfg); + _dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, &stage_cfg[0]); =20 for (i =3D 0; i < cstate->num_mixers; i++) { ctl =3D mixer[i].lm_ctl; @@ -535,8 +540,13 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crt= c) mixer[i].mixer_op_mode, ctl->idx - CTL_0); =20 + /* + * call dpu_hw_ctl_setup_blendstage() to blend layers per stage cfg. + * There is 4 mixers at most. The first 2 are for the left half, and + * the later 2 are for the right half. + */ ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx, - &stage_cfg); + &stage_cfg[i / 2]); } } =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_mdss.h index 3277debe11689..d8f5cffa60ea6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -34,6 +34,7 @@ =20 #define PIPES_PER_PLANE 2 #define PIPES_PER_LM_PAIR 2 +#define LM_PAIRS_PER_PLANE 2 #ifndef DPU_MAX_DE_CURVES #define DPU_MAX_DE_CURVES 3 #endif --=20 2.34.1 From nobody Wed Nov 27 14:32:38 2024 Received: from mail-pj1-f51.google.com (mail-pj1-f51.google.com [209.85.216.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 665F9191F77 for ; Wed, 9 Oct 2024 08:51:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728463881; cv=none; b=HmXqgQ95w6Tvo4PSPe3sjIMnFLBBIoL0Xf1ix9t+MkJa7NvdiDmaig+6jCyJ2qvQaCS525GX4WzBB8EMvcLXyRd3XwidfVxYtkgXRqLdJ8nbTIrEDxLVy87ARpYL9SLqzkQFngQqbAF2j2UweA0QIKoOyAeFbKzl5wkFt0QY+WI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728463881; c=relaxed/simple; bh=d6FA+M/FjBX/3MEHc7VsbcrNZioGkbL6iFmPiKpmDOA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=i1bK7q5n0Ckn3YP109nALsUwbC5R0gtD7ZM2Syg4bPwNcSi7YdbYmufIS4cSUg/PF8FwKcGwigBqIQ9XHu8h6/eGl7BwFQylcECrlgzIva2467xagXJjnzRh0d73SWPt+ZySDcdVmUK/sw3iXjeYJwtKjUcO8ghlmEgEtzrVNhY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=FCUKIiU+; arc=none smtp.client-ip=209.85.216.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="FCUKIiU+" Received: by mail-pj1-f51.google.com with SMTP id 98e67ed59e1d1-2e2a96b23e4so261125a91.2 for ; Wed, 09 Oct 2024 01:51:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728463879; x=1729068679; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=vpK0k4xFfIit4zaSmhmserorxSb9ry7uxeuhNDC7oJA=; b=FCUKIiU+X0+N3J2daT41tpgormrLGPJzJp1d0UiJldjZA496wwfShpkbiL9Od+gG1g lMoZ2xvokMjFLyQCd9CXeI+9Q75te/okcEehvnSLlGfY4CBQf0OxVaMIEvwcnJdvEF8a 0p/Fq+sYOMWIsJeBKQQs8FTNm7x5YF71hXmKx4zB5eKXghZs4Fwv3Q+PVF4W3IxlH4tP /z9DT6hHHKpI1qhH+KcyP1CVxE8TFC3U+tSW/gcvUcsvfJBeidTvUehLToFm6xSKXJTq 7un9NgsXC61417VUjVihukKqjJN1HmOfspbVbhCiclFp3cqCERmAxyyvmD5pfBHmXQlX BMsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728463879; x=1729068679; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vpK0k4xFfIit4zaSmhmserorxSb9ry7uxeuhNDC7oJA=; b=f8/V6OrLEgOLJHNFLggIzON08Hg3A71ElFp8YMVdzB3Z5FDPhaTnuMqAbG4tzcDAlL YkSU0x3nVWoKDHnJivqZFYahqTzuPseSgcEHeCUiVcJ5+cBPfEnKX3hAhHwwUjdgpL5l CP0eIGlxxijihIkGnKLU1N+TiR6t9S4UeOIloi877DFbod+YnJ4Xvceh+BcYBjXmwVU6 AR3XLxUg3Mlmf1ng3WNuoT3aKyt8CElbERfrqqv6qNyL5iizNKQq97uRiZgTXWIWomSx eoAQJ9DgOau8P1m0hRtlZAIkjcY/zhLQM+MvcCEfUFD2ihqZvC9PBFI5naX4VcuJJTsd TMgw== X-Forwarded-Encrypted: i=1; AJvYcCVdKRMwu5aSdoKo5vN+u0dcBiewtVNANznFbB6km2bs1bYX3XeAc4dMF/jd/MycWPTO3soIjf76SoKkKms=@vger.kernel.org X-Gm-Message-State: AOJu0YzLRSC2MvESNPtMvoBlD5fH/MhGsQrQxK1jdfokkB/RqhIDYvYG yJqWnERd/tlFi0RTPy//kQLiegD7Xlx6cVFqCZd5Myybi9vY8mvyIwZvjCV0ynWSRo3Smyum5x3 NIJT7fA== X-Google-Smtp-Source: AGHT+IHe9FbYiCWGUad9G8MFOgochWsO+40bvV7MWi4goN1+2gyN6VXnBwTao4ak546a2TWM8Yprwg== X-Received: by 2002:a17:90b:f8d:b0:2e2:af88:2b9f with SMTP id 98e67ed59e1d1-2e2af8834fdmr967039a91.16.1728463878553; Wed, 09 Oct 2024 01:51:18 -0700 (PDT) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2abad236esm898157a91.10.2024.10.09.01.51.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 01:51:18 -0700 (PDT) From: Jun Nie Date: Wed, 09 Oct 2024 16:50:23 +0800 Subject: [PATCH v2 10/14] drm/msm/dpu: Support quad-pipe in SSPP checking Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-10-76d4f5d413bf@linaro.org> References: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> In-Reply-To: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728463820; l=5070; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=d6FA+M/FjBX/3MEHc7VsbcrNZioGkbL6iFmPiKpmDOA=; b=GNVGnJbpfVw6aGjlDgu20HadTv0FDiH386iH87aVQ269ay9VWGIcPUPm7SHKJB4uiQ11KNiLF T7UOMZoHl8eAHZEJA4fx/XjzPS7+1GXtF2sHMd/brCB8LNDdM/tLjds X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Move requreiment check to routine of every pipe check. Because there is multiple SSPPs for quad-pipe case in future. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 2 + drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 86 ++++++++++++++-----------= ---- 2 files changed, 44 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_sspp.h index fc54625ae5d4f..05b92ff7eb529 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -143,11 +143,13 @@ struct dpu_hw_pixel_ext { * such as decimation, flip etc to program this field * @dest_rect: destination ROI. * @rotation: simplified drm rotation hint + * @valid: notify that this pipe and config is in use */ struct dpu_sw_pipe_cfg { struct drm_rect src_rect; struct drm_rect dst_rect; unsigned int rotation; + bool valid; }; =20 /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index 9a8fbeec2e1e8..904ebec1c8a18 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -739,12 +739,40 @@ static int dpu_plane_check_inline_rotation(struct dpu= _plane *pdpu, static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe, struct dpu_sw_pipe_cfg *pipe_cfg, - const struct msm_format *fmt, - const struct drm_display_mode *mode) + const struct drm_display_mode *mode, + struct drm_plane_state *new_plane_state) { uint32_t min_src_size; struct dpu_kms *kms =3D _dpu_plane_get_kms(&pdpu->base); int ret; + const struct msm_format *fmt; + uint32_t supported_rotations; + const struct dpu_sspp_cfg *pipe_hw_caps; + const struct dpu_sspp_sub_blks *sblk; + + pipe_hw_caps =3D pipe->sspp->cap; + sblk =3D pipe->sspp->cap->sblk; + + /* + * We already have verified scaling against platform limitations. + * Now check if the SSPP supports scaling at all. + */ + if (!sblk->scaler_blk.len && + ((drm_rect_width(&new_plane_state->src) >> 16 !=3D + drm_rect_width(&new_plane_state->dst)) || + (drm_rect_height(&new_plane_state->src) >> 16 !=3D + drm_rect_height(&new_plane_state->dst)))) + return -ERANGE; + + fmt =3D msm_framebuffer_format(new_plane_state->fb); + + supported_rotations =3D DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0; + + if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) + supported_rotations |=3D DRM_MODE_ROTATE_90; + + pipe_cfg->rotation =3D drm_rotation_simplify(new_plane_state->rotation, + supported_rotations); =20 min_src_size =3D MSM_FORMAT_IS_YUV(fmt) ? 2 : 1; =20 @@ -920,49 +948,19 @@ static int dpu_plane_atomic_check_pipes(struct drm_pl= ane *plane, drm_atomic_get_new_plane_state(state, plane); struct dpu_plane *pdpu =3D to_dpu_plane(plane); struct dpu_plane_state *pstate =3D to_dpu_plane_state(new_plane_state); - const struct msm_format *fmt; - struct dpu_sw_pipe *pipe =3D &pstate->pipe[0]; - struct dpu_sw_pipe *r_pipe =3D &pstate->pipe[1]; - struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg[0]; - struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->pipe_cfg[1]; - uint32_t supported_rotations; - const struct dpu_sspp_cfg *pipe_hw_caps; - const struct dpu_sspp_sub_blks *sblk; - int ret =3D 0; - - pipe_hw_caps =3D pipe->sspp->cap; - sblk =3D pipe->sspp->cap->sblk; - - /* - * We already have verified scaling against platform limitations. - * Now check if the SSPP supports scaling at all. - */ - if (!sblk->scaler_blk.len && - ((drm_rect_width(&new_plane_state->src) >> 16 !=3D - drm_rect_width(&new_plane_state->dst)) || - (drm_rect_height(&new_plane_state->src) >> 16 !=3D - drm_rect_height(&new_plane_state->dst)))) - return -ERANGE; - - fmt =3D msm_framebuffer_format(new_plane_state->fb); - - supported_rotations =3D DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0; - - if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) - supported_rotations |=3D DRM_MODE_ROTATE_90; - - pipe_cfg->rotation =3D drm_rotation_simplify(new_plane_state->rotation, - supported_rotations); - r_pipe_cfg->rotation =3D pipe_cfg->rotation; - - ret =3D dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt, - &crtc_state->adjusted_mode); - if (ret) - return ret; + struct dpu_sw_pipe *pipe; + struct dpu_sw_pipe_cfg *pipe_cfg; + int ret =3D 0, i; =20 - if (drm_rect_width(&r_pipe_cfg->src_rect) !=3D 0) { - ret =3D dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, fmt, - &crtc_state->adjusted_mode); + for (i =3D 0; i < PIPES_PER_PLANE; i++) { + pipe =3D &pstate->pipe[i]; + pipe_cfg =3D &pstate->pipe_cfg[i]; + if (!pipe_cfg->valid || !pipe->sspp) + break; + DPU_DEBUG_PLANE(pdpu, "pipe %d is in use, validate it\n", i); + ret =3D dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, + &crtc_state->adjusted_mode, + new_plane_state); if (ret) return ret; } --=20 2.34.1 From nobody Wed Nov 27 14:32:38 2024 Received: from mail-pg1-f181.google.com (mail-pg1-f181.google.com [209.85.215.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7AE31922EF for ; Wed, 9 Oct 2024 08:51:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728463886; cv=none; b=n9v8gxbkkCGA9OM+UnKmDuCr5S53ZYCFlWxV5MjbbhNKSjBx0gjovZMiPFGXgbUQel4toSNLdOGbPIFOc0IDqhR6iGjYUrOENRNNj3H5DR6PX/8hJUDPHSETgOTtV02CSAiZydiKAIxEEnNM5v8gMPsKaKTI2MTiMagjTMlUsp8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728463886; c=relaxed/simple; bh=GMo45gPySZjy72Hc4Yw7xEv8zW3cyCFzGsnKJn8DLoY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pY00i4nGPghi26kQxmdr3zNcQYFWB+++i2L6MzDhJafjBV660al6jUP8nqHWiYNWT5fj+LD+lJsZDbP0jBMcrrxTaoBa+DXHaEx3fYKQcByEjOZGubRPnDKg6/OSCQsZl7C9T7tjzkfwjnjZa7GBSEKqzalYm4ZiZ3UeI8P897w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=cRTHj0ks; arc=none smtp.client-ip=209.85.215.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="cRTHj0ks" Received: by mail-pg1-f181.google.com with SMTP id 41be03b00d2f7-7c1324be8easo475371a12.1 for ; Wed, 09 Oct 2024 01:51:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728463884; x=1729068684; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=F3RVtVtcWQ38kTkihMst8OMHNbsHVAelds2Db2o3IYo=; b=cRTHj0ksWijCyqPtamOvnuG8m5HFGjNvAgThSr321LoY/nNVdGTZZZq7cKBYRZo6P+ AtMOWyVMUNrd2TP+zBcWq9To4RARz2G6p1Gc2b9v4LnnDoX8Xk3Iy8MXgqNsVkrB2pje Lwsdbo6DO9y24znRe6zw2+fmshFU4djlIo6/yE6v3WkLd3laQmxVtlPe66HzGaGb6y5c 53+SwPuqab7T8lngWaPrunV7XM4G8WHCFg8ssr4ImCyZyVKoHyzPDQ+U6zfnCXnlJnis wm28FBHUrI68Z7QX4Gs+xdnXHK4NDzJq+Z2QaAaTBhFck/KQEDftHbbexgJvLcZ4tFOw TOEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728463884; x=1729068684; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F3RVtVtcWQ38kTkihMst8OMHNbsHVAelds2Db2o3IYo=; b=ESC4T6/+HcVjORhz5onspLEk0Iaqa9aWD+HnqB/0GDmZpbQVqewXBGwyfUHipbUSzV 3dmdalVHoozWCDztgJ03HwuY70GXBQFqFYExzmKgB4POthbJ5XRlMgyJIEk1lpWgYaaT Jydb7B1Xyfx6pQsk6gVT70nxWKQ9OzOx6ydv3abdI75Z+QKU71feOp7bDEtl3Fy3ONFm fKT0tog0p4dt6wso7kN0qCv8oKVjaF+bNR0u5p3jRUrVWpuzZAglq/XLiI2LoJmgD5IC j/e64lRg816J1h31RM4j0xn/dp8+Ls/WWqC8Ch7N4HeVuL97pVo9+Z8CjbwFHr4YqvAv qolQ== X-Forwarded-Encrypted: i=1; AJvYcCXQXlxMP8+iUx5PyzxUXaxuVMMYLY0QQhWLQZ2J7+9Y8SnLhq8ECZa4x59KsFLjLj5BIQs622BSE4f479w=@vger.kernel.org X-Gm-Message-State: AOJu0YzXkWPpoMCnihT5vhVdq3l2OpNvZi8uvLNnp7HA0plRdefQbOkp d2vE/SvDyj9lvM2k3giPq4jOjbk8YrCB1X2x8Towlr8JPCDY320Iqk5Fz1l8XQs= X-Google-Smtp-Source: AGHT+IHvpp82pkdvaPTIW66VfEKItG5LVqsQe3Zkoe6/T3/uxKCH9ZD03Stms/drz+eJxsVEGQyKiA== X-Received: by 2002:a17:90b:fd7:b0:2e2:91aa:e683 with SMTP id 98e67ed59e1d1-2e2a084ca8amr2758796a91.13.1728463884302; Wed, 09 Oct 2024 01:51:24 -0700 (PDT) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2abad236esm898157a91.10.2024.10.09.01.51.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 01:51:24 -0700 (PDT) From: Jun Nie Date: Wed, 09 Oct 2024 16:50:24 +0800 Subject: [PATCH v2 11/14] drm/msm/dpu: Share SSPP info for multi-rect case Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-11-76d4f5d413bf@linaro.org> References: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> In-Reply-To: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728463820; l=1040; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=GMo45gPySZjy72Hc4Yw7xEv8zW3cyCFzGsnKJn8DLoY=; b=S5CivVtMEYLewBJNoQ4eLfAA051Szb5Ae40kwyuCmurPDIxSr7oJL65CcW9kP+NnxKrfSzSw/ R6CxNMzFZddCCXWtYFQwLsGDsthBKAZQ35QcxpcHqcQtfuGd6WUQh18 X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Share SSPP info for multi-rect case if virtual plane is not enabled. Otherwise, the 2nd half of DMA content is not displayed due to sspp pointer of r_pipe is null. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index 904ebec1c8a18..898fc2937954e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -1042,6 +1042,11 @@ static int dpu_plane_atomic_check(struct drm_plane *= plane, pipe->multirect_index =3D DPU_SSPP_RECT_0; pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_PARALLEL; =20 + /* + * Signifies that r_pipe is to be used if the width of the 2nd + * pipe is not 0. This does not apply to virtual plane case. + */ + r_pipe->sspp =3D pipe->sspp; r_pipe->multirect_index =3D DPU_SSPP_RECT_1; r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_PARALLEL; } --=20 2.34.1 From nobody Wed Nov 27 14:32:38 2024 Received: from mail-pj1-f41.google.com (mail-pj1-f41.google.com [209.85.216.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A0A65192B76 for ; Wed, 9 Oct 2024 08:51:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728463893; cv=none; b=FnfYLKJWA+zVkWaPoNFONlqtrG8oS4qFfVsxcePY9eVEVVUTzkKpcsdvAcOKl3pQujV4mQo0XcYKQ+1QCJGqg5Mo1d46XB1bUXZqJVJ614d1zHoBvimp1M8Sa/jW4ihaVcW4z3y48AEu2iwS8N5H+8Tj/Fkt6dXdV9yRfFLtyWI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728463893; c=relaxed/simple; bh=CZPvn+ixECCJlwEHRHraiyoiomUWWKsJjwFhygCQwTY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Tq8Bda0JbEg8fEpy6ByAYFkC8DcvuPoXgi+L+hWPX08UvN0ydG67B+4FbcjnS414cdYh5cig+6mVq/4sfPwoJbpYprwsOnI5ClVTj/dQ8pALtOxBeL07d7I2KZc3MtNBauliuhevG+HBfwiSL76VSb4cSOhbecDoh9Rp6THLO/U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=QxBjHlEv; arc=none smtp.client-ip=209.85.216.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="QxBjHlEv" Received: by mail-pj1-f41.google.com with SMTP id 98e67ed59e1d1-2e2bd0e2c4fso18199a91.3 for ; Wed, 09 Oct 2024 01:51:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728463890; x=1729068690; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=lBJlR6luuHJD2SBRXmS4TBrVXnItCuuwBx1jOrvel4A=; b=QxBjHlEvj8RB1yTY/w9SoPYl95cKwHKG5eHLhxj0vUwlkBR0G3qYL/bcBBi+o+BX8O uWXzEQsBDI9Q6EnWqJ0/0FKmnU8bKXMjNExejUZhB/9rQdeV/N2/AapSFULuDCLvZul6 e4V3IsEbIMzd2kUdx6Sw44ecTJYH2+ZbGwJM/W+s5V4Hk3I0CSQfo4dggOxbWDrDEBf0 yeRJRTKkeuk1Mcs8uVL2omu/bUQ1r0UG6jKZIE2ZhFA6A7xmbeJ4TRd4wr5aTj8CcPIx 1492g0jxlsoMer1HTRWJR7+RyePTIwJqH78WP3EqKz+SSKdPoXdvjmVUBoKW2NPa1hIe 7r9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728463890; x=1729068690; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lBJlR6luuHJD2SBRXmS4TBrVXnItCuuwBx1jOrvel4A=; b=if5pNSjURE5o4xOoED1o2ElNcFk0SplF8kPPA3YBCIh/Y9CR8aJqu6bnTddHLnFkeI 34xR6Pj3JdbcHFX6mOoBesmfrhapufOXbQTR1IijJuy1fkqS0Q7JR/ni3fibUKMwot9H nsnMUDem3oNrr8vopG5GMKmT+jjPgUqlCKqR4WR6jB04q2kzznwgQZjKwNMik2vI+Y4a uyz3QmG5VSggxdjMYxgfyCMFVoiF6q591VawdP3rT/AUMQa4I4BgnoaGvfOvGgFkAw90 XVR2VW+kFzS3itpHtP5uUxf7iUJVbXGY1GzC9B2nSwpYUEJ84E40ohrkREnplIbK5mEY iXFA== X-Forwarded-Encrypted: i=1; AJvYcCUxc69reusEIRR4IgnGKbrE8d/2UK5+7CAEzE4T++n9kN+8ciYpW+wQAUHP/nktqWAxyqlR/sw1wfLpQhQ=@vger.kernel.org X-Gm-Message-State: AOJu0YwVicwwK6e0GXJFjew/cWbu2pXd5R8loPNiLYBrXxkXr4RKOOph ogJWXpb6dhXE0MFHpWpl0W4hgAtJ6yB1figoidXbba0L9+4HaQ2ccOakXcgcD5o= X-Google-Smtp-Source: AGHT+IG66GziAUmgiUUsi3KTQJBC4gAlqvuDR119PyWGN/Diu92dHzPdmdutFYrMKyP3/PNQiJlbkA== X-Received: by 2002:a17:90a:ce94:b0:2e2:7f8f:3ad7 with SMTP id 98e67ed59e1d1-2e2a21eeb54mr1854426a91.7.1728463889956; Wed, 09 Oct 2024 01:51:29 -0700 (PDT) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2abad236esm898157a91.10.2024.10.09.01.51.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 01:51:29 -0700 (PDT) From: Jun Nie Date: Wed, 09 Oct 2024 16:50:25 +0800 Subject: [PATCH v2 12/14] drm/msm/dpu: support plane splitting in quad-pipe case Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-12-76d4f5d413bf@linaro.org> References: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> In-Reply-To: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728463820; l=7922; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=CZPvn+ixECCJlwEHRHraiyoiomUWWKsJjwFhygCQwTY=; b=EHUAFkbmU3QeX8NKH88pnLfL76SKXBm4B7CBY7a1Ly9PBgUR2iMfPx/8K+/9vtilcuHatv8Y+ JEN4cyXPL0WBGTTWsGHnXXvj5hBqCJvz6Olo107OIMCR07oRbbhEDWg X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Clip plane into pipes per left and right half screen ROI if topology is quad pipe. Then split the clipped rectangle by half if the rectangle width still exceeds width limit. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 7 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 6 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 99 ++++++++++++++++++++++-----= ---- 3 files changed, 84 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 66f745399a602..d2aca0a9493d5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1310,6 +1310,13 @@ int dpu_crtc_vblank(struct drm_crtc *crtc, bool en) return 0; } =20 +unsigned int dpu_crtc_get_lm_num(const struct drm_crtc_state *state) +{ + struct dpu_crtc_state *cstate =3D to_dpu_crtc_state(state); + + return cstate->num_mixers; +} + #ifdef CONFIG_DEBUG_FS static int _dpu_debugfs_status_show(struct seq_file *s, void *data) { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.h index 5260e2440f059..ee7cf71f89fc7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h @@ -304,4 +304,10 @@ static inline enum dpu_crtc_client_type dpu_crtc_get_c= lient_type( =20 void dpu_crtc_frame_event_cb(struct drm_crtc *crtc, u32 event); =20 +/** + * dpu_crtc_get_lm_num - Get mixer number in this CRTC pipeline + * state: Pointer to drm crtc state object + */ +unsigned int dpu_crtc_get_lm_num(const struct drm_crtc_state *state); + #endif /* _DPU_CRTC_H_ */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index 898fc2937954e..480a1b46aba72 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -837,10 +837,12 @@ static int dpu_plane_atomic_check_nopipe(struct drm_p= lane *plane, struct dpu_kms *kms =3D _dpu_plane_get_kms(&pdpu->base); u64 max_mdp_clk_rate =3D kms->perf.max_core_clk_rate; struct dpu_plane_state *pstate =3D to_dpu_plane_state(new_plane_state); - struct dpu_sw_pipe_cfg *pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg; + struct dpu_sw_pipe_cfg pipe_cfg; struct drm_rect fb_rect =3D { 0 }; + const struct drm_display_mode *mode =3D &crtc_state->adjusted_mode; uint32_t max_linewidth; + u32 lm_num; + int lmcfg_id, lmcfg_num; =20 min_scale =3D FRAC_16_16(1, MAX_UPSCALE_RATIO); max_scale =3D MAX_DOWNSCALE_RATIO << 16; @@ -863,13 +865,10 @@ static int dpu_plane_atomic_check_nopipe(struct drm_p= lane *plane, return -EINVAL; } =20 - /* move the assignment here, to ease handling to another pairs later */ - pipe_cfg =3D &pstate->pipe_cfg[0]; - r_pipe_cfg =3D &pstate->pipe_cfg[1]; - /* state->src is 16.16, src_rect is not */ - drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src); + lm_num =3D dpu_crtc_get_lm_num(crtc_state); =20 - pipe_cfg->dst_rect =3D new_plane_state->dst; + /* state->src is 16.16, src_rect is not */ + drm_rect_fp_to_int(&pipe_cfg.src_rect, &new_plane_state->src); =20 fb_rect.x2 =3D new_plane_state->fb->width; fb_rect.y2 =3D new_plane_state->fb->height; @@ -884,34 +883,78 @@ static int dpu_plane_atomic_check_nopipe(struct drm_p= lane *plane, =20 max_linewidth =3D pdpu->catalog->caps->max_linewidth; =20 - drm_rect_rotate(&pipe_cfg->src_rect, + drm_rect_rotate(&pipe_cfg.src_rect, new_plane_state->fb->width, new_plane_state->fb->height, new_plane_state->rotation); =20 - if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) || - _dpu_plane_calc_clk(&crtc_state->adjusted_mode, pipe_cfg) > max_mdp_= clk_rate) { - if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) { - DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", - DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); - return -E2BIG; + /* + * We have 1 mixer pair cfg for 1:1:1 and 2:2:1 topology, 2 mixer pair + * configs for left and right half screen in case of 4:4:2 topology. + * But we may have 2 rect to split plane with 1 config for 2:2:1. + * So need to handle super wide plane splitting, and plane on right half + * for quad-pipe case. Check dest rectangle left/right clipping + * first, then check super wide rectangle splitting in every half next. + */ + lmcfg_num =3D (lm_num + 1) / 2; + /* iterate mixer configs for this plane, to separate left/right with the = id */ + for (lmcfg_id =3D 0; lmcfg_id < lmcfg_num; lmcfg_id++) { + struct drm_rect mixer_rect =3D {lmcfg_id * mode->hdisplay / lmcfg_num, 0, + (lmcfg_id + 1) * mode->hdisplay / lmcfg_num, mode->vdisplay}; + int cfg_idx =3D lmcfg_id * PIPES_PER_LM_PAIR; + struct dpu_sw_pipe_cfg *cur_pipecfg =3D &pstate->pipe_cfg[cfg_idx]; + + drm_rect_fp_to_int(&cur_pipecfg->src_rect, &new_plane_state->src); + cur_pipecfg->dst_rect =3D new_plane_state->dst; + + DPU_DEBUG_PLANE(pdpu, "checking src " DRM_RECT_FMT + " vs clip window " DRM_RECT_FMT "\n", + DRM_RECT_ARG(&cur_pipecfg->src_rect), + DRM_RECT_ARG(&mixer_rect)); + + /* If this plane does not fall into mixer rect, check next mixer rect */ + if (!drm_rect_clip_scaled(&cur_pipecfg->src_rect, &cur_pipecfg->dst_rect= , &mixer_rect)) { + memset(&pstate->pipe_cfg[cfg_idx], 0, 2 * sizeof(struct dpu_sw_pipe_cfg= )); + memset(&pstate->pipe[cfg_idx], 0, 2 * sizeof(struct dpu_sw_pipe)); + continue; } =20 - *r_pipe_cfg =3D *pipe_cfg; - pipe_cfg->src_rect.x2 =3D (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2= ) >> 1; - pipe_cfg->dst_rect.x2 =3D (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2= ) >> 1; - r_pipe_cfg->src_rect.x1 =3D pipe_cfg->src_rect.x2; - r_pipe_cfg->dst_rect.x1 =3D pipe_cfg->dst_rect.x2; - } else { - memset(r_pipe_cfg, 0, sizeof(*r_pipe_cfg)); - } + cur_pipecfg->valid =3D true; + cur_pipecfg->dst_rect.x1 -=3D mixer_rect.x1; + cur_pipecfg->dst_rect.x2 -=3D mixer_rect.x1; + + DPU_DEBUG_PLANE(pdpu, "Got clip src:" DRM_RECT_FMT " dst: " DRM_RECT_FMT= "\n", + DRM_RECT_ARG(&cur_pipecfg->src_rect), DRM_RECT_ARG(&cur_pipecfg->dst_r= ect)); + + /* Split super wide rect into 2 rect */ + if ((drm_rect_width(&cur_pipecfg->src_rect) > max_linewidth) || + _dpu_plane_calc_clk(mode, cur_pipecfg) > max_mdp_clk_rate) { + struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->pipe_cfg[cfg_idx + 1]; + + if (drm_rect_width(&cur_pipecfg->src_rect) > 2 * max_linewidth) { + DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", + DRM_RECT_ARG(&cur_pipecfg->src_rect), max_linewidth); + return -E2BIG; + } + + memcpy(r_pipe_cfg, cur_pipecfg, sizeof(struct dpu_sw_pipe_cfg)); + cur_pipecfg->src_rect.x2 =3D (cur_pipecfg->src_rect.x1 + cur_pipecfg->s= rc_rect.x2) >> 1; + cur_pipecfg->dst_rect.x2 =3D (cur_pipecfg->dst_rect.x1 + cur_pipecfg->d= st_rect.x2) >> 1; + r_pipe_cfg->src_rect.x1 =3D cur_pipecfg->src_rect.x2; + r_pipe_cfg->dst_rect.x1 =3D cur_pipecfg->dst_rect.x2; + r_pipe_cfg->valid =3D true; + DPU_DEBUG_PLANE(pdpu, "Split super wide plane into:" + DRM_RECT_FMT " and " DRM_RECT_FMT "\n", + DRM_RECT_ARG(&cur_pipecfg->src_rect), + DRM_RECT_ARG(&r_pipe_cfg->src_rect)); + } else { + memset(&pstate->pipe_cfg[cfg_idx + 1], 0, sizeof(struct dpu_sw_pipe_cfg= )); + memset(&pstate->pipe[cfg_idx + 1], 0, sizeof(struct dpu_sw_pipe)); + } =20 - drm_rect_rotate_inv(&pipe_cfg->src_rect, - new_plane_state->fb->width, new_plane_state->fb->height, - new_plane_state->rotation); - if (drm_rect_width(&r_pipe_cfg->src_rect) !=3D 0) - drm_rect_rotate_inv(&r_pipe_cfg->src_rect, + drm_rect_rotate_inv(&cur_pipecfg->src_rect, new_plane_state->fb->width, new_plane_state->fb->height, new_plane_state->rotation); + } =20 pstate->needs_qos_remap =3D drm_atomic_crtc_needs_modeset(crtc_state); =20 --=20 2.34.1 From nobody Wed Nov 27 14:32:38 2024 Received: from mail-pj1-f45.google.com (mail-pj1-f45.google.com [209.85.216.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBD1818A92D for ; Wed, 9 Oct 2024 08:51:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728463897; cv=none; b=UBtXKw3BllFxjq41r3SKT9s56Lh41QX9qycBeyBrTZjXlElU1o9BYLOCYi3USRKvxkhZlIWZNkDxzEB10m2FloaG+Gg5cECD4uPMJJ/7KuQiu9iNdDLz+agUl6LXtJrWhFm/j+2aZ3YvVQPr9JmT0ffTEs6E7zTlUHy22LxNFuU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728463897; c=relaxed/simple; bh=81jK3N0j+q+DAMnsIs+UuOUU0xKWIcMiivwpFJMyey8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NppUUzhfpsy31UP2BCgMCvUmsEcZPAGAnHxs1j6vd5foNKAbWw3Pc2MFYOFyYBH5e67zBW/QIKrHiSES8wF5JzhfKaGQ/bPU8P/eEE/h46zI38vUdx2IV8WXgmukUtlwxOaq2IR7IChgJ/C/AmyMrQ+CjHuiJXQSRJIKv+36bFA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=L7qhB+fx; arc=none smtp.client-ip=209.85.216.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="L7qhB+fx" Received: by mail-pj1-f45.google.com with SMTP id 98e67ed59e1d1-2e2bb1efe78so37956a91.1 for ; Wed, 09 Oct 2024 01:51:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728463895; x=1729068695; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=J50cstReZOAStzssDowtSyHGuYNkBj/m3heNj/5l6AQ=; b=L7qhB+fxMCDZ9v7ncKD7ygWpIEZsoBo8i4mtwOYH37VoMLZK4dFFZJOJixhNpwmHed 3/39rbarqVOspGAGq3cgjyRMHKpOntnGqJI31CpjkGXrBiI6JPTwE4olsV7NdqJKkslk Z50v5CaB2UiRB/XswqrJHOFWaD0czCfC6cQmp7iYoVFz5kL4U9nuaU4R5nA91OQoBojg Ua+M6NUqrrN0SGQNk1ZMj88rwTZIA7aV09+FDpPsHTMrb84J4AEtE/NHOSss5L/cqca/ aRS/5WyOIfX4T/l/4d/cjz9RTgvsXI81EDWFsHBPZ1ubBFQTJkzqDgU6QQFYQ8hJHlT2 +XNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728463895; x=1729068695; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J50cstReZOAStzssDowtSyHGuYNkBj/m3heNj/5l6AQ=; b=EHCWbCOMOCW94fpkOSDdmfd3bG16GM5rAnvI6akigJNJ77Uj4bgAN214GHGDMA5HIt Mg+DPRW5G6ORFQSbKwkC0titBQzvEyWGKxrgf9WOH4tnp04BdGQw2O9JYLkBz2w2/VXt SUDvJcl9lohk8avM7CVqChedpgGKJtyyH7Hkp+WW0SgjyZtZwhstlwgvANpzPcF3NVXm G9pMNb2vAzkmtcnr2r+M4F9EWUXo68O1h3b7xyFHshRs//8fFfCglYhPJsYx19PstlVF bDH/47VMsBottoPBENpmGQxK0+qwAJa9DNxxhtydic4AQ2/sfqFn+11o7qOydhiFqX5S AyNw== X-Forwarded-Encrypted: i=1; AJvYcCVoQiByIiiQNWcMi4qPY1lYqX4Ar5HuJfrsoYbUutIHnOqA9UBkYLtNtSn9VMjRvL27ABbI9Rbcpy3QTt0=@vger.kernel.org X-Gm-Message-State: AOJu0YxC4slPEdtMoNNSqcMuzdFyHiRrsNyICBgg23HSGmXEhhxarg/q G9C6ZVIqMkGrl70YLWKvWHt6SiRt/HuVy29IjumHlHDZqF/CxCG96eMnLDaCJ0c= X-Google-Smtp-Source: AGHT+IGh9hWeUvEBQWoVINgVGvCvhY1wTX7fgeC/PcJue28p3V3B/iyUf2JTyGKo3OaTbJ8zsQLDwA== X-Received: by 2002:a17:90b:4c12:b0:2da:82d4:c63c with SMTP id 98e67ed59e1d1-2e27dd3c2c0mr9615183a91.4.1728463895250; Wed, 09 Oct 2024 01:51:35 -0700 (PDT) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2abad236esm898157a91.10.2024.10.09.01.51.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 01:51:34 -0700 (PDT) From: Jun Nie Date: Wed, 09 Oct 2024 16:50:26 +0800 Subject: [PATCH v2 13/14] drm/msm/dpu: support SSPP assignment for quad-pipe case Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-13-76d4f5d413bf@linaro.org> References: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> In-Reply-To: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728463820; l=5496; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=81jK3N0j+q+DAMnsIs+UuOUU0xKWIcMiivwpFJMyey8=; b=T2DDlAeki79IVTctGUrvaj5XGACyxwdgxLwVCSDMiyi7MaCokffcNiEXMdg9z8ampm5Okjoid qYQVV0H1p1TBiQAtOoEekEoUnh5BEej73xKINai11HinJq+tccjEGZy X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Support SSPP assignment for quad-pipe case with unified method. The first 2 pipes can share a set of mixer config and enable multi-rect mode if condition is met. It is also the case for the later 2 pipes. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 85 +++++++++++++++------------= ---- 1 file changed, 42 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index 480a1b46aba72..23de2ca6fabb0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -999,7 +999,7 @@ static int dpu_plane_atomic_check_pipes(struct drm_plan= e *plane, pipe =3D &pstate->pipe[i]; pipe_cfg =3D &pstate->pipe_cfg[i]; if (!pipe_cfg->valid || !pipe->sspp) - break; + continue; DPU_DEBUG_PLANE(pdpu, "pipe %d is in use, validate it\n", i); ret =3D dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, &crtc_state->adjusted_mode, @@ -1154,13 +1154,10 @@ static int dpu_plane_virtual_assign_resources(struc= t drm_crtc *crtc, struct dpu_kms *dpu_kms =3D _dpu_plane_get_kms(plane); struct dpu_rm_sspp_requirements reqs; struct dpu_plane_state *pstate; - struct dpu_sw_pipe *pipe; - struct dpu_sw_pipe *r_pipe; - struct dpu_sw_pipe_cfg *pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg; + struct dpu_plane *pdpu =3D to_dpu_plane(plane); const struct msm_format *fmt; uint32_t max_linewidth; - int i; + int i, lm_num, lmcfg_id, lmcfg_num; =20 if (plane_state->crtc) crtc_state =3D drm_atomic_get_new_crtc_state(state, @@ -1168,12 +1165,6 @@ static int dpu_plane_virtual_assign_resources(struct= drm_crtc *crtc, =20 pstate =3D to_dpu_plane_state(plane_state); =20 - /* loop below code for another pair later */ - pipe =3D &pstate->pipe[0]; - r_pipe =3D &pstate->pipe[1]; - pipe_cfg =3D &pstate->pipe_cfg[0]; - r_pipe_cfg =3D &pstate->pipe_cfg[1]; - for (i =3D 0; i < PIPES_PER_PLANE; i++) pstate->pipe[i].sspp =3D NULL; =20 @@ -1189,41 +1180,49 @@ static int dpu_plane_virtual_assign_resources(struc= t drm_crtc *crtc, =20 max_linewidth =3D dpu_kms->catalog->caps->max_linewidth; =20 - pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &req= s); - if (!pipe->sspp) - return -ENODEV; - - if (drm_rect_width(&r_pipe_cfg->src_rect) =3D=3D 0) { - pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; - - r_pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; - - r_pipe->sspp =3D NULL; - } else { - if (dpu_plane_is_multirect_parallel_capable(pipe, pipe_cfg, fmt, max_lin= ewidth) && - dpu_plane_is_multirect_parallel_capable(r_pipe, r_pipe_cfg, fmt, max= _linewidth) && - (test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) || - test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features))) { - r_pipe->sspp =3D pipe->sspp; + lm_num =3D dpu_crtc_get_lm_num(crtc_state); + lmcfg_num =3D (lm_num + 1) / 2; + for (lmcfg_id =3D 0; lmcfg_id < lmcfg_num; lmcfg_id++) { + for (i =3D lmcfg_id * PIPES_PER_LM_PAIR; i < (lmcfg_id + 1) * PIPES_PER_= LM_PAIR; i++) { + struct dpu_sw_pipe *pipe =3D &pstate->pipe[i]; + struct dpu_sw_pipe *r_pipe =3D &pstate->pipe[i + 1]; + struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg[i]; + struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->pipe_cfg[i + 1]; =20 - pipe->multirect_index =3D DPU_SSPP_RECT_0; - pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_PARALLEL; + if (!pipe_cfg->valid) + break; =20 - r_pipe->multirect_index =3D DPU_SSPP_RECT_1; - r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_PARALLEL; - } else { - /* multirect is not possible, use two SSPP blocks */ - r_pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, = &reqs); - if (!r_pipe->sspp) + pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &r= eqs); + if (!pipe->sspp) return -ENODEV; =20 - pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; - - r_pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + /* + * If current pipe is the first pipe in pipe pair, check + * multi-rect opportunity for the 2nd pipe in the pair. + * SSPP multi-rect mode cross mixer pairs is not supported. + */ + if (!(i % 2) && + r_pipe_cfg->valid && + drm_rect_width(&r_pipe_cfg->src_rect) !=3D 0 && + dpu_plane_is_multirect_parallel_capable(pipe, pipe_cfg, fmt, max_li= newidth) && + dpu_plane_is_multirect_parallel_capable(r_pipe, r_pipe_cfg, fmt, ma= x_linewidth) && + (test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) || + test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features))) { + pipe->multirect_index =3D DPU_SSPP_RECT_0; + pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_PARALLEL; + + DPU_DEBUG_PLANE(pdpu, "allocating sspp_%d for pipe %d and set pipe %d = as multi-rect\n", + pipe->sspp->idx - SSPP_NONE, i, i + 1); + r_pipe->sspp =3D pipe->sspp; + r_pipe->multirect_index =3D DPU_SSPP_RECT_1; + r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_PARALLEL; + i++; + } else { + pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; + pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + DPU_DEBUG_PLANE(pdpu, "allocating sspp_%d for pipe %d.\n", + pipe->sspp->idx - SSPP_NONE, i); + } } } =20 --=20 2.34.1 From nobody Wed Nov 27 14:32:38 2024 Received: from mail-pg1-f178.google.com (mail-pg1-f178.google.com [209.85.215.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5DB911957E4 for ; Wed, 9 Oct 2024 08:51:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728463903; cv=none; b=OyT41WaXc7nvu9dTpM9u3uNydUmgCLxm7NQFKuAtVZxv2XcCmU57du9GUohnm75STaRyZ4Jfw18DAyV/LKvvssezhEDhACyBB8OjEQo+4fXAN1uRhISuoB8UWSC/asn91ioLvnvy37KN7FKdZcVZ2GiuB5H56IDZ+uUPFof/+Yc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728463903; c=relaxed/simple; bh=7+ZvIkQm3+KbgF5bXG62KdNVBcWEMmn0s/slfuucy/Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jJDwKqylqrMpZgDeuu0glA0CC5LX9t5UwgdYOvGwHRhc0h1lJ83Y5DY/f3rsW8TPkD0FT6kMGzOBfspmHV6nfpBTk07s1+6GUl/7iwKLVAJ4ZLTneI/Z2gmYRCkJt3+1Vi1vp0Mo6H+c8zKJk4xjzSYJ5jacnr5+iQwlpSTAQoE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=EM7C+/yg; arc=none smtp.client-ip=209.85.215.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="EM7C+/yg" Received: by mail-pg1-f178.google.com with SMTP id 41be03b00d2f7-7d4fa972cbeso4843757a12.2 for ; Wed, 09 Oct 2024 01:51:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1728463901; x=1729068701; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Pwqv1rhTGFasLdg0WvU6AXjOOGyCaNS4WyGtK80xkko=; b=EM7C+/ygglU+FX/7YSg5XYJ7NmgTudyHN2Uwdc8JLfdeLv9B+DG1k1pskWef6CJ1ER gJF1lT3+4Fv46C/U6I2dp7/1m3B9dbvmZrH1YotZZXZDBBxWjkaZhmCUmMXdizL9vdD0 7bw22Ri8sNmOtuKaK8Ggy2Nm3ZTixb155ThsYwp3PYxg8GoGM6pECoEHWwDyAI9/nPje dJCzcVhEDjXgr9ogN0VinKFnpdghPZZbOMZxz0URTYu0+s597SaNfy9qkDLDkMryqTU8 Vh7wejprLgRyCAVv8z3w6w1dO5p+3hzPNw+swArXX9J60PvDkJbEnzmD1AJIyF/aWAuV 44eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728463901; x=1729068701; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Pwqv1rhTGFasLdg0WvU6AXjOOGyCaNS4WyGtK80xkko=; b=Krhlla4SCLIU7cx9XyetHHXgbE+pyAx6wsy99Klv1XAjk7s88/bBtZpaL6+/1/WB2M akVUZlc7kB7slQpLeWF2xTWCGmLPLExt5RZCs/6fpW9j6w7CAUe4sy0tRe3b57vXRUwz 7ag6s3zrGgA1jfynJsBvoAxQ5MU5MWIEkd8zVevfzwqDg+pZ29suID+HYa2mL8Orrg2e xEmzPYfqBKBAYrlf/Ez6YGGOUxkGr84MdCkFanyMlSyh4KDYfyvCs+HIOLG39lkvtefa immdMFb+WZIp4NB3ghEW+wmFBrA9lqPQaUtiW5A2kOo2MCe7aCfmRwpDfb9q1k4KoBAv SIag== X-Forwarded-Encrypted: i=1; AJvYcCX4e/Bwz3mvVBJk4SIx6Ny1WQ4z+lAo0tJnN51VEyqnfRdd3hs5xmor/13VLuofW76eAZYW6Z3DgYZCZL0=@vger.kernel.org X-Gm-Message-State: AOJu0YyyQ5HrIZiv6aqljgDa8Wx2ALvKvD0ONeiLeuu8pIKZtdXOUMbd jmraBLb4+auuE5TeKN+abaIbLJ0kcJOIMjxivYQftXD9Aobuwr6f8Oq3iwVcSMA= X-Google-Smtp-Source: AGHT+IH/OP3QTgGjxIuKJ0oyytzwGzO6tFYp3oV193Ebfd756Hp2A4o+GBtu5EabM4fWhmuN+lSVgA== X-Received: by 2002:a17:90a:744a:b0:2dd:92e5:6f7d with SMTP id 98e67ed59e1d1-2e2a2471e84mr2313793a91.20.1728463900699; Wed, 09 Oct 2024 01:51:40 -0700 (PDT) Received: from [127.0.1.1] ([112.65.12.217]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2abad236esm898157a91.10.2024.10.09.01.51.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2024 01:51:40 -0700 (PDT) From: Jun Nie Date: Wed, 09 Oct 2024 16:50:27 +0800 Subject: [PATCH v2 14/14] drm/msm/dpu: Enable quad-pipe for DSC and dual-DSI case Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-14-76d4f5d413bf@linaro.org> References: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> In-Reply-To: <20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728463820; l=6009; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=7+ZvIkQm3+KbgF5bXG62KdNVBcWEMmn0s/slfuucy/Q=; b=rgEs/g/vWs4Vpc3qv0Yve1dY4lYYjjpml8TIJBgX0vKvSOeV5royXLdUYsPS6UFPTrxwJBslz J2BLnZXAbGsBNs2tGlsVrNZkPkX5KG0DZyxhksp051co0lyg7Gn5H4C X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Request 4 mixers and 4 DSC for the case that both dual-DSI and DSC are enabled. We prefer to use 4 pipes for dual DSI case for it is power optimal for DSC. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 6 ++--- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 29 ++++++++++++++++++--= ---- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 3 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 +- 6 files changed, 30 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index d2aca0a9493d5..dbdfff1c7792a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -200,7 +200,7 @@ static int dpu_crtc_get_lm_crc(struct drm_crtc *crtc, struct dpu_crtc_state *crtc_state) { struct dpu_crtc_mixer *m; - u32 crcs[CRTC_DUAL_MIXERS]; + u32 crcs[CRTC_QUAD_MIXERS]; =20 int rc =3D 0; int i; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.h index ee7cf71f89fc7..f8276afd99192 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h @@ -211,7 +211,7 @@ struct dpu_crtc_state { =20 bool bw_control; bool bw_split_vote; - struct drm_rect lm_bounds[CRTC_DUAL_MIXERS]; + struct drm_rect lm_bounds[CRTC_QUAD_MIXERS]; =20 uint64_t input_fence_timeout_ns; =20 @@ -219,10 +219,10 @@ struct dpu_crtc_state { =20 /* HW Resources reserved for the crtc */ u32 num_mixers; - struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS]; + struct dpu_crtc_mixer mixers[CRTC_QUAD_MIXERS]; =20 u32 num_ctls; - struct dpu_hw_ctl *hw_ctls[CRTC_DUAL_MIXERS]; + struct dpu_hw_ctl *hw_ctls[CRTC_QUAD_MIXERS]; =20 u32 num_dscs; enum dpu_crtc_crc_source crc_source; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index 68655c8817bf8..ed220ac691e8a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -54,7 +54,7 @@ #define MAX_PHYS_ENCODERS_PER_VIRTUAL \ (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES) =20 -#define MAX_CHANNELS_PER_ENC 2 +#define MAX_CHANNELS_PER_ENC 4 =20 #define IDLE_SHORT_TIMEOUT 1 =20 @@ -588,15 +588,19 @@ static struct msm_display_topology dpu_encoder_get_to= pology( =20 /* Datapath topology selection * - * Dual display + * Dual display without DSC * 2 LM, 2 INTF ( Split display using 2 interfaces) * + * Dual display with DSC + * 4 LM, 2 INTF ( Split display using 2 interfaces) + * * Single display * 1 LM, 1 INTF * 2 LM, 1 INTF (stream merge to support high resolution interfaces) * * Add dspps to the reservation requirements if ctm is requested */ + if (intf_count =3D=3D 2) topology.num_lm =3D 2; else if (!dpu_kms->catalog->caps->has_3d_merge) @@ -615,10 +619,21 @@ static struct msm_display_topology dpu_encoder_get_to= pology( * 2 DSC encoders, 2 layer mixers and 1 interface * this is power optimal and can drive up to (including) 4k * screens + * But for dual display case, we prefer 4 layer mixers. Because + * the resolution is always high in the case and 4 DSCs are more + * power optimal. While a single SSPP can only co-work with one + * mixer pair. So 4 mixers are needed in this case. */ - topology.num_dsc =3D 2; - topology.num_lm =3D 2; - topology.num_intf =3D 1; + + if (intf_count =3D=3D 2) { + topology.num_dsc =3D 4; + topology.num_lm =3D 4; + topology.num_intf =3D 2; + } else { + topology.num_dsc =3D 2; + topology.num_lm =3D 2; + topology.num_intf =3D 1; + } } =20 return topology; @@ -2031,8 +2046,8 @@ static void dpu_encoder_helper_reset_mixers(struct dp= u_encoder_phys *phys_enc) struct dpu_hw_mixer_cfg mixer; int i, num_lm; struct dpu_global_state *global_state; - struct dpu_hw_blk *hw_lm[2]; - struct dpu_hw_mixer *hw_mixer[2]; + struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; + struct dpu_hw_mixer *hw_mixer[MAX_CHANNELS_PER_ENC]; struct dpu_hw_ctl *ctl =3D phys_enc->hw_ctl; =20 memset(&mixer, 0, sizeof(mixer)); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu= /drm/msm/disp/dpu1/dpu_encoder_phys.h index e77ebe3a68da9..c877ee45535ac 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -324,7 +324,8 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper= _get_3d_blend_mode( =20 /* Use merge_3d unless DSC MERGE topology is used */ if (phys_enc->split_role =3D=3D ENC_ROLE_SOLO && - dpu_cstate->num_mixers =3D=3D CRTC_DUAL_MIXERS && + (dpu_cstate->num_mixers =3D=3D CRTC_DUAL_MIXERS || + dpu_cstate->num_mixers =3D=3D CRTC_QUAD_MIXERS) && !dpu_encoder_use_dsc_merge(phys_enc->parent)) return BLEND_3D_H_ROW_INT; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index bf86d643887dd..f79ecd409a830 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -25,6 +25,7 @@ #define MAX_IMG_HEIGHT 0x3fff =20 #define CRTC_DUAL_MIXERS 2 +#define CRTC_QUAD_MIXERS 4 =20 #define MAX_XIN_COUNT 16 =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_mdss.h index d8f5cffa60ea6..671e03406df74 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -32,9 +32,9 @@ #define DPU_MAX_PLANES 4 #endif =20 -#define PIPES_PER_PLANE 2 #define PIPES_PER_LM_PAIR 2 #define LM_PAIRS_PER_PLANE 2 +#define PIPES_PER_PLANE (PIPES_PER_LM_PAIR * LM_PAIRS_PER_PLANE) #ifndef DPU_MAX_DE_CURVES #define DPU_MAX_DE_CURVES 3 #endif --=20 2.34.1