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Wed, 09 Oct 2024 14:34:18 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 499EYHxR000395 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 9 Oct 2024 14:34:17 GMT Received: from hu-mahap-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 9 Oct 2024 07:34:10 -0700 From: Mahadevan Date: Wed, 9 Oct 2024 20:02:01 +0530 Subject: [PATCH v4 1/5] dt-bindings: display/msm: Document MDSS on SA8775P Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241009-patchv3_1-v4-1-cd683a9ca554@quicinc.com> References: <20241009-patchv3_1-v4-0-cd683a9ca554@quicinc.com> In-Reply-To: <20241009-patchv3_1-v4-0-cd683a9ca554@quicinc.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mahadevan , Neil Armstrong , Bjorn Andersson , "Konrad Dybcio" CC: , , , , , Kalyan Thota , Jayaprakash Madisetty , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Reviewed-by: Krzysztof Kozlowski Signed-off-by: Mahadevan --- .../bindings/display/msm/qcom,sa8775p-mdss.yaml | 241 +++++++++++++++++= ++++ 1 file changed, 241 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mds= s.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.ya= ml new file mode 100644 index 0000000000000000000000000000000000000000..37c04ae6876f873c2cddc51b516= 0b1f54e2b5118 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml @@ -0,0 +1,241 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sa8775p-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SA87755P Display MDSS + +maintainers: + - Mahadevan + +description: + SA8775P MSM Mobile Display Subsystem(MDSS), which encapsulates sub-block= s like + DPU display controller, DP interfaces and EDP etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sa8775p-mdss + + clocks: + items: + - description: Display AHB + - description: Display hf AXI + - description: Display core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 3 + + interconnect-names: + maxItems: 3 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sa8775p-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + items: + - const: qcom,sa8775p-dp + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + display-subsystem@ae00000 { + compatible =3D "qcom,sa8775p-mdss"; + reg =3D <0x0ae00000 0x1000>; + reg-names =3D "mdss"; + + interconnects =3D <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISP= LAY_CFG>; + interconnect-names =3D "mdp0-mem", + "mdp1-mem", + "cpu-cfg"; + + + resets =3D <&dispcc_core_bcr>; + power-domains =3D <&dispcc_gdsc>; + + clocks =3D <&dispcc_ahb_clk>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc_mdp_clk>; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + iommus =3D <&apps_smmu 0x1000 0x402>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + display-controller@ae01000 { + compatible =3D "qcom,sa8775p-dpu"; + reg =3D <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc_ahb_clk>, + <&dispcc_mdp_lut_clk>, + <&dispcc_mdp_clk>, + <&dispcc_mdp_vsync_clk>; + clock-names =3D "bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&dispcc_mdp_vsync_clk>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdss0_mdp_opp_table>; + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + interrupt-parent =3D <&mdss0>; + interrupts =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dpu_intf0_out: endpoint { + remote-endpoint =3D <&mdss0_dp0_in>; + }; + }; + }; + + mdss0_mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-375000000 { + opp-hz =3D /bits/ 64 <375000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + + opp-575000000 { + opp-hz =3D /bits/ 64 <575000000>; + required-opps =3D <&rpmhpd_opp_turbo>; + }; + + opp-650000000 { + opp-hz =3D /bits/ 64 <650000000>; + required-opps =3D <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + + displayport-controller@af54000 { + compatible =3D "qcom,sa8775p-dp"; + + pinctrl-0 =3D <&dp_hot_plug_det>; + pinctrl-names =3D "default"; + + reg =3D <0xaf54000 0x104>, + <0xaf54200 0x0c0>, + <0xaf55000 0x770>, + <0xaf56000 0x09c>; + + interrupt-parent =3D <&mdss0>; + interrupts =3D <12>; + + clocks =3D <&dispcc_mdss_ahb_clk>, + <&dispcc_dptx0_aux_clk>, + <&dispcc_dptx0_link_clk>, + <&dispcc_dptx0_link_intf_clk>, + <&dispcc_dptx0_pixel0_clk>; + clock-names =3D "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks =3D <&dispcc_mdss_dptx0_link_clk_src>, + <&dispcc_mdss_dptx0_pixel0_clk_src>; + assigned-clock-parents =3D <&mdss0_edp_phy 0>, <&mdss0_edp_phy= 1>; + + phys =3D <&mdss0_edp_phy>; + phy-names =3D "dp"; + + operating-points-v2 =3D <&dp_opp_table>; + power-domains =3D <&rpmhpd SA8775P_MMCX>; + + #sound-dai-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mdss0_dp0_in: endpoint { + remote-endpoint =3D <&dpu_intf0_out>; + }; + }; + + port@1 { + reg =3D <1>; + mdss0_dp_out: endpoint { }; + }; + }; + + dp_opp_table: opp-table { + compatible =3D "operating-points-v2"; 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Signed-off-by: Mahadevan --- Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml index c4087cc5abbdd44885a6755e1facda767a16f35d..01cf79bd754b491349c52c5aef4= 9ba06e835d0bf 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml @@ -14,6 +14,7 @@ $ref: /schemas/display/msm/dpu-common.yaml# properties: compatible: enum: + - qcom,sa8775p-dpu - qcom,sm8650-dpu - qcom,x1e80100-dpu =20 --=20 2.34.1 From nobody Wed Nov 27 14:25:22 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E9695192B7A; Wed, 9 Oct 2024 14:34:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Reviewed-by: Dmitry Baryshkov Signed-off-by: Mahadevan --- drivers/gpu/drm/msm/msm_mdss.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index faa88fd6eb4d6aec383a242b66a2b5125c91b3bc..8f1d42a43bd02dd79acf222a342= 3d11ff3b3cba3 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -573,6 +573,16 @@ static const struct msm_mdss_data qcm2290_data =3D { .reg_bus_bw =3D 76800, }; =20 +static const struct msm_mdss_data sa8775p_data =3D { + .ubwc_enc_version =3D UBWC_4_0, + .ubwc_dec_version =3D UBWC_4_0, + .ubwc_swizzle =3D 4, + .ubwc_static =3D 1, + .highest_bank_bit =3D 0, + .macrotile_mode =3D 1, + .reg_bus_bw =3D 74000, +}; + static const struct msm_mdss_data sc7180_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, @@ -710,6 +720,7 @@ static const struct of_device_id mdss_dt_match[] =3D { { .compatible =3D "qcom,mdss" }, { .compatible =3D "qcom,msm8998-mdss", .data =3D &msm8998_data }, { .compatible =3D "qcom,qcm2290-mdss", .data =3D &qcm2290_data }, + { .compatible =3D "qcom,sa8775p-mdss", .data =3D &sa8775p_data }, { .compatible =3D "qcom,sdm670-mdss", .data =3D &sdm670_data }, { .compatible =3D "qcom,sdm845-mdss", .data =3D &sdm845_data }, { .compatible =3D "qcom,sc7180-mdss", .data =3D &sc7180_data }, --=20 2.34.1 From nobody Wed Nov 27 14:25:22 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCC8D18BBB0; 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Reviewed-by: Dmitry Baryshkov Signed-off-by: Mahadevan --- .../drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 485 +++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 488 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h new file mode 100644 index 0000000000000000000000000000000000000000..907b4d7ceb470b0391d2bbbab3c= e520efa2b3263 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h @@ -0,0 +1,485 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DPU_8_4_SA8775P_H +#define _DPU_8_4_SA8775P_H + +static const struct dpu_caps sa8775p_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages =3D 0xb, + .has_src_split =3D true, + .has_dim_layer =3D true, + .has_idle_pc =3D true, + .has_3d_merge =3D true, + .max_linewidth =3D 5120, + .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_mdp_cfg sa8775p_mdp =3D { + .name =3D "top_0", + .base =3D 0x0, .len =3D 0x494, + .features =3D BIT(DPU_MDP_PERIPH_0_REMOVED), + .clk_ctrls =3D { + [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, + [DPU_CLK_CTRL_VIG1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 0 }, + [DPU_CLK_CTRL_VIG2] =3D { .reg_off =3D 0x2bc, .bit_off =3D 0 }, + [DPU_CLK_CTRL_VIG3] =3D { .reg_off =3D 0x2c4, .bit_off =3D 0 }, + [DPU_CLK_CTRL_DMA0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 8 }, + [DPU_CLK_CTRL_DMA1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 8 }, + [DPU_CLK_CTRL_DMA2] =3D { .reg_off =3D 0x2bc, .bit_off =3D 8 }, + [DPU_CLK_CTRL_DMA3] =3D { .reg_off =3D 0x2c4, .bit_off =3D 8 }, + [DPU_CLK_CTRL_WB2] =3D { .reg_off =3D 0x2bc, .bit_off =3D 16 }, + [DPU_CLK_CTRL_REG_DMA] =3D { .reg_off =3D 0x2bc, .bit_off =3D 20 }, + }, +}; + +/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL = support */ +static const struct dpu_ctl_cfg sa8775p_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x15000, .len =3D 0x204, + .features =3D BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name =3D "ctl_1", .id =3D CTL_1, + .base =3D 0x16000, .len =3D 0x204, + .features =3D BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name =3D "ctl_2", .id =3D CTL_2, + .base =3D 0x17000, .len =3D 0x204, + .features =3D CTL_SC7280_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name =3D "ctl_3", .id =3D CTL_3, + .base =3D 0x18000, .len =3D 0x204, + .features =3D CTL_SC7280_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, { + .name =3D "ctl_4", .id =3D CTL_4, + .base =3D 0x19000, .len =3D 0x204, + .features =3D CTL_SC7280_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, { + .name =3D "ctl_5", .id =3D CTL_5, + .base =3D 0x1a000, .len =3D 0x204, + .features =3D CTL_SC7280_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + }, +}; + +static const struct dpu_sspp_cfg sa8775p_sspp[] =3D { + { + .name =3D "sspp_0", .id =3D SSPP_VIG0, + .base =3D 0x4000, .len =3D 0x32c, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_1, + .xin_id =3D 0, + .type =3D SSPP_TYPE_VIG, + .clk_ctrl =3D DPU_CLK_CTRL_VIG0, + }, { + .name =3D "sspp_1", .id =3D SSPP_VIG1, + .base =3D 0x6000, .len =3D 0x32c, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_1, + .xin_id =3D 4, + .type =3D SSPP_TYPE_VIG, + .clk_ctrl =3D DPU_CLK_CTRL_VIG1, + }, { + .name =3D "sspp_2", .id =3D SSPP_VIG2, + .base =3D 0x8000, .len =3D 0x32c, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_1, + .xin_id =3D 8, + .type =3D SSPP_TYPE_VIG, + .clk_ctrl =3D DPU_CLK_CTRL_VIG2, + }, { + .name =3D "sspp_3", .id =3D SSPP_VIG3, + .base =3D 0xa000, .len =3D 0x32c, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_1, + .xin_id =3D 12, + .type =3D SSPP_TYPE_VIG, + .clk_ctrl =3D DPU_CLK_CTRL_VIG3, + }, { + .name =3D "sspp_8", .id =3D SSPP_DMA0, + .base =3D 0x24000, .len =3D 0x32c, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 1, + .type =3D SSPP_TYPE_DMA, + .clk_ctrl =3D DPU_CLK_CTRL_DMA0, + }, { + .name =3D "sspp_9", .id =3D SSPP_DMA1, + .base =3D 0x26000, .len =3D 0x32c, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 5, + .type =3D SSPP_TYPE_DMA, + .clk_ctrl =3D DPU_CLK_CTRL_DMA1, + }, { + .name =3D "sspp_10", .id =3D SSPP_DMA2, + .base =3D 0x28000, .len =3D 0x32c, + .features =3D DMA_CURSOR_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 9, + .type =3D SSPP_TYPE_DMA, + .clk_ctrl =3D DPU_CLK_CTRL_DMA2, + }, { + .name =3D "sspp_11", .id =3D SSPP_DMA3, + .base =3D 0x2a000, .len =3D 0x32c, + .features =3D DMA_CURSOR_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 13, + .type =3D SSPP_TYPE_DMA, + .clk_ctrl =3D DPU_CLK_CTRL_DMA3, + }, +}; + +static const struct dpu_lm_cfg sa8775p_lm[] =3D { + { + .name =3D "lm_0", .id =3D LM_0, + .base =3D 0x44000, .len =3D 0x400, + .features =3D MIXER_SDM845_MASK, + .sblk =3D &sdm845_lm_sblk, + .lm_pair =3D LM_1, + .pingpong =3D PINGPONG_0, + .dspp =3D DSPP_0, + }, { + .name =3D "lm_1", .id =3D LM_1, + .base =3D 0x45000, .len =3D 0x400, + .features =3D MIXER_SDM845_MASK, + .sblk =3D &sdm845_lm_sblk, + .lm_pair =3D LM_0, + .pingpong =3D PINGPONG_1, + .dspp =3D DSPP_1, + }, { + .name =3D "lm_2", .id =3D LM_2, + .base =3D 0x46000, .len =3D 0x400, + .features =3D MIXER_SDM845_MASK, + .sblk =3D &sdm845_lm_sblk, + .lm_pair =3D LM_3, + .pingpong =3D PINGPONG_2, + .dspp =3D DSPP_2, + }, { + .name =3D "lm_3", .id =3D LM_3, + .base =3D 0x47000, .len =3D 0x400, + .features =3D MIXER_SDM845_MASK, + .sblk =3D &sdm845_lm_sblk, + .lm_pair =3D LM_2, + .pingpong =3D PINGPONG_3, + .dspp =3D DSPP_3, + }, { + .name =3D "lm_4", .id =3D LM_4, + .base =3D 0x48000, .len =3D 0x400, + .features =3D MIXER_SDM845_MASK, + .sblk =3D &sdm845_lm_sblk, + .lm_pair =3D LM_5, + .pingpong =3D PINGPONG_4, + }, { + .name =3D "lm_5", .id =3D LM_5, + .base =3D 0x49000, .len =3D 0x400, + .features =3D MIXER_SDM845_MASK, + .sblk =3D &sdm845_lm_sblk, + .lm_pair =3D LM_4, + .pingpong =3D PINGPONG_5, + }, +}; + +static const struct dpu_dspp_cfg sa8775p_dspp[] =3D { + { + .name =3D "dspp_0", .id =3D DSPP_0, + .base =3D 0x54000, .len =3D 0x1800, + .features =3D DSPP_SC7180_MASK, + .sblk =3D &sdm845_dspp_sblk, + }, { + .name =3D "dspp_1", .id =3D DSPP_1, + .base =3D 0x56000, .len =3D 0x1800, + .features =3D DSPP_SC7180_MASK, + .sblk =3D &sdm845_dspp_sblk, + }, { + .name =3D "dspp_2", .id =3D DSPP_2, + .base =3D 0x58000, .len =3D 0x1800, + .features =3D DSPP_SC7180_MASK, + .sblk =3D &sdm845_dspp_sblk, + }, { + .name =3D "dspp_3", .id =3D DSPP_3, + .base =3D 0x5a000, .len =3D 0x1800, + .features =3D DSPP_SC7180_MASK, + .sblk =3D &sdm845_dspp_sblk, + }, +}; + +static const struct dpu_pingpong_cfg sa8775p_pp[] =3D { + { + .name =3D "pingpong_0", .id =3D PINGPONG_0, + .base =3D 0x69000, .len =3D 0, + .features =3D BIT(DPU_PINGPONG_DITHER), + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_0, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + }, { + .name =3D "pingpong_1", .id =3D PINGPONG_1, + .base =3D 0x6a000, .len =3D 0, + .features =3D BIT(DPU_PINGPONG_DITHER), + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_0, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + }, { + .name =3D "pingpong_2", .id =3D PINGPONG_2, + .base =3D 0x6b000, .len =3D 0, + .features =3D BIT(DPU_PINGPONG_DITHER), + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_1, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + }, { + .name =3D "pingpong_3", .id =3D PINGPONG_3, + .base =3D 0x6c000, .len =3D 0, + .features =3D BIT(DPU_PINGPONG_DITHER), + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_1, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + }, { + .name =3D "pingpong_4", .id =3D PINGPONG_4, + .base =3D 0x6d000, .len =3D 0, + .features =3D BIT(DPU_PINGPONG_DITHER), + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_2, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + }, { + .name =3D "pingpong_5", .id =3D PINGPONG_5, + .base =3D 0x6e000, .len =3D 0, + .features =3D BIT(DPU_PINGPONG_DITHER), + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_2, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), + }, { + .name =3D "pingpong_6", .id =3D PINGPONG_6, + .base =3D 0x65800, .len =3D 0, + .features =3D BIT(DPU_PINGPONG_DITHER), + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_3, + }, { + .name =3D "pingpong_7", .id =3D PINGPONG_7, + .base =3D 0x65c00, .len =3D 0, + .features =3D BIT(DPU_PINGPONG_DITHER), + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_3, + }, +}; + +static const struct dpu_merge_3d_cfg sa8775p_merge_3d[] =3D { + { + .name =3D "merge_3d_0", .id =3D MERGE_3D_0, + .base =3D 0x4e000, .len =3D 0x8, + }, { + .name =3D "merge_3d_1", .id =3D MERGE_3D_1, + .base =3D 0x4f000, .len =3D 0x8, + }, { + .name =3D "merge_3d_2", .id =3D MERGE_3D_2, + .base =3D 0x50000, .len =3D 0x8, + }, { + .name =3D "merge_3d_3", .id =3D MERGE_3D_3, + .base =3D 0x65f00, .len =3D 0x8, + }, +}; + +/* + * NOTE: Each display compression engine (DCE) contains dual hard + * slice DSC encoders so both share same base address but with + * its own different sub block address. + */ +static const struct dpu_dsc_cfg sa8775p_dsc[] =3D { + { + .name =3D "dce_0_0", .id =3D DSC_0, + .base =3D 0x80000, .len =3D 0x4, + .features =3D BIT(DPU_DSC_HW_REV_1_2), + .sblk =3D &dsc_sblk_0, + }, { + .name =3D "dce_0_1", .id =3D DSC_1, + .base =3D 0x80000, .len =3D 0x4, + .features =3D BIT(DPU_DSC_HW_REV_1_2), + .sblk =3D &dsc_sblk_1, + }, { + .name =3D "dce_1_0", .id =3D DSC_2, + .base =3D 0x81000, .len =3D 0x4, + .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &dsc_sblk_0, + }, { + .name =3D "dce_1_1", .id =3D DSC_3, + .base =3D 0x81000, .len =3D 0x4, + .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &dsc_sblk_1, + }, { + .name =3D "dce_2_0", .id =3D DSC_4, + .base =3D 0x82000, .len =3D 0x4, + .features =3D BIT(DPU_DSC_HW_REV_1_2), + .sblk =3D &dsc_sblk_0, + }, { + .name =3D "dce_2_1", .id =3D DSC_5, + .base =3D 0x82000, .len =3D 0x4, + .features =3D BIT(DPU_DSC_HW_REV_1_2), + .sblk =3D &dsc_sblk_1, + }, +}; + +static const struct dpu_wb_cfg sa8775p_wb[] =3D { + { + .name =3D "wb_2", .id =3D WB_2, + .base =3D 0x65000, .len =3D 0x2c8, + .features =3D WB_SM8250_MASK, + .format_list =3D wb2_formats_rgb_yuv, + .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), + .clk_ctrl =3D DPU_CLK_CTRL_WB2, + .xin_id =3D 6, + .vbif_idx =3D VBIF_RT, + .maxlinewidth =3D 4096, + .intr_wb_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), + }, +}; + +/* TODO: INTF 3, 6, 7 and 8 are used for MST, marked as INTF_NONE for now = */ +static const struct dpu_intf_cfg sa8775p_intf[] =3D { + { + .name =3D "intf_0", .id =3D INTF_0, + .base =3D 0x34000, .len =3D 0x280, + .features =3D INTF_SC7280_MASK, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + }, { + .name =3D "intf_1", .id =3D INTF_1, + .base =3D 0x35000, .len =3D 0x300, + .features =3D INTF_SC7280_MASK, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr =3D DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), + }, { + .name =3D "intf_2", .id =3D INTF_2, + .base =3D 0x36000, .len =3D 0x300, + .features =3D INTF_SC7280_MASK, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_1, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), + .intr_tear_rd_ptr =3D DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), + }, { + .name =3D "intf_3", .id =3D INTF_3, + .base =3D 0x37000, .len =3D 0x280, + .features =3D INTF_SC7280_MASK, + .type =3D INTF_NONE, + .controller_id =3D MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), + }, { + .name =3D "intf_4", .id =3D INTF_4, + .base =3D 0x38000, .len =3D 0x280, + .features =3D INTF_SC7280_MASK, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_1, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21), + }, { + .name =3D "intf_6", .id =3D INTF_6, + .base =3D 0x3A000, .len =3D 0x280, + .features =3D INTF_SC7280_MASK, + .type =3D INTF_NONE, + .controller_id =3D MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16), + }, { + .name =3D "intf_7", .id =3D INTF_7, + .base =3D 0x3b000, .len =3D 0x280, + .features =3D INTF_SC7280_MASK, + .type =3D INTF_NONE, + .controller_id =3D MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19), + }, { + .name =3D "intf_8", .id =3D INTF_8, + .base =3D 0x3c000, .len =3D 0x280, + .features =3D INTF_SC7280_MASK, + .type =3D INTF_NONE, + .controller_id =3D MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */ + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), + }, +}; + +static const struct dpu_perf_cfg sa8775p_perf_data =3D { + .max_bw_low =3D 13600000, + .max_bw_high =3D 18200000, + .min_core_ib =3D 2500000, + .min_llcc_ib =3D 0, + .min_dram_ib =3D 800000, + .min_prefill_lines =3D 35, + /* FIXME: lut tables */ + .danger_lut_tbl =3D {0x3ffff, 0x3ffff, 0x0}, + .safe_lut_tbl =3D {0xfff0, 0xfff0, 0x1}, + .qos_lut_tbl =3D { + {.nentry =3D ARRAY_SIZE(sm6350_qos_linear_macrotile), + .entries =3D sm6350_qos_linear_macrotile + }, + {.nentry =3D ARRAY_SIZE(sm6350_qos_linear_macrotile), + .entries =3D sm6350_qos_linear_macrotile + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_nrt), + .entries =3D sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg =3D { + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, + .bw_inefficiency_factor =3D 120, +}; + +static const struct dpu_mdss_version sa8775p_mdss_ver =3D { + .core_major_ver =3D 8, + .core_minor_ver =3D 4, +}; + +const struct dpu_mdss_cfg dpu_sa8775p_cfg =3D { + .mdss_ver =3D &sa8775p_mdss_ver, + .caps =3D &sa8775p_dpu_caps, + .mdp =3D &sa8775p_mdp, + .cdm =3D &sc7280_cdm, + .ctl_count =3D ARRAY_SIZE(sa8775p_ctl), + .ctl =3D sa8775p_ctl, + .sspp_count =3D ARRAY_SIZE(sa8775p_sspp), + .sspp =3D sa8775p_sspp, + .mixer_count =3D ARRAY_SIZE(sa8775p_lm), + .mixer =3D sa8775p_lm, + .dspp_count =3D ARRAY_SIZE(sa8775p_dspp), + .dspp =3D sa8775p_dspp, + .pingpong_count =3D ARRAY_SIZE(sa8775p_pp), + .pingpong =3D sa8775p_pp, + .dsc_count =3D ARRAY_SIZE(sa8775p_dsc), + .dsc =3D sa8775p_dsc, + .merge_3d_count =3D ARRAY_SIZE(sa8775p_merge_3d), + .merge_3d =3D sa8775p_merge_3d, + .wb_count =3D ARRAY_SIZE(sa8775p_wb), + .wb =3D sa8775p_wb, + .intf_count =3D ARRAY_SIZE(sa8775p_intf), + .intf =3D sa8775p_intf, + .vbif_count =3D ARRAY_SIZE(sdm845_vbif), + .vbif =3D sdm845_vbif, + .perf =3D &sa8775p_perf_data, +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index dcb4fd85e73b9cc05e669043602d69229881c0b4..cc67bc82128f17216478e1b1592= 8a9c90edecbbb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -699,6 +699,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = =3D { =20 #include "catalog/dpu_8_0_sc8280xp.h" #include "catalog/dpu_8_1_sm8450.h" +#include "catalog/dpu_8_4_sa8775p.h" =20 #include "catalog/dpu_9_0_sm8550.h" =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 37e18e820a20a4c4ab9a97da78df19a2ff7cfa00..9665eedec699e125cf72da20738= a3031279bc522 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -850,6 +850,7 @@ extern const struct dpu_mdss_cfg dpu_sm8350_cfg; extern const struct dpu_mdss_cfg dpu_sc7280_cfg; extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg; extern const struct dpu_mdss_cfg dpu_sm8450_cfg; +extern const struct dpu_mdss_cfg dpu_sa8775p_cfg; extern const struct dpu_mdss_cfg dpu_sm8550_cfg; extern const struct dpu_mdss_cfg dpu_sm8650_cfg; extern const struct dpu_mdss_cfg dpu_x1e80100_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 9bcae53c4f458cd8e400f0e851b791c0f4165085..6d47d7dcffc2c1feafd99731571= 826a9b3f912b6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1447,6 +1447,7 @@ static const struct dev_pm_ops dpu_pm_ops =3D { static const struct of_device_id dpu_dt_match[] =3D { { .compatible =3D "qcom,msm8998-dpu", .data =3D &dpu_msm8998_cfg, }, { .compatible =3D "qcom,qcm2290-dpu", .data =3D &dpu_qcm2290_cfg, }, + { .compatible =3D "qcom,sa8775p-dpu", .data =3D &dpu_sa8775p_cfg, }, { .compatible =3D "qcom,sdm630-mdp5", .data =3D &dpu_sdm630_cfg, }, { .compatible =3D "qcom,sdm660-mdp5", .data =3D &dpu_sdm660_cfg, }, { .compatible =3D "qcom,sdm670-dpu", .data =3D &dpu_sdm670_cfg, }, --=20 2.34.1 From nobody Wed Nov 27 14:25:22 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E22E21A2C21; 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Reviewed-by: Dmitry Baryshkov Signed-off-by: Mahadevan --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 89 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 89 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/sa8775p.dtsi index 8fd68a8aa916e6595134b470f87b18b509178a51..66bd5e1c82a426f93097dee63a6= 9c03527f04b3e 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -2937,6 +2938,94 @@ camcc: clock-controller@ade0000 { #power-domain-cells =3D <1>; }; =20 + mdss0: display-subsystem@ae00000 { + compatible =3D "qcom,sa8775p-mdss"; + reg =3D <0x0 0x0ae00000 0x0 0x1000>; + reg-names =3D "mdss"; + + /* same path used twice */ + interconnects =3D <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "mdp0-mem", + "mdp1-mem", + "cpu-cfg"; + + resets =3D <&dispcc0 MDSS_DISP_CC_MDSS_CORE_BCR>; + + power-domains =3D <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>; + + clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + iommus =3D <&apps_smmu 0x1000 0x402>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + mdss0_mdp: display-controller@ae01000 { + compatible =3D "qcom,sa8775p-dpu"; + reg =3D <0x0 0x0ae01000 0x0 0x8f000>, + <0x0 0x0aeb0000 0x0 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdss0_mdp_opp_table>; + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + interrupt-parent =3D <&mdss0>; + interrupts =3D <0>; + + mdss0_mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-375000000 { + opp-hz =3D /bits/ 64 <375000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + + opp-575000000 { + opp-hz =3D /bits/ 64 <575000000>; + required-opps =3D <&rpmhpd_opp_turbo>; + }; + + opp-650000000 { + opp-hz =3D /bits/ 64 <650000000>; + required-opps =3D <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + }; + dispcc0: clock-controller@af00000 { compatible =3D "qcom,sa8775p-dispcc0"; reg =3D <0x0 0x0af00000 0x0 0x20000>; --=20 2.34.1