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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN3PEPF0000B078.mail.protection.outlook.com (10.167.243.123) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8048.13 via Frontend Transport; Tue, 8 Oct 2024 22:17:15 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 8 Oct 2024 17:17:14 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , , Subject: [PATCH 01/15] cxl/aer/pci: Add CXL PCIe port error handler callbacks in AER service driver Date: Tue, 8 Oct 2024 17:16:43 -0500 Message-ID: <20241008221657.1130181-2-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241008221657.1130181-1-terry.bowman@amd.com> References: <20241008221657.1130181-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B078:EE_|SJ2PR12MB8159:EE_ X-MS-Office365-Filtering-Correlation-Id: dbbf03eb-a5d0-41d5-0394-08dce7e6f6fe X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013|7416014|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2024 22:17:15.1323 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dbbf03eb-a5d0-41d5-0394-08dce7e6f6fe X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B078.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8159 Content-Type: text/plain; charset="utf-8" CXL protocol errors are reported to the OS through PCIe correctable and uncorrectable internal errors. However, since CXL PCIe port devices are currently bound to the portdrv driver, there is no mechanism to notify the CXL driver, which is necessary for proper logging and handling. To address this, introduce CXL PCIe port error callbacks along with register/unregister and accessor functions. The callbacks will be invoked by the AER driver in the case protocol errors are reported by a CXL port device. The AER driver callbacks will be used in future patches implementing CXL PCIe port error handling. Signed-off-by: Terry Bowman --- drivers/pci/pcie/aer.c | 22 ++++++++++++++++++++++ include/linux/aer.h | 14 ++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 13b8586924ea..a9792b9576b4 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -50,6 +50,8 @@ struct aer_rpc { DECLARE_KFIFO(aer_fifo, struct aer_err_source, AER_ERROR_SOURCES_MAX); }; =20 +static struct cxl_port_err_hndlrs cxl_port_hndlrs; + /* AER stats for the device */ struct aer_stats { =20 @@ -1078,6 +1080,26 @@ static inline void cxl_rch_handle_error(struct pci_d= ev *dev, struct aer_err_info *info) { } #endif =20 +void register_cxl_port_hndlrs(struct cxl_port_err_hndlrs *_cxl_port_hndlrs) +{ + cxl_port_hndlrs.error_detected =3D _cxl_port_hndlrs->error_detected; + cxl_port_hndlrs.cor_error_detected =3D _cxl_port_hndlrs->cor_error_detect= ed; +} +EXPORT_SYMBOL_NS_GPL(register_cxl_port_hndlrs, CXL); + +void unregister_cxl_port_hndlrs(void) +{ + cxl_port_hndlrs.error_detected =3D NULL; + cxl_port_hndlrs.cor_error_detected =3D NULL; +} +EXPORT_SYMBOL_NS_GPL(unregister_cxl_port_hndlrs, CXL); + +struct cxl_port_err_hndlrs *find_cxl_port_hndlrs(void) +{ + return &cxl_port_hndlrs; +} +EXPORT_SYMBOL_NS_GPL(find_cxl_port_hndlrs, CXL); + /** * pci_aer_handle_error - handle logging error into an event log * @dev: pointer to pci_dev data structure of error source device diff --git a/include/linux/aer.h b/include/linux/aer.h index 4b97f38f3fcf..67fd04c5ae2b 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -10,6 +10,7 @@ =20 #include #include +#include =20 #define AER_NONFATAL 0 #define AER_FATAL 1 @@ -55,5 +56,18 @@ void pci_print_aer(struct pci_dev *dev, int aer_severity, int cper_severity_to_aer(int cper_severity); void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn, int severity, struct aer_capability_regs *aer_regs); + +struct cxl_port_err_hndlrs { + + /* CXL uncorrectable error detected on this device */ + pci_ers_result_t (*error_detected)(struct pci_dev *dev, + pci_channel_state_t error); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2024 22:17:26.1863 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bd1dc2c2-3d7c-435b-58b2-08dce7e6fd92 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B073.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8770 Content-Type: text/plain; charset="utf-8" CXL port error handling will be updated in future and will use logic to determine if an error requires CXL or PCIe processing. Internal errors are one indicator to identify an error is a CXL protocol error. is_internal_error() is currently limited by CONFIG_PCIEAER_CXL kernel config. Update the is_internal_error() function's declaration such that it is always available regardless if CONFIG_PCIEAER_CXL kernel config is enabled or disabled. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron --- drivers/pci/pcie/aer.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index a9792b9576b4..1e72829a249f 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -941,8 +941,15 @@ static bool find_source_device(struct pci_dev *parent, return true; } =20 -#ifdef CONFIG_PCIEAER_CXL +static bool is_internal_error(struct aer_err_info *info) +{ + if (info->severity =3D=3D AER_CORRECTABLE) + return info->status & PCI_ERR_COR_INTERNAL; =20 + return info->status & PCI_ERR_UNC_INTN; +} + +#ifdef CONFIG_PCIEAER_CXL /** * pci_aer_unmask_internal_errors - unmask internal errors * @dev: pointer to the pcie_dev data structure @@ -994,14 +1001,6 @@ static bool cxl_error_is_native(struct pci_dev *dev) return (pcie_ports_native || host->native_aer); } =20 -static bool is_internal_error(struct aer_err_info *info) -{ - if (info->severity =3D=3D AER_CORRECTABLE) - return info->status & PCI_ERR_COR_INTERNAL; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2024 22:17:37.2562 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4b04c59c-d6fa-4eb6-dab5-08dce7e7042d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B072.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7631 Content-Type: text/plain; charset="utf-8" The AER service driver already includes support for CXL restricted host (RCH) downstream port error handling. The current implementation is based CXl1.1 using a root complex event collector. Update the function interfaces and parameters where necessary to add virtual hierarchy (VH) mode CXL PCIe port error handling alongside the RCH handling. The CXL PCIe port error handling will be added in a future patch. Limit changes to refactoring variable and function names. No functional changes are added. Signed-off-by: Terry Bowman --- drivers/pci/pcie/aer.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 1e72829a249f..dc8b17999001 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1030,7 +1030,7 @@ static int cxl_rch_handle_error_iter(struct pci_dev *= dev, void *data) return 0; } =20 -static void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info = *info) +static void cxl_handle_error(struct pci_dev *dev, struct aer_err_info *inf= o) { /* * Internal errors of an RCEC indicate an AER error in an @@ -1053,30 +1053,30 @@ static int handles_cxl_error_iter(struct pci_dev *d= ev, void *data) return *handles_cxl; } =20 -static bool handles_cxl_errors(struct pci_dev *rcec) +static bool handles_cxl_errors(struct pci_dev *dev) { bool handles_cxl =3D false; =20 - if (pci_pcie_type(rcec) =3D=3D PCI_EXP_TYPE_RC_EC && - pcie_aer_is_native(rcec)) - pcie_walk_rcec(rcec, handles_cxl_error_iter, &handles_cxl); + if (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_RC_EC && + pcie_aer_is_native(dev)) + pcie_walk_rcec(dev, handles_cxl_error_iter, &handles_cxl); =20 return handles_cxl; } =20 -static void cxl_rch_enable_rcec(struct pci_dev *rcec) +static void cxl_enable_internal_errors(struct pci_dev *dev) { - if (!handles_cxl_errors(rcec)) + if (!handles_cxl_errors(dev)) return; =20 - pci_aer_unmask_internal_errors(rcec); - pci_info(rcec, "CXL: Internal errors unmasked"); + pci_aer_unmask_internal_errors(dev); + pci_info(dev, "CXL: Internal errors unmasked"); } =20 #else -static inline void cxl_rch_enable_rcec(struct pci_dev *dev) { } -static inline void cxl_rch_handle_error(struct pci_dev *dev, - struct aer_err_info *info) { } +static inline void cxl_enable_internal_errors(struct pci_dev *dev) { } +static inline void cxl_handle_error(struct pci_dev *dev, + struct aer_err_info *info) { } #endif =20 void register_cxl_port_hndlrs(struct cxl_port_err_hndlrs *_cxl_port_hndlrs) @@ -1134,7 +1134,7 @@ static void pci_aer_handle_error(struct pci_dev *dev,= struct aer_err_info *info) =20 static void handle_error_source(struct pci_dev *dev, struct aer_err_info *= info) { - cxl_rch_handle_error(dev, info); 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Tue, 8 Oct 2024 22:17:48 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN3PEPF0000B074.mail.protection.outlook.com (10.167.243.119) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8048.13 via Frontend Transport; Tue, 8 Oct 2024 22:17:48 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 8 Oct 2024 17:17:47 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , , Subject: [PATCH 04/15] cxl/aer/pci: Add CXL PCIe port correctable error support in AER service driver Date: Tue, 8 Oct 2024 17:16:46 -0500 Message-ID: <20241008221657.1130181-5-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241008221657.1130181-1-terry.bowman@amd.com> References: <20241008221657.1130181-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B074:EE_|IA0PR12MB7577:EE_ X-MS-Office365-Filtering-Correlation-Id: 9cc0c316-2105-4fe0-9291-08dce7e70ace X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|82310400026|1800799024|7416014|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2024 22:17:48.3758 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9cc0c316-2105-4fe0-9291-08dce7e70ace X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B074.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7577 Content-Type: text/plain; charset="utf-8" The AER service driver currently does not manage CXL PCIe port protocol errors reported by CXL root ports, CXL upstream switch ports, and CXL downstream switch ports. Consequently, RAS protocol errors from CXL PCIe port devices are not properly logged or handled. These errors are reported to the OS via the root port's AER correctable and uncorrectable internal error fields. While the AER driver supports handling downstream port protocol errors in restricted CXL host (RCH) mode also known as CXL1.1, it lacks the same functionality for CXL PCIe ports operating in virtual hierarchy (VH) mode, introduced in CXL2.0. To address this gap, update the AER driver to handle CXL PCIe port device protocol correctable errors (CE). The uncorrectable error handling (UCE) will be added in a future patch. Make this update alongside the existing downstream port RCH error handling logic, extending support to CXL PCIe ports in VH. Signed-off-by: Terry Bowman --- drivers/pci/pcie/aer.c | 54 +++++++++++++++++++++++++++++++++--------- 1 file changed, 43 insertions(+), 11 deletions(-) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index dc8b17999001..1c996287d4ce 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -40,6 +40,8 @@ #define AER_MAX_TYPEOF_COR_ERRS 16 /* as per PCI_ERR_COR_STATUS */ #define AER_MAX_TYPEOF_UNCOR_ERRS 27 /* as per PCI_ERR_UNCOR_STATUS*/ =20 +#define CXL_DVSEC_PORT_EXTENSIONS 3 + struct aer_err_source { u32 status; /* PCI_ERR_ROOT_STATUS */ u32 id; /* PCI_ERR_ROOT_ERR_SRC */ @@ -941,6 +943,17 @@ static bool find_source_device(struct pci_dev *parent, return true; } =20 +static bool is_pcie_cxl_port(struct pci_dev *dev) +{ + if ((pci_pcie_type(dev) !=3D PCI_EXP_TYPE_ROOT_PORT) && + (pci_pcie_type(dev) !=3D PCI_EXP_TYPE_UPSTREAM) && + (pci_pcie_type(dev) !=3D PCI_EXP_TYPE_DOWNSTREAM)) + return false; + + return (!!pci_find_dvsec_capability(dev, PCI_VENDOR_ID_CXL, + CXL_DVSEC_PORT_EXTENSIONS)); +} + static bool is_internal_error(struct aer_err_info *info) { if (info->severity =3D=3D AER_CORRECTABLE) @@ -1032,14 +1045,22 @@ static int cxl_rch_handle_error_iter(struct pci_dev= *dev, void *data) =20 static void cxl_handle_error(struct pci_dev *dev, struct aer_err_info *inf= o) { - /* - * Internal errors of an RCEC indicate an AER error in an - * RCH's downstream port. Check and handle them in the CXL.mem - * device driver. - */ - if (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_RC_EC && - is_internal_error(info)) + if (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_RC_EC) pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info); + + if (info->severity =3D=3D AER_CORRECTABLE) { + struct cxl_port_err_hndlrs *cxl_port_hndlrs =3D + find_cxl_port_hndlrs(); + int aer =3D dev->aer_cap; + + if (aer) + pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS, + info->status); + + if (cxl_port_hndlrs && cxl_port_hndlrs->cor_error_detected) + cxl_port_hndlrs->cor_error_detected(dev); + pcie_clear_device_status(dev); + } } =20 static int handles_cxl_error_iter(struct pci_dev *dev, void *data) @@ -1057,9 +1078,13 @@ static bool handles_cxl_errors(struct pci_dev *dev) { bool handles_cxl =3D false; =20 - if (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_RC_EC && - pcie_aer_is_native(dev)) + if (!pcie_aer_is_native(dev)) + return false; + + if (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_RC_EC) pcie_walk_rcec(dev, handles_cxl_error_iter, &handles_cxl); + else + handles_cxl =3D is_pcie_cxl_port(dev); =20 return handles_cxl; } @@ -1077,6 +1102,10 @@ static void cxl_enable_internal_errors(struct pci_de= v *dev) static inline void cxl_enable_internal_errors(struct pci_dev *dev) { } static inline void cxl_handle_error(struct pci_dev *dev, struct aer_err_info *info) { } +static bool handles_cxl_errors(struct pci_dev *dev) +{ + return false; +} #endif =20 void register_cxl_port_hndlrs(struct cxl_port_err_hndlrs *_cxl_port_hndlrs) @@ -1134,8 +1163,11 @@ static void pci_aer_handle_error(struct pci_dev *dev= , struct aer_err_info *info) =20 static void handle_error_source(struct pci_dev *dev, struct aer_err_info *= info) { - cxl_handle_error(dev, info); - pci_aer_handle_error(dev, info); + if (is_internal_error(info) && handles_cxl_errors(dev)) + cxl_handle_error(dev, info); + else + pci_aer_handle_error(dev, info); + pci_dev_put(dev); } =20 --=20 2.34.1 From nobody Wed Nov 27 16:50:51 2024 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2082.outbound.protection.outlook.com [40.107.243.82]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0AD4221503B; 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Tue, 8 Oct 2024 17:17:58 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , , Subject: [PATCH 05/15] cxl/aer/pci: Update AER driver to read UCE fatal status for all CXL PCIe port devices Date: Tue, 8 Oct 2024 17:16:47 -0500 Message-ID: <20241008221657.1130181-6-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241008221657.1130181-1-terry.bowman@amd.com> References: <20241008221657.1130181-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B075:EE_|SA1PR12MB8844:EE_ X-MS-Office365-Filtering-Correlation-Id: de3be1b9-fcf7-41bf-2728-08dce7e7115f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|7416014|36860700013|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2024 22:17:59.3896 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: de3be1b9-fcf7-41bf-2728-08dce7e7115f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B075.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8844 Content-Type: text/plain; charset="utf-8" The AER service driver's aer_get_device_err_info() function does not read uncorrectable (UCE) fatal error status from PCIe upstream port devices. As a result, fatal errors are not logged or handled as needed for CXL PCIe upstream switch port devices. Update the aer_get_device_err_info() function to read the UCE fatal status for all CXL PCIe port devices. The fatal error status will be used in future patches implementing CXL PCIe port error handling and logging. Signed-off-by: Terry Bowman --- drivers/pci/pcie/aer.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 1c996287d4ce..9b2872c8e20d 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1282,6 +1282,7 @@ int aer_get_device_error_info(struct pci_dev *dev, st= ruct aer_err_info *info) } else if (type =3D=3D PCI_EXP_TYPE_ROOT_PORT || type =3D=3D PCI_EXP_TYPE_RC_EC || type =3D=3D PCI_EXP_TYPE_DOWNSTREAM || + type =3D=3D PCI_EXP_TYPE_UPSTREAM || info->severity =3D=3D AER_NONFATAL) { =20 /* Link is still healthy for IO reads */ --=20 2.34.1 From nobody Wed Nov 27 16:50:51 2024 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2084.outbound.protection.outlook.com [40.107.92.84]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D97A22C859; Tue, 8 Oct 2024 22:18:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 8 Oct 2024 17:18:09 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , , Subject: [PATCH 06/15] cxl/aer/pci: Introduce PCI_ERS_RESULT_PANIC to pci_ers_result type Date: Tue, 8 Oct 2024 17:16:48 -0500 Message-ID: <20241008221657.1130181-7-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241008221657.1130181-1-terry.bowman@amd.com> References: <20241008221657.1130181-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B076:EE_|DM4PR12MB5986:EE_ X-MS-Office365-Filtering-Correlation-Id: 2e317adf-bcf2-40e7-be25-08dce7e717e8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|7416014|82310400026|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2024 22:18:10.3733 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2e317adf-bcf2-40e7-be25-08dce7e717e8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B076.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5986 Content-Type: text/plain; charset="utf-8" The CXL AER service will be updated to support CXL PCIe port error handling in the future. These devices will use a system panic during recovery handling. Add PCI_ERS_RESULT_PANIC enumeration to pci_ers_result type. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron --- include/linux/pci.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/linux/pci.h b/include/linux/pci.h index 4cf89a4b4cbc..6f7e7371161d 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -857,6 +857,9 @@ enum pci_ers_result { =20 /* No AER capabilities registered for the driver */ PCI_ERS_RESULT_NO_AER_DRIVER =3D (__force pci_ers_result_t) 6, + + /* Device state requires system panic */ + PCI_ERS_RESULT_PANIC =3D (__force pci_ers_result_t) 7, }; =20 /* PCI bus error event callbacks */ --=20 2.34.1 From nobody Wed Nov 27 16:50:51 2024 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2047.outbound.protection.outlook.com [40.107.94.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2A31215029; Tue, 8 Oct 2024 22:18:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 8 Oct 2024 17:18:20 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , , Subject: [PATCH 07/15] cxl/aer/pci: Add CXL PCIe port uncorrectable error recovery in AER service driver Date: Tue, 8 Oct 2024 17:16:49 -0500 Message-ID: <20241008221657.1130181-8-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241008221657.1130181-1-terry.bowman@amd.com> References: <20241008221657.1130181-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B078:EE_|SA1PR12MB7269:EE_ X-MS-Office365-Filtering-Correlation-Id: e71c4f5c-825e-4a2c-f40c-08dce7e71e86 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|36860700013|1800799024|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2024 22:18:21.4608 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e71c4f5c-825e-4a2c-f40c-08dce7e71e86 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B078.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7269 Content-Type: text/plain; charset="utf-8" The current pcie_do_recovery() handles device recovery as result of uncorrectable errors (UCE). But, CXL port devices require unique recovery handling. Create a cxl_do_recovery() function parallel to pcie_do_recovery(). Add CXL specific handling to the new recovery function. The CXL port UCE recovery must invoke the AER service driver's CXL port UCE callback. This is different than the standard pcie_do_recovery() recovery that calls the pci_driver::err_handler UCE handler instead. Treat all CXL PCIe port UCE errors as fatal and call kernel panic to "recover" the error. A panic is called instead of attempting recovery to avoid potential system corruption. The uncorrectable support added here will be used to complete CXL PCIe port error handling in the future. Signed-off-by: Terry Bowman --- drivers/pci/pci.h | 5 ++ drivers/pci/pcie/aer.c | 5 +- drivers/pci/pcie/err.c | 150 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 159 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 79c8398f3938..d1f5b42fa48d 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -632,6 +632,11 @@ pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, pci_channel_state_t state, pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)); =20 +/* CXL error reporting and recovery */ +pci_ers_result_t cxl_do_recovery(struct pci_dev *dev, + pci_channel_state_t state, + pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)); + bool pcie_wait_for_link(struct pci_dev *pdev, bool active); int pcie_retrain_link(struct pci_dev *pdev, bool use_lt); =20 diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 9b2872c8e20d..81a19028c4e7 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1060,7 +1060,10 @@ static void cxl_handle_error(struct pci_dev *dev, st= ruct aer_err_info *info) if (cxl_port_hndlrs && cxl_port_hndlrs->cor_error_detected) cxl_port_hndlrs->cor_error_detected(dev); pcie_clear_device_status(dev); - } + } else if (info->severity =3D=3D AER_NONFATAL) + cxl_do_recovery(dev, pci_channel_io_normal, aer_root_reset); + else if (info->severity =3D=3D AER_FATAL) + cxl_do_recovery(dev, pci_channel_io_frozen, aer_root_reset); } =20 static int handles_cxl_error_iter(struct pci_dev *dev, void *data) diff --git a/drivers/pci/pcie/err.c b/drivers/pci/pcie/err.c index 31090770fffc..de12f2eb19ef 100644 --- a/drivers/pci/pcie/err.c +++ b/drivers/pci/pcie/err.c @@ -86,6 +86,63 @@ static int report_error_detected(struct pci_dev *dev, return 0; } =20 +static int cxl_report_error_detected(struct pci_dev *dev, + pci_channel_state_t state, + enum pci_ers_result *result) +{ + struct cxl_port_err_hndlrs *cxl_port_hndlrs; + struct pci_driver *pdrv; + pci_ers_result_t vote; + + device_lock(&dev->dev); + cxl_port_hndlrs =3D find_cxl_port_hndlrs(); + pdrv =3D dev->driver; + if (pci_dev_is_disconnected(dev)) { + vote =3D PCI_ERS_RESULT_DISCONNECT; + } else if (!pci_dev_set_io_state(dev, state)) { + pci_info(dev, "can't recover (state transition %u -> %u invalid)\n", + dev->error_state, state); + vote =3D PCI_ERS_RESULT_NONE; + } else if (!cxl_port_hndlrs || !cxl_port_hndlrs->error_detected) { + if (dev->hdr_type !=3D PCI_HEADER_TYPE_BRIDGE) { + vote =3D PCI_ERS_RESULT_NO_AER_DRIVER; + pci_info(dev, "can't recover (no error_detected callback)\n"); + } else { + vote =3D PCI_ERS_RESULT_NONE; + } + } else { + vote =3D cxl_port_hndlrs->error_detected(dev, state); + } + pci_uevent_ers(dev, vote); + *result =3D merge_result(*result, vote); + device_unlock(&dev->dev); + return 0; +} + +static int cxl_report_frozen_detected(struct pci_dev *dev, void *data) +{ + /* + * CXL endpoints report using pci_dev::err_handlers. + * CXL PCIe ports report using aer_rpc::cxl_port_err_handlers. + */ + if (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_ENDPOINT) + return report_error_detected(dev, pci_channel_io_frozen, data); + else + return cxl_report_error_detected(dev, pci_channel_io_frozen, data); +} + +static int cxl_report_normal_detected(struct pci_dev *dev, void *data) +{ + /* + * CXL endpoints report using pci_dev::err_handlers. + * CXL PCIe ports report using aer_rpc::cxl_port_err_handlers. + */ + if (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_ENDPOINT) + return report_error_detected(dev, pci_channel_io_normal, data); + else + return cxl_report_error_detected(dev, pci_channel_io_normal, data); +} + static int pci_pm_runtime_get_sync(struct pci_dev *pdev, void *data) { pm_runtime_get_sync(&pdev->dev); @@ -188,6 +245,28 @@ static void pci_walk_bridge(struct pci_dev *bridge, cb(bridge, userdata); } =20 +/** + * cxl_walk_bridge - walk bridges potentially AER affected + * @bridge: bridge which may be a Port, an RCEC, or an RCiEP + * @cb: callback to be called for each device found + * @userdata: arbitrary pointer to be passed to callback + * + * If the device provided is a bridge, walk the subordinate bus, including + * the device itself and any bridged devices on buses under this bus. Call + * the provided callback on each device found. + * + * If the device provided has no subordinate bus, e.g., an RCEC or RCiEP, + * call the callback on the device itself. + */ +static void cxl_walk_bridge(struct pci_dev *bridge, + int (*cb)(struct pci_dev *, void *), + void *userdata) +{ + cb(bridge, userdata); + if (bridge->subordinate) + pci_walk_bus(bridge->subordinate, cb, userdata); +} + pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, pci_channel_state_t state, pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)) @@ -276,3 +355,74 @@ pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, =20 return status; } + +pci_ers_result_t cxl_do_recovery(struct pci_dev *bridge, + pci_channel_state_t state, + pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)) +{ + struct pci_host_bridge *host =3D pci_find_host_bridge(bridge->bus); + pci_ers_result_t status =3D PCI_ERS_RESULT_CAN_RECOVER; + int type =3D pci_pcie_type(bridge); + + if ((type !=3D PCI_EXP_TYPE_ROOT_PORT) && + (type !=3D PCI_EXP_TYPE_RC_EC) && + (type !=3D PCI_EXP_TYPE_DOWNSTREAM) && + (type !=3D PCI_EXP_TYPE_UPSTREAM)) { + pci_dbg(bridge, "Unsupported device type (%x)\n", type); + return status; + } + + cxl_walk_bridge(bridge, pci_pm_runtime_get_sync, NULL); + + pci_dbg(bridge, "broadcast error_detected message\n"); + if (state =3D=3D pci_channel_io_frozen) { + cxl_walk_bridge(bridge, cxl_report_frozen_detected, &status); + if (reset_subordinates(bridge) !=3D PCI_ERS_RESULT_RECOVERED) { + pci_warn(bridge, "subordinate device reset failed\n"); + goto failed; + } + } else { + cxl_walk_bridge(bridge, cxl_report_normal_detected, &status); + } + + if (status =3D=3D PCI_ERS_RESULT_PANIC) + panic("CXL cachemem error. Invoking panic"); + + if (status =3D=3D PCI_ERS_RESULT_CAN_RECOVER) { + status =3D PCI_ERS_RESULT_RECOVERED; + pci_dbg(bridge, "broadcast mmio_enabled message\n"); + cxl_walk_bridge(bridge, report_mmio_enabled, &status); + } + + if (status =3D=3D PCI_ERS_RESULT_NEED_RESET) { + status =3D PCI_ERS_RESULT_RECOVERED; + pci_dbg(bridge, "broadcast slot_reset message\n"); + report_slot_reset(bridge, &status); + pci_walk_bridge(bridge, report_slot_reset, &status); + } + + if (status !=3D PCI_ERS_RESULT_RECOVERED) + goto failed; + + pci_dbg(bridge, "broadcast resume message\n"); + cxl_walk_bridge(bridge, report_resume, &status); + + if (host->native_aer || pcie_ports_native) { + pcie_clear_device_status(bridge); + pci_aer_clear_nonfatal_status(bridge); + } + + cxl_walk_bridge(bridge, pci_pm_runtime_put, NULL); + + pci_info(bridge, "device recovery successful\n"); + return status; + +failed: + cxl_walk_bridge(bridge, pci_pm_runtime_put, NULL); + + pci_uevent_ers(bridge, PCI_ERS_RESULT_DISCONNECT); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2024 22:18:32.5949 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4e84dd3a-8117-492c-7f87-08dce7e72527 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B074.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB8138 Content-Type: text/plain; charset="utf-8" CXL PCIe port protocol error support will be added in the future. This requires searching for a CXL PCIe port device in the CXL topology as provided by find_cxl_port(). But, find_cxl_port() is defined static and as a result is not callable outside of this source file. Update the find_cxl_port() declaration to be non-static. Signed-off-by: Terry Bowman --- drivers/cxl/core/core.h | 3 +++ drivers/cxl/core/port.c | 4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 72a506c9dbd0..14a8b4d14af6 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -108,4 +108,7 @@ int cxl_update_hmat_access_coordinates(int nid, struct = cxl_region *cxlr, enum access_coordinate_class access); bool cxl_need_node_perf_attrs_update(int nid); =20 +struct cxl_port *find_cxl_port(struct device *dport_dev, + struct cxl_dport **dport); + #endif /* __CXL_CORE_H__ */ diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 1d5007e3795a..089a1f4535c1 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1336,8 +1336,8 @@ static struct cxl_port *__find_cxl_port(struct cxl_fi= nd_port_ctx *ctx) return NULL; } =20 -static struct cxl_port *find_cxl_port(struct device *dport_dev, - struct cxl_dport **dport) +struct cxl_port *find_cxl_port(struct device *dport_dev, + struct cxl_dport **dport) { struct cxl_find_port_ctx ctx =3D { .dport_dev =3D dport_dev, --=20 2.34.1 From nobody Wed Nov 27 16:50:51 2024 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on2086.outbound.protection.outlook.com [40.107.96.86]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A8D53215039; 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Tue, 8 Oct 2024 17:18:42 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , , Subject: [PATCH 09/15] cxl/pci: Map CXL PCIe downstream port RAS registers Date: Tue, 8 Oct 2024 17:16:51 -0500 Message-ID: <20241008221657.1130181-10-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241008221657.1130181-1-terry.bowman@amd.com> References: <20241008221657.1130181-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B071:EE_|PH7PR12MB6860:EE_ X-MS-Office365-Filtering-Correlation-Id: 004e4685-5204-4c26-6379-08dce7e72bd9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026|7416014|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2024 22:18:43.8271 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 004e4685-5204-4c26-6379-08dce7e72bd9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B071.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6860 Content-Type: text/plain; charset="utf-8" RAS registers are not mapped for CXL root ports, CXL downstream switch ports, or CXL upstream switch ports. To prepare for future RAS logging and handling, the driver needs updating to map PCIe port RAS registers. Refactor and rename cxl_setup_parent_dport() to be cxl_init_ep_ports_aer(). Update the function such that it will iterate an endpoint's dports to map the RAS registers. Rename cxl_dport_map_regs() to be cxl_dport_init_aer(). The new function name is a more accurate description of the function's work. This update should also include checking for previously mapped registers within the topology, particularly with CXL switches. Endpoints under a CXL switch may share a common downstream and upstream port, ensure that the registers are only mapped once. Signed-off-by: Terry Bowman --- drivers/cxl/core/pci.c | 37 ++++++++++++++++--------------------- drivers/cxl/cxl.h | 7 ++++--- drivers/cxl/mem.c | 27 +++++++++++++++++++++++++-- 3 files changed, 45 insertions(+), 26 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 51132a575b27..6f7bcdb389bf 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -787,21 +787,6 @@ static void cxl_dport_map_rch_aer(struct cxl_dport *dp= ort) dport->regs.dport_aer =3D dport_aer; } =20 -static void cxl_dport_map_regs(struct cxl_dport *dport) -{ - struct cxl_register_map *map =3D &dport->reg_map; - struct device *dev =3D dport->dport_dev; - - if (!map->component_map.ras.valid) - dev_dbg(dev, "RAS registers not found\n"); - else if (cxl_map_component_regs(map, &dport->regs.component, - BIT(CXL_CM_CAP_CAP_ID_RAS))) - dev_dbg(dev, "Failed to map RAS capability.\n"); - - if (dport->rch) - cxl_dport_map_rch_aer(dport); -} - static void cxl_disable_rch_root_ints(struct cxl_dport *dport) { void __iomem *aer_base =3D dport->regs.dport_aer; @@ -831,7 +816,7 @@ static void cxl_disable_rch_root_ints(struct cxl_dport = *dport) } } =20 -void cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport) +void cxl_dport_init_aer(struct cxl_dport *dport) { struct device *dport_dev =3D dport->dport_dev; =20 @@ -840,15 +825,25 @@ void cxl_setup_parent_dport(struct device *host, stru= ct cxl_dport *dport) =20 if (host_bridge->native_aer) dport->rcrb.aer_cap =3D cxl_rcrb_to_aer(dport_dev, dport->rcrb.base); + + cxl_dport_map_rch_aer(dport); + cxl_disable_rch_root_ints(dport); } =20 - dport->reg_map.host =3D host; - cxl_dport_map_regs(dport); + /* dport may have more than 1 downstream EP. Check if already mapped. */ + if (dport->regs.ras) { + dev_warn(dport_dev, "RAS is already mapped\n"); + return; + } =20 - if (dport->rch) - cxl_disable_rch_root_ints(dport); + dport->reg_map.host =3D dport_dev; + if (cxl_map_component_regs(&dport->reg_map, &dport->regs.component, + BIT(CXL_CM_CAP_CAP_ID_RAS))) { + dev_err(dport_dev, "Failed to map RAS capability.\n"); + return; + } } -EXPORT_SYMBOL_NS_GPL(cxl_setup_parent_dport, CXL); +EXPORT_SYMBOL_NS_GPL(cxl_dport_init_aer, CXL); =20 static void cxl_handle_rdport_cor_ras(struct cxl_dev_state *cxlds, struct cxl_dport *dport) diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 9afb407d438f..cb9e05e2912b 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -592,6 +592,7 @@ struct cxl_dax_region { * @parent_dport: dport that points to this port in the parent * @decoder_ida: allocator for decoder ids * @reg_map: component and ras register mapping parameters + * @uport_regs: mapped component registers * @nr_dports: number of entries in @dports * @hdm_end: track last allocated HDM decoder instance for allocation orde= ring * @commit_end: cursor to track highest committed decoder for commit order= ing @@ -612,6 +613,7 @@ struct cxl_port { struct cxl_dport *parent_dport; struct ida decoder_ida; struct cxl_register_map reg_map; + struct cxl_component_regs uport_regs; int nr_dports; int hdm_end; int commit_end; @@ -761,10 +763,9 @@ struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_po= rt *port, resource_size_t rcrb); =20 #ifdef CONFIG_PCIEAER_CXL -void cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport); +void cxl_dport_init_aer(struct cxl_dport *dport); #else -static inline void cxl_setup_parent_dport(struct device *host, - struct cxl_dport *dport) { } +static inline void cxl_dport_init_aer(struct cxl_dport *dport) { } #endif =20 struct cxl_decoder *to_cxl_decoder(struct device *dev); diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index 7de232eaeb17..b7204f010785 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -45,6 +45,30 @@ static int cxl_mem_dpa_show(struct seq_file *file, void = *data) return 0; } =20 +static bool dev_is_cxl_pci(struct device *dev, u32 pcie_type) +{ + struct pci_dev *pdev; + + if (!dev_is_pci(dev)) + return false; + + pdev =3D to_pci_dev(dev); + if (pci_pcie_type(pdev) !=3D pcie_type) + return false; + + return pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL, + CXL_DVSEC_REG_LOCATOR); +} + +static void cxl_init_ep_ports_aer(struct cxl_ep *ep) +{ + struct cxl_dport *dport =3D ep->dport; + + if (dev_is_cxl_pci(dport->dport_dev, PCI_EXP_TYPE_DOWNSTREAM) || + dev_is_cxl_pci(dport->dport_dev, PCI_EXP_TYPE_ROOT_PORT)) + cxl_dport_init_aer(dport); +} + static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *c= xlmd, struct cxl_dport *parent_dport) { @@ -62,6 +86,7 @@ static int devm_cxl_add_endpoint(struct device *host, str= uct cxl_memdev *cxlmd, =20 ep =3D cxl_ep_load(iter, cxlmd); ep->next =3D down; + cxl_init_ep_ports_aer(ep); } =20 /* Note: endpoint port component registers are derived from @cxlds */ @@ -166,8 +191,6 @@ static int cxl_mem_probe(struct device *dev) else endpoint_parent =3D &parent_port->dev; =20 - cxl_setup_parent_dport(dev, dport); - device_lock(endpoint_parent); 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN3PEPF0000B073.mail.protection.outlook.com (10.167.243.118) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8048.13 via Frontend Transport; Tue, 8 Oct 2024 22:18:55 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 8 Oct 2024 17:18:54 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , , Subject: [PATCH 10/15] cxl/pci: Map CXL PCIe upstream port RAS registers Date: Tue, 8 Oct 2024 17:16:52 -0500 Message-ID: <20241008221657.1130181-11-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241008221657.1130181-1-terry.bowman@amd.com> References: <20241008221657.1130181-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B073:EE_|PH8PR12MB7277:EE_ X-MS-Office365-Filtering-Correlation-Id: a757d139-0184-4cdc-8283-08dce7e7328b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|7416014|376014|1800799024|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2024 22:18:55.0608 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a757d139-0184-4cdc-8283-08dce7e7328b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B073.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7277 Content-Type: text/plain; charset="utf-8" RAS registers are mapped for CXL root ports and CXL downstream but not for CXL upstream switch ports. CXL upstream switch ports' mapped RAS registers are required for handling and logging protocol errors. Introduce 'struct cxl_regs' member into 'struct cxl_port' to store a pointer to the upstream port's mapped RAS registers. Map the the CXL upstream switch port's RAS register block. The upstream port may be have multiple downstream endpoints. Before mapping AER registers check if the registers are already mapped. Signed-off-by: Terry Bowman --- drivers/cxl/core/pci.c | 17 +++++++++++++++++ drivers/cxl/cxl.h | 2 ++ drivers/cxl/mem.c | 3 +++ 3 files changed, 22 insertions(+) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 6f7bcdb389bf..be181358a775 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -816,6 +816,23 @@ static void cxl_disable_rch_root_ints(struct cxl_dport= *dport) } } =20 +void cxl_uport_init_aer(struct cxl_port *port) +{ + /* uport may have more than 1 downstream EP. Check if already mapped. */ + if (port->uport_regs.ras) { + dev_warn(&port->dev, "RAS is already mapped\n"); + return; + } + + port->reg_map.host =3D &port->dev; + if (cxl_map_component_regs(&port->reg_map, &port->uport_regs, + BIT(CXL_CM_CAP_CAP_ID_RAS))) { + dev_err(&port->dev, "Failed to map RAS capability.\n"); + return; + } +} +EXPORT_SYMBOL_NS_GPL(cxl_uport_init_aer, CXL); + void cxl_dport_init_aer(struct cxl_dport *dport) { struct device *dport_dev =3D dport->dport_dev; diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index cb9e05e2912b..7a5f2c33223e 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -764,8 +764,10 @@ struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_po= rt *port, =20 #ifdef CONFIG_PCIEAER_CXL void cxl_dport_init_aer(struct cxl_dport *dport); +void cxl_uport_init_aer(struct cxl_port *port); #else static inline void cxl_dport_init_aer(struct cxl_dport *dport) { } +static inline void cxl_uport_init_aer(struct cxl_port *port) { } #endif =20 struct cxl_decoder *to_cxl_decoder(struct device *dev); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2024 22:19:06.2137 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e635509d-a781-405c-b0ca-08dce7e73933 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B077.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9145 Content-Type: text/plain; charset="utf-8" CXL PCIe port protocol error handling support will be added to the CXL drivers in the future. In preparation, refactor the existing interfaces to support handling all CXL PCIe port protocol errors. The driver's RAS support functions currently rely on a 'struct cxl_dev_state' type parameter, which is not available for CXL port devices. However, since the same CXL RAS capability structure is needed across most CXL components and devices, a common handling approach should be adopted. To accommodate this, update the __cxl_handle_cor_ras() and __cxl_handle_ras() functions to use a `struct device` instead of `struct cxl_dev_state`. No functional changes are introduced. [1] CXL3.1 - 8.2.4 CXL.cache and CXL.mem Registers Signed-off-by: Terry Bowman --- drivers/cxl/core/pci.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index be181358a775..c3c82c051d73 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -686,7 +686,7 @@ void read_cdat_data(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(read_cdat_data, CXL); =20 -static void __cxl_handle_cor_ras(struct cxl_dev_state *cxlds, +static void __cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base) { void __iomem *addr; @@ -699,13 +699,13 @@ static void __cxl_handle_cor_ras(struct cxl_dev_state= *cxlds, status =3D readl(addr); if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); - trace_cxl_aer_correctable_error(cxlds->cxlmd, status); + trace_cxl_aer_correctable_error(to_cxl_memdev(dev), status); } } =20 static void cxl_handle_endpoint_cor_ras(struct cxl_dev_state *cxlds) { - return __cxl_handle_cor_ras(cxlds, cxlds->regs.ras); + return __cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlds->regs.ras); } =20 /* CXL spec rev3.0 8.2.4.16.1 */ @@ -729,8 +729,7 @@ static void header_log_copy(void __iomem *ras_base, u32= *log) * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. */ -static bool __cxl_handle_ras(struct cxl_dev_state *cxlds, - void __iomem *ras_base) +static bool __cxl_handle_ras(struct device *dev, void __iomem *ras_base) { u32 hl[CXL_HEADERLOG_SIZE_U32]; void __iomem *addr; @@ -757,7 +756,7 @@ static bool __cxl_handle_ras(struct cxl_dev_state *cxld= s, } =20 header_log_copy(ras_base, hl); - trace_cxl_aer_uncorrectable_error(cxlds->cxlmd, status, fe, hl); + trace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl); writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); =20 return true; @@ -765,7 +764,7 @@ static bool __cxl_handle_ras(struct cxl_dev_state *cxld= s, =20 static bool cxl_handle_endpoint_ras(struct cxl_dev_state *cxlds) { - return __cxl_handle_ras(cxlds, cxlds->regs.ras); + return __cxl_handle_ras(&cxlds->cxlmd->dev, cxlds->regs.ras); } =20 #ifdef CONFIG_PCIEAER_CXL @@ -865,13 +864,13 @@ EXPORT_SYMBOL_NS_GPL(cxl_dport_init_aer, CXL); static void cxl_handle_rdport_cor_ras(struct cxl_dev_state *cxlds, struct cxl_dport *dport) { - return __cxl_handle_cor_ras(cxlds, dport->regs.ras); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2024 22:19:17.3675 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 29edf4d0-e21d-4360-a11e-08dce7e73fd9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B078.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4084 Content-Type: text/plain; charset="utf-8" The CXL drivers do not contain error handlers for CXL PCIe port device protocol errors. These are needed in order to handle and log RAS protocol errors. Add CXL PCIe port protocol error handlers to the CXL driver. Provide access to RAS registers for the specific CXL PCIe port types: root port, upstream switch port, and downstream switch port. Also, register and unregister the CXL PCIe port error handlers with the AER service driver using register_cxl_port_err_hndlrs() and unregister_cxl_port_err_hndlrs(). Invoke the registration from cxl_pci_driver_init() and the unregistration from cxl_pci_driver_exit(). [1] CXL3.1 - 12.2.2 CXL Root Ports, Downstream Switch Ports, and Upstream Switch Ports Signed-off-by: Terry Bowman --- drivers/cxl/core/pci.c | 83 ++++++++++++++++++++++++++++++++++++++++++ drivers/cxl/cxl.h | 5 +++ drivers/cxl/pci.c | 8 ++++ 3 files changed, 96 insertions(+) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index c3c82c051d73..7e3770f7a955 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -815,6 +815,89 @@ static void cxl_disable_rch_root_ints(struct cxl_dport= *dport) } } =20 +static int match_uport(struct device *dev, const void *data) +{ + struct device *uport_dev =3D (struct device *)data; + struct cxl_port *port; + + if (!is_cxl_port(dev)) + return 0; + + port =3D to_cxl_port(dev); + + return port->uport_dev =3D=3D uport_dev; +} + +static void __iomem *cxl_pci_port_ras(struct pci_dev *pdev) +{ + void __iomem *ras_base; + struct cxl_port *port; + + if (!pdev) + return NULL; + + if ((pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_ROOT_PORT) || + (pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_DOWNSTREAM)) { + struct cxl_dport *dport; + + port =3D find_cxl_port(&pdev->dev, &dport); + ras_base =3D dport ? dport->regs.ras : NULL; + put_device(&port->dev); + return ras_base; + } else if (pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_UPSTREAM) { + struct device *port_dev __free(put_device); + + port_dev =3D bus_find_device(&cxl_bus_type, NULL, &pdev->dev, match_upor= t); + if (!port_dev) + return NULL; + + port =3D to_cxl_port(port_dev); + if (!port) + return NULL; + + ras_base =3D port ? port->uport_regs.ras : NULL; + return ras_base; + } + + return NULL; +} + +void cxl_cor_port_err_detected(struct pci_dev *pdev) +{ + void __iomem *ras_base =3D cxl_pci_port_ras(pdev); + + __cxl_handle_cor_ras(&pdev->dev, ras_base); +} +EXPORT_SYMBOL_NS_GPL(cxl_cor_port_err_detected, CXL); + +pci_ers_result_t cxl_port_err_detected(struct pci_dev *pdev, pci_channel_s= tate_t state) +{ + void __iomem *ras_base =3D cxl_pci_port_ras(pdev); + bool ue; + + ue =3D __cxl_handle_ras(&pdev->dev, ras_base); + if (ue) + return PCI_ERS_RESULT_PANIC; + + switch (state) { + case pci_channel_io_normal: + dev_err(&pdev->dev, "%s():%d: pci_channel_io_normal\n", + __func__, __LINE__); + return PCI_ERS_RESULT_CAN_RECOVER; + case pci_channel_io_frozen: + dev_err(&pdev->dev, "%s():%d: pci_channel_io_frozen\n", + __func__, __LINE__); + return PCI_ERS_RESULT_NEED_RESET; + case pci_channel_io_perm_failure: + dev_err(&pdev->dev, "%s():%d: pci_channel_io_perm_failure\n", + __func__, __LINE__); + return PCI_ERS_RESULT_DISCONNECT; + } + + return PCI_ERS_RESULT_NEED_RESET; +} +EXPORT_SYMBOL_NS_GPL(cxl_port_err_detected, CXL); + void cxl_uport_init_aer(struct cxl_port *port) { /* uport may have more than 1 downstream EP. Check if already mapped. */ diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 7a5f2c33223e..06fcde4b88b5 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -10,6 +10,7 @@ #include #include #include +#include #include =20 extern const struct nvdimm_security_ops *cxl_security_ops; @@ -901,6 +902,10 @@ void cxl_coordinates_combine(struct access_coordinate = *out, =20 bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port); =20 +pci_ers_result_t cxl_port_err_detected(struct pci_dev *pdev, + pci_channel_state_t state); +void cxl_cor_port_err_detected(struct pci_dev *pdev); + /* * Unit test builds overrides this to __weak, find the 'strong' version * of these symbols in tools/testing/cxl/. diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 4be35dc22202..9179b34c35bb 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -978,6 +978,11 @@ static void cxl_reset_done(struct pci_dev *pdev) } } =20 +static struct cxl_port_err_hndlrs cxl_port_hndlrs =3D { + .error_detected =3D cxl_port_err_detected, + .cor_error_detected =3D cxl_cor_port_err_detected +}; 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Tue, 8 Oct 2024 22:19:28 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN3PEPF0000B074.mail.protection.outlook.com (10.167.243.119) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8048.13 via Frontend Transport; Tue, 8 Oct 2024 22:19:28 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 8 Oct 2024 17:19:27 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , , Subject: [PATCH 13/15] cxl/pci: Add trace logging for CXL PCIe port RAS errors Date: Tue, 8 Oct 2024 17:16:55 -0500 Message-ID: <20241008221657.1130181-14-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241008221657.1130181-1-terry.bowman@amd.com> References: <20241008221657.1130181-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B074:EE_|IA0PR12MB8326:EE_ X-MS-Office365-Filtering-Correlation-Id: 2d056cbb-ef32-4b20-31ea-08dce7e7467a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|7416014|376014|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2024 22:19:28.4861 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2d056cbb-ef32-4b20-31ea-08dce7e7467a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B074.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8326 Content-Type: text/plain; charset="utf-8" The CXL drivers use kernel trace functions for logging endpoint and RCH downstream port RAS errors. However, similar functionality is required for CXL root ports, CXL downstream switch ports, and CXL upstream switch ports. Introduce trace logging functions for both RAS correctable and uncorrectable errors specific to CXL PCIe ports. Additionally, update the PCIe port error handlers to invoke these new trace functions. Signed-off-by: Terry Bowman --- drivers/cxl/core/pci.c | 16 ++++++++++---- drivers/cxl/core/trace.h | 47 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+), 4 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 7e3770f7a955..4706113d2582 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -697,10 +697,14 @@ static void __cxl_handle_cor_ras(struct device *dev, =20 addr =3D ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET; status =3D readl(addr); - if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { - writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); + if (!(status & CXL_RAS_CORRECTABLE_STATUS_MASK)) + return; + writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); + + if (is_cxl_memdev(dev)) trace_cxl_aer_correctable_error(to_cxl_memdev(dev), status); - } + else if (dev_is_pci(dev)) + trace_cxl_port_aer_correctable_error(dev, status); } =20 static void cxl_handle_endpoint_cor_ras(struct cxl_dev_state *cxlds) @@ -756,7 +760,11 @@ static bool __cxl_handle_ras(struct device *dev, void = __iomem *ras_base) } =20 header_log_copy(ras_base, hl); - trace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl); + if (is_cxl_memdev(dev)) + trace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl); + else if (dev_is_pci(dev)) + trace_cxl_port_aer_uncorrectable_error(dev, status, fe, hl); + writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); =20 return true; diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h index 9167cfba7f59..6305c0eea627 100644 --- a/drivers/cxl/core/trace.h +++ b/drivers/cxl/core/trace.h @@ -48,6 +48,34 @@ { CXL_RAS_UC_IDE_RX_ERR, "IDE Rx Error" } \ ) =20 +TRACE_EVENT(cxl_port_aer_uncorrectable_error, + TP_PROTO(struct device *dev, u32 status, u32 fe, u32 *hl), + TP_ARGS(dev, status, fe, hl), + TP_STRUCT__entry( + __string(devname, dev_name(dev)) + __string(host, dev_name(dev->parent)) + __field(u32, status) + __field(u32, first_error) + __array(u32, header_log, CXL_HEADERLOG_SIZE_U32) + ), + TP_fast_assign( + __assign_str(devname); + __assign_str(host); + __entry->status =3D status; + __entry->first_error =3D fe; + /* + * Embed the 512B headerlog data for user app retrieval and + * parsing, but no need to print this in the trace buffer. + */ + memcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE); + ), + TP_printk("device=3D%s host=3D%s status: '%s' first_error: '%s'", + __get_str(devname), __get_str(host), + show_uc_errs(__entry->status), + show_uc_errs(__entry->first_error) + ) +); + TRACE_EVENT(cxl_aer_uncorrectable_error, TP_PROTO(const struct cxl_memdev *cxlmd, u32 status, u32 fe, u32 *hl), TP_ARGS(cxlmd, status, fe, hl), @@ -96,6 +124,25 @@ TRACE_EVENT(cxl_aer_uncorrectable_error, { CXL_RAS_CE_PHYS_LAYER_ERR, "Received Error From Physical Layer" } \ ) =20 +TRACE_EVENT(cxl_port_aer_correctable_error, + TP_PROTO(struct device *dev, u32 status), + TP_ARGS(dev, status), + TP_STRUCT__entry( + __string(devname, dev_name(dev)) + __string(host, dev_name(dev->parent)) + __field(u32, status) + ), + TP_fast_assign( + __assign_str(devname); + __assign_str(host); + __entry->status =3D status; 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Tue, 8 Oct 2024 22:19:39 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN3PEPF0000B071.mail.protection.outlook.com (10.167.243.116) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8048.13 via Frontend Transport; Tue, 8 Oct 2024 22:19:39 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 8 Oct 2024 17:19:38 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , , Subject: [PATCH 14/15] cxl/aer/pci: Export pci_aer_unmask_internal_errors() Date: Tue, 8 Oct 2024 17:16:56 -0500 Message-ID: <20241008221657.1130181-15-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241008221657.1130181-1-terry.bowman@amd.com> References: <20241008221657.1130181-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B071:EE_|DS7PR12MB5933:EE_ X-MS-Office365-Filtering-Correlation-Id: eb7182a3-222b-4b78-d284-08dce7e74d11 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|36860700013|1800799024|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2024 22:19:39.5618 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eb7182a3-222b-4b78-d284-08dce7e74d11 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B071.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5933 Content-Type: text/plain; charset="utf-8" The CXL driver needs to enable AER correctable and uncorrectable internal errors in order to receive notification of protocol errors. pci_aer_unmask_internal_errors() is currently defined as 'static' in the AER service driver. Update the AER service driver, exporting pci_aer_unmask_internal_errors() to CXL namespace. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron --- drivers/pci/pcie/aer.c | 6 ++++-- include/linux/aer.h | 2 ++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 81a19028c4e7..1b4004932084 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -962,7 +962,6 @@ static bool is_internal_error(struct aer_err_info *info) return info->status & PCI_ERR_UNC_INTN; } =20 -#ifdef CONFIG_PCIEAER_CXL /** * pci_aer_unmask_internal_errors - unmask internal errors * @dev: pointer to the pcie_dev data structure @@ -973,7 +972,7 @@ static bool is_internal_error(struct aer_err_info *info) * Note: AER must be enabled and supported by the device which must be * checked in advance, e.g. with pcie_aer_is_native(). */ -static void pci_aer_unmask_internal_errors(struct pci_dev *dev) +void pci_aer_unmask_internal_errors(struct pci_dev *dev) { int aer =3D dev->aer_cap; u32 mask; @@ -986,6 +985,9 @@ static void pci_aer_unmask_internal_errors(struct pci_d= ev *dev) mask &=3D ~PCI_ERR_COR_INTERNAL; pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, mask); } +EXPORT_SYMBOL_NS_GPL(pci_aer_unmask_internal_errors, CXL); + +#ifdef CONFIG_PCIEAER_CXL =20 static bool is_cxl_mem_dev(struct pci_dev *dev) { diff --git a/include/linux/aer.h b/include/linux/aer.h index 67fd04c5ae2b..c43d2b60b992 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -69,5 +69,7 @@ struct cxl_port_err_hndlrs { void register_cxl_port_hndlrs(struct cxl_port_err_hndlrs *_cxl_port_hndlrs= ); void unregister_cxl_port_hndlrs(void); struct cxl_port_err_hndlrs *find_cxl_port_hndlrs(void); + +void pci_aer_unmask_internal_errors(struct pci_dev *dev); #endif //_AER_H_ =20 --=20 2.34.1 From nobody Wed Nov 27 16:50:51 2024 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2087.outbound.protection.outlook.com [40.107.223.87]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D78521791F; 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Tue, 8 Oct 2024 17:19:49 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , , Subject: [PATCH 15/15] cxl/pci: Enable internal CE/UCE interrupts for CXL PCIe port devices Date: Tue, 8 Oct 2024 17:16:57 -0500 Message-ID: <20241008221657.1130181-16-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241008221657.1130181-1-terry.bowman@amd.com> References: <20241008221657.1130181-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B074:EE_|SJ2PR12MB7920:EE_ X-MS-Office365-Filtering-Correlation-Id: 8607cf10-952b-4600-14af-08dce7e753a3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|7416014|1800799024|376014|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2024 22:19:50.5644 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8607cf10-952b-4600-14af-08dce7e753a3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B074.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7920 Content-Type: text/plain; charset="utf-8" The AER service drivers and CXL drivers are updated to handle PCIe port protocol errors. But, the PCIe AER correctable and uncorrectable internal errors are mask disabled for the PCIe port devices. Enable the AER internal errors for CXL PCIe port devices. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron --- drivers/cxl/core/pci.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 4706113d2582..1d84a7022c4d 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -908,6 +908,7 @@ EXPORT_SYMBOL_NS_GPL(cxl_port_err_detected, CXL); =20 void cxl_uport_init_aer(struct cxl_port *port) { + struct pci_dev *pdev =3D to_pci_dev(port->uport_dev); /* uport may have more than 1 downstream EP. Check if already mapped. */ if (port->uport_regs.ras) { dev_warn(&port->dev, "RAS is already mapped\n"); @@ -920,12 +921,14 @@ void cxl_uport_init_aer(struct cxl_port *port) dev_err(&port->dev, "Failed to map RAS capability.\n"); return; } + pci_aer_unmask_internal_errors(pdev); } EXPORT_SYMBOL_NS_GPL(cxl_uport_init_aer, CXL); =20 void cxl_dport_init_aer(struct cxl_dport *dport) { struct device *dport_dev =3D dport->dport_dev; + struct pci_dev *pdev =3D to_pci_dev(dport_dev); =20 if (dport->rch) { struct pci_host_bridge *host_bridge =3D to_pci_host_bridge(dport_dev); @@ -949,6 +952,7 @@ void cxl_dport_init_aer(struct cxl_dport *dport) dev_err(dport_dev, "Failed to map RAS capability.\n"); return; } + pci_aer_unmask_internal_errors(pdev); } EXPORT_SYMBOL_NS_GPL(cxl_dport_init_aer, CXL); =20 --=20 2.34.1