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([2405:201:1e:f1d5:c7a7:6c1f:8104:8963]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71dfea52097sm4650939b3a.103.2024.10.08.12.16.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 12:16:35 -0700 (PDT) From: Advait Dhamorikar To: alexander.deucher@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, simona@ffwll.ch, leo.liu@amd.com, sathishkumar.sundararaju@amd.com, saleemkhan.jamadar@amd.com, sonny.jiang@amd.com Cc: amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, skhan@linuxfoundation.org, anupnewsmail@gmail.com, Advait Dhamorikar Subject: [PATCH-next v3] drm/amdgpu: Cleanup shift coding style Date: Wed, 9 Oct 2024 00:46:23 +0530 Message-Id: <20241008191623.8171-1-advaitdhamorikar@gmail.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Improves the coding style by updating bit-shift operations in the amdgpu_jpeg.c driver file. It ensures consistency and avoids potential issues by explicitly using 1U and 1ULL for unsigned and unsigned long long shifts in all relevant instances. Signed-off-by: Advait Dhamorikar --- v1->v2: address review comments https://lore.kernel.org/lkml/CAJ7bepJrm9tJJMSZXz0B_94y8817X4oFpwnrTmUHeagOF= gVL7g@mail.gmail.com/ v2->v3: update changelog and add additional 1U cleanups https://lore.kernel.org/lkml/CADnq5_OgZvTgUDvDqDikoUh28jTRm2mOAVV6zAEtWE9RH= TFkyA@mail.gmail.com/ drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c b/drivers/gpu/drm/amd= /amdgpu/amdgpu_jpeg.c index 95e2796919fc..995bc28b4fe6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c @@ -47,7 +47,7 @@ int amdgpu_jpeg_sw_init(struct amdgpu_device *adev) adev->jpeg.indirect_sram =3D true; =20 for (i =3D 0; i < adev->jpeg.num_jpeg_inst; i++) { - if (adev->jpeg.harvest_config & (1 << i)) + if (adev->jpeg.harvest_config & (1U << i)) continue; =20 if (adev->jpeg.indirect_sram) { @@ -73,7 +73,7 @@ int amdgpu_jpeg_sw_fini(struct amdgpu_device *adev) int i, j; =20 for (i =3D 0; i < adev->jpeg.num_jpeg_inst; ++i) { - if (adev->jpeg.harvest_config & (1 << i)) + if (adev->jpeg.harvest_config & (1U << i)) continue; =20 amdgpu_bo_free_kernel( @@ -110,7 +110,7 @@ static void amdgpu_jpeg_idle_work_handler(struct work_s= truct *work) unsigned int i, j; =20 for (i =3D 0; i < adev->jpeg.num_jpeg_inst; ++i) { - if (adev->jpeg.harvest_config & (1 << i)) + if (adev->jpeg.harvest_config & (1U << i)) continue; =20 for (j =3D 0; j < adev->jpeg.num_jpeg_rings; ++j) @@ -357,7 +357,7 @@ static int amdgpu_debugfs_jpeg_sched_mask_set(void *dat= a, u64 val) if (!adev) return -ENODEV; =20 - mask =3D (1 << (adev->jpeg.num_jpeg_inst * adev->jpeg.num_jpeg_rings)) - = 1; + mask =3D (1ULL << (adev->jpeg.num_jpeg_inst * adev->jpeg.num_jpeg_rings))= - 1; if ((val & mask) =3D=3D 0) return -EINVAL; =20 @@ -388,7 +388,7 @@ static int amdgpu_debugfs_jpeg_sched_mask_get(void *dat= a, u64 *val) for (j =3D 0; j < adev->jpeg.num_jpeg_rings; ++j) { ring =3D &adev->jpeg.inst[i].ring_dec[j]; if (ring->sched.ready) - mask |=3D 1 << ((i * adev->jpeg.num_jpeg_rings) + j); + mask |=3D 1ULL << ((i * adev->jpeg.num_jpeg_rings) + j); } } *val =3D mask; --=20 2.34.1