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Signed-off-by: Lad Prabhakar --- v1->v2 - Set opp-microvolt to 800000 for frequencies below 1.1GHz --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g057.dtsi index 1ad5a1b6917f..4bbe75b81f54 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -20,6 +20,39 @@ audio_extal_clk: audio-clk { clock-frequency =3D <0>; }; =20 + /* + * The default cluster table is based on the assumption that the PLLCA55 = clock + * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to + * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally = can be + * clocked to 1.8GHz as well). The table below should be overridden in th= e board + * DTS based on the PLLCA55 clock frequency. + */ + cluster0_opp: opp-table-0 { + compatible =3D "operating-points-v2"; + + opp-1700000000 { + opp-hz =3D /bits/ 64 <1700000000>; + opp-microvolt =3D <900000>; + clock-latency-ns =3D <300000>; + }; + opp-850000000 { + opp-hz =3D /bits/ 64 <850000000>; + opp-microvolt =3D <800000>; + clock-latency-ns =3D <300000>; + }; + opp-425000000 { + opp-hz =3D /bits/ 64 <425000000>; + opp-microvolt =3D <800000>; + clock-latency-ns =3D <300000>; + }; + opp-212500000 { + opp-hz =3D /bits/ 64 <212500000>; + opp-microvolt =3D <800000>; + clock-latency-ns =3D <300000>; + opp-suspend; + }; + }; + cpus { #address-cells =3D <1>; #size-cells =3D <0>; @@ -30,6 +63,8 @@ cpu0: cpu@0 { device_type =3D "cpu"; next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; + clocks =3D <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK0>; + operating-points-v2 =3D <&cluster0_opp>; }; =20 cpu1: cpu@100 { @@ -38,6 +73,8 @@ cpu1: cpu@100 { device_type =3D "cpu"; next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; + clocks =3D <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK1>; + operating-points-v2 =3D <&cluster0_opp>; }; =20 cpu2: cpu@200 { @@ -46,6 +83,8 @@ cpu2: cpu@200 { device_type =3D "cpu"; next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; + clocks =3D <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK2>; + operating-points-v2 =3D <&cluster0_opp>; }; =20 cpu3: cpu@300 { @@ -54,6 +93,8 @@ cpu3: cpu@300 { device_type =3D "cpu"; next-level-cache =3D <&L3_CA55>; enable-method =3D "psci"; + clocks =3D <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK3>; + operating-points-v2 =3D <&cluster0_opp>; }; =20 L3_CA55: cache-controller-0 { --=20 2.43.0