From nobody Wed Nov 27 19:36:23 2024 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C31F51E0483; Tue, 8 Oct 2024 14:46:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=116.203.77.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728398809; cv=none; b=PwNfySltEM5W9X66Zla6K54m//gT348dLwKDz2MtWUq+4WvHoN5CgGVlsCsvYJhCnyKbAbqzWBby6TTi4NMLmolXg7UvCSth31uTS/bH6KJkl8Asr4GBA4sWNdF2L80STAoyJ+ALH7qtKh1/iCyUfCNIC++4bXwKC5F+T4LKUnk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728398809; c=relaxed/simple; bh=UUutSx+gDrSV47eLsMwHxM5rwhM3H7WeUMuQZmxxPsU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gPyxbyHI2sZS5Tnj7mJvYMg3+jMmCUeh+CuYJCMYT+UQSdArac9LcxkxlK7/ZHrHheKyXS3on5gVTToREF9jvFhPJUVbkIlVOf9DL5iKnFAnc0xZLESrN3VNA3z97bDz0vU6zryz/Z8EBmrZc1y0j+muujH8KCx/WVg7gxetjOM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=fris.de; spf=fail smtp.mailfrom=fris.de; arc=none smtp.client-ip=116.203.77.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=fris.de Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=fris.de Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 19DE2BFB5A; Tue, 8 Oct 2024 16:38:42 +0200 (CEST) From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, imx@lists.linux.dev, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Frieder Schrempf , Fabio Estevam , Pengutronix Kernel Team Subject: [PATCH v3 3/4] arm64: dts: imx8mm-kontron: Add support for display bridges on BL i.MX8MM Date: Tue, 8 Oct 2024 16:37:45 +0200 Message-ID: <20241008143804.126795-4-frieder@fris.de> In-Reply-To: <20241008143804.126795-1-frieder@fris.de> References: <20241008143804.126795-1-frieder@fris.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf The Kontron Electronics BL i.MX8MM has oboard disply bridges for DSI->HDMI and DSI->LVDS conversion. The DSI interface is muxed by a GPIO-controlled switch to one of these two bridges. By default the HDMI bridge is enabled. The LVDS bridge can be selected by loading an additional (panel-specific) overlay. Signed-off-by: Frieder Schrempf --- Changes for v3: * none Changes for v2: * Remove blank lines from hdmi node * Fix order of lvds and hdmi nodes within i2c * Remove the unneeded deletion of samsung,pll-clock-frequency * Use the existing MIPI DSI output port from imx8mm.dtsi --- .../boot/dts/freescale/imx8mm-kontron-bl.dts | 131 ++++++++++++++++++ 1 file changed, 131 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts b/arch/arm= 64/boot/dts/freescale/imx8mm-kontron-bl.dts index aab8e24216501..a8ef4fba16a9e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts @@ -25,6 +25,17 @@ osc_can: clock-osc-can { clock-output-names =3D "osc-can"; }; =20 + hdmi-out { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi_in_conn: endpoint { + remote-endpoint =3D <&bridge_out_conn>; + }; + }; + }; + leds { compatible =3D "gpio-leds"; pinctrl-names =3D "default"; @@ -132,6 +143,86 @@ ethphy: ethernet-phy@0 { }; }; =20 +&gpio4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio4>; + + dsi_mux_sel_hdmi: dsi-mux-sel-hdmi-hog { + gpio-hog; + gpios =3D <14 GPIO_ACTIVE_HIGH>; + output-high; + line-name =3D "dsi-mux-sel"; + }; + + dsi_mux_sel_lvds: dsi-mux-sel-lvds-hog { + gpio-hog; + gpios =3D <14 GPIO_ACTIVE_HIGH>; + output-low; + line-name =3D "dsi-mux-sel"; + status =3D "disabled"; + }; + + dsi-mux-oe-hog { + gpio-hog; + gpios =3D <15 GPIO_ACTIVE_LOW>; + output-high; + line-name =3D "dsi-mux-oe"; + }; +}; + +&i2c3 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c3>; + status =3D "okay"; + + lvds: bridge@2c { + compatible =3D "ti,sn65dsi84"; + reg =3D <0x2c>; + enable-gpios =3D <&gpio4 26 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_sn65dsi84>; + status =3D "disabled"; + }; + + hdmi: hdmi@39 { + compatible =3D "adi,adv7535"; + reg =3D <0x39>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_adv7535>; + adi,dsi-lanes =3D <4>; + interrupt-parent =3D <&gpio4>; + interrupts =3D <16 IRQ_TYPE_LEVEL_LOW>; + a2vdd-supply =3D <®_vdd_1v8>; + avdd-supply =3D <®_vdd_1v8>; + dvdd-supply =3D <®_vdd_1v8>; + pvdd-supply =3D <®_vdd_1v8>; + v1p2-supply =3D <®_vdd_1v8>; + v3p3-supply =3D <®_vdd_3v3>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + bridge_in_dsi_hdmi: endpoint { + remote-endpoint =3D <&mipi_dsi_out>; + }; + }; + + port@1 { + reg =3D <1>; + + bridge_out_conn: endpoint { + remote-endpoint =3D <&hdmi_in_conn>; + }; + }; + }; + }; +}; + &i2c4 { clock-frequency =3D <100000>; pinctrl-names =3D "default"; @@ -144,6 +235,19 @@ rx8900: rtc@32 { }; }; =20 +&lcdif { + status =3D "okay"; +}; + +&mipi_dsi { + samsung,esc-clock-frequency =3D <54000000>; + status =3D "okay"; +}; + +&mipi_dsi_out { + remote-endpoint =3D <&bridge_in_dsi_hdmi>; +}; + &pwm2 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_pwm2>; @@ -207,6 +311,12 @@ &iomuxc { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_gpio>; =20 + pinctrl_adv7535: adv7535grp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 + >; + }; + pinctrl_can: cangrp { fsl,pins =3D < MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 @@ -277,6 +387,20 @@ MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 >; }; =20 + pinctrl_gpio4: gpio4grp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000083 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000083 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins =3D < MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000083 @@ -290,6 +414,13 @@ MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 >; }; =20 + pinctrl_sn65dsi84: sn65dsi84grp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x19 + MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x19 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins =3D < MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x0 --=20 2.46.0