From nobody Wed Nov 27 20:39:48 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 301FD1DF25D; Tue, 8 Oct 2024 12:55:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728392103; cv=none; b=k3C7+THZWfXiwQfZqU+MRfAABo+4jyo7PTGqUIBOJ1btmShwauz9vM0/S1OnEdhqteBuJW+snVS+HrLLfCjY6Xc/u8iDUjLBYjD7ZgzAAbqazAUKjkSJhMGgn/ekGpRSxARXtJPF+kMZLwzyF1mju5H4l6JFcGjze2MJQBMocP0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728392103; c=relaxed/simple; bh=+dQ4gFEXMYvpBW3zZel9F+W3kW5UTQuhM1w5QKPt/RM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=A9b8qoTRBzDzjr6GH3Pn4LTD9aTNfngKndvPIfC2/HgczPRjBEXqVX171tTXH1hL246Ph4WavqK+jLGXOa7DZo21OjCAMXRrSj53aC9mdclqNLxFHE5iat73tGFPsyaN1zN0j3i/oYxZVQ4N12W4wLFJyh1tZCtoZx5yKCI+KgU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=oYqlYyVv; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="oYqlYyVv" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4985vcho021306; Tue, 8 Oct 2024 12:54:46 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= vOnI2NZ1hyA6gdnw6KJkUQLPoFuXV7NXF0G6EDDR/Vs=; b=oYqlYyVvP9C9vx0o GTJYabDJLMv5L3jDVV6xlZHufAW7wc7k49J6FeWHOOOmJTF3sXSMQS+swasnebwd npEvKpaWyVs2HjgTbjEjEMykL8uOQg8N10ICRKAOr6SVmlGHBDDUZIaTiT5RbmAE aJt0e3TEVETS10m/nVhAPzK6smSPamwTo3xyHWT/1gDLGoVL2LMJp9VzyaIt8SdI vmmx7ZJzr+zDPUBZb1fAflOR4o0WaRUse7USXhyQXcnxXMDtsFblJG+7iKZgkqDP KscP3QNM1+RN1nf21SJzaLy0/Haavk8tUJ+jyE15ophSdoXJL27WRMjwnBeX90GD GpggOw== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 422xr5qcfm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 08 Oct 2024 12:54:46 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 498CsjGo018087 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 8 Oct 2024 12:54:45 GMT Received: from hu-bibekkum-hyd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 8 Oct 2024 05:54:41 -0700 From: Bibek Kumar Patro To: , , , , , , , , , CC: , , , , Subject: [PATCH v16 2/5] iommu/arm-smmu: refactor qcom_smmu structure to include single pointer Date: Tue, 8 Oct 2024 18:24:07 +0530 Message-ID: <20241008125410.3422512-3-quic_bibekkum@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241008125410.3422512-1-quic_bibekkum@quicinc.com> References: <20241008125410.3422512-1-quic_bibekkum@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: CR1Yqc9Q5dVxKr8M04LG3YTeZ5tfUTW6 X-Proofpoint-ORIG-GUID: CR1Yqc9Q5dVxKr8M04LG3YTeZ5tfUTW6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 clxscore=1015 mlxlogscore=999 priorityscore=1501 impostorscore=0 adultscore=0 mlxscore=0 phishscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410080081 Content-Type: text/plain; charset="utf-8" qcom_smmu_match_data is static and constant so refactor qcom_smmu to store single pointer to qcom_smmu_match_data instead of replicating multiple child members of the same and handle the further dereferences in the places that want them. Suggested-by: Robin Murphy Reviewed-by: Dmitry Baryshkov Signed-off-by: Bibek Kumar Patro Reviewed-by: Rob Clark --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c | 2 +- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 +- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c b/drivers/iom= mu/arm/arm-smmu/arm-smmu-qcom-debug.c index 548783f3f8e8..d03b2239baad 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c @@ -73,7 +73,7 @@ void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smm= u) if (__ratelimit(&rs)) { dev_err(smmu->dev, "TLB sync timed out -- SMMU may be deadlocked\n"); - cfg =3D qsmmu->cfg; + cfg =3D qsmmu->data->cfg; if (!cfg) return; diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm= /arm-smmu/arm-smmu-qcom.c index 0cb10b354802..6e0a2a43e45a 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -534,7 +534,7 @@ static struct arm_smmu_device *qcom_smmu_create(struct = arm_smmu_device *smmu, return ERR_PTR(-ENOMEM); qsmmu->smmu.impl =3D impl; - qsmmu->cfg =3D data->cfg; + qsmmu->data =3D data; return &qsmmu->smmu; } diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h b/drivers/iommu/arm= /arm-smmu/arm-smmu-qcom.h index 3c134d1a6277..b55cd3e3ae48 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h @@ -8,7 +8,7 @@ struct qcom_smmu { struct arm_smmu_device smmu; - const struct qcom_smmu_config *cfg; + const struct qcom_smmu_match_data *data; bool bypass_quirk; u8 bypass_cbndx; u32 stall_enabled; -- 2.34.1