From nobody Wed Nov 27 21:31:31 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D0801C9B99; Tue, 8 Oct 2024 12:54:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728392098; cv=none; b=tRwAfpbMqWr2ZVsMC6gjzxcCiQt2iIBYPED8lMhe0wpxkKi3CYwU+3iskLw+fiscJlvYhk9zIKvEZpGDQWUxfi6s4BbT++9Jn7JBRJ0vZPuFBRmaDMlAtJ4kSCKDGScXG7ij4ffHIwrHIZnjjUjBjxnns4HNpLQXT5oNdqek3NQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728392098; c=relaxed/simple; bh=a5u0nrsBvJPFtQqVD782CMJ9K5DcjHsuW8ISsjQp5f0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=g16xxRySyQaB7XSu4CTJ7BESW1Fn5wAZ7DxfiovZkwkvDku8UxTOuTjsRI8ciWiffn1ONWdmvFi8m8xtu/0S9t3mwjpyJ6LoF5iUdmd8Sl7+kn+B0aTkdaUAlyt/k/L/nPgT807+p/46V3lqJ3l+83kcxk/I7lEyP+Z63AiXkZY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=HxPzMMOA; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="HxPzMMOA" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49867p9b027160; Tue, 8 Oct 2024 12:54:42 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= pisCdr9NWnrRRgIMMBRCLbDY/8BeAAtZDiDWE+77Llw=; b=HxPzMMOA9PIEiQGD yxt44OVZ3Q52MYXon9nBgRFd2y+POg0pPjb0DULMYo4haIdKhw5x3K08eufr7qP5 aPZ3xR1MezlklnIWYc/JvFNheoSFSZLncQn7dqzxXLsm8f1O6P5VCjVRO7/S6o+L N1e4vjCqmzE3uc+lqHIzDYbvgpGyPcHgCu9Af4uHvKKLXAU31wBx9Mrjg0gYHg2b T0E0np6QNJZlpOYGgeP3IDuRIj+mt8Sw14VgMDVSgbNDA/j9t0OmZ9NbuEmxdVMZ jLRbdiAerNbNEU5UAW6wQcO4Emx0lsiuxeqSNaIr2OSeqBcLqdfFsbGZm3kmlB01 Qh2jbA== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 422xq9yfks-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 08 Oct 2024 12:54:41 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 498CsfbJ026101 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 8 Oct 2024 12:54:41 GMT Received: from hu-bibekkum-hyd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 8 Oct 2024 05:54:36 -0700 From: Bibek Kumar Patro To: , , , , , , , , , CC: , , , , , Konrad Dybcio Subject: [PATCH v16 1/5] iommu/arm-smmu: re-enable context caching in smmu reset operation Date: Tue, 8 Oct 2024 18:24:06 +0530 Message-ID: <20241008125410.3422512-2-quic_bibekkum@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241008125410.3422512-1-quic_bibekkum@quicinc.com> References: <20241008125410.3422512-1-quic_bibekkum@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: KG8vR4A51PftEv1Qe8NLIuDZBziR5qjH X-Proofpoint-GUID: KG8vR4A51PftEv1Qe8NLIuDZBziR5qjH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 phishscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 suspectscore=0 malwarescore=0 adultscore=0 mlxlogscore=999 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410080081 Content-Type: text/plain; charset="utf-8" Default MMU-500 reset operation disables context caching in prefetch buffer. It is however expected for context banks using the ACTLR register to retain their prefetch value during reset and runtime suspend. Replace default MMU-500 reset operation with Qualcomm specific reset operation which envelope the default reset operation and re-enables context caching in prefetch buffer for Qualcomm SoCs. Reviewed-by: Konrad Dybcio Signed-off-by: Bibek Kumar Patro Reviewed-by: Rob Clark --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 45 ++++++++++++++++++++-- 1 file changed, 42 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm= /arm-smmu/arm-smmu-qcom.c index 087fb4f6f4d3..0cb10b354802 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -16,6 +16,16 @@ #define QCOM_DUMMY_VAL -1 +/* + * SMMU-500 TRM defines BIT(0) as CMTLB (Enable context caching in the + * macro TLB) and BIT(1) as CPRE (Enable context caching in the prefetch + * buffer). The remaining bits are implementation defined and vary across + * SoCs. + */ + +#define CPRE (1 << 1) +#define CMTLB (1 << 0) + static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) { return container_of(smmu, struct qcom_smmu, smmu); @@ -396,11 +406,40 @@ static int qcom_smmu_def_domain_type(struct device *d= ev) return match ? IOMMU_DOMAIN_IDENTITY : 0; } +static int qcom_smmu500_reset(struct arm_smmu_device *smmu) +{ + int ret; + u32 val; + int i; + + ret =3D arm_mmu500_reset(smmu); + if (ret) + return ret; + + /* + * arm_mmu500_reset() disables CPRE which is re-enabled here. + * The errata for MMU-500 before the r2p2 revision requires CPRE to be + * disabled. The arm_mmu500_reset function disables CPRE to accommodate a= ll + * RTL revisions. Since all Qualcomm SoCs are on the r2p4 revision, where + * the CPRE bit can be enabled, the qcom_smmu500_reset function re-enables + * the CPRE bit for the next-page prefetcher to retain the prefetch value + * during reset and runtime suspend operations. + */ + + for (i =3D 0; i < smmu->num_context_banks; ++i) { + val =3D arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_ACTLR); + val |=3D CPRE; + arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_ACTLR, val); + } + + return 0; +} + static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu) { int ret; - arm_mmu500_reset(smmu); + qcom_smmu500_reset(smmu); /* * To address performance degradation in non-real time clients, @@ -427,7 +466,7 @@ static const struct arm_smmu_impl qcom_smmu_500_impl = =3D { .init_context =3D qcom_smmu_init_context, .cfg_probe =3D qcom_smmu_cfg_probe, .def_domain_type =3D qcom_smmu_def_domain_type, - .reset =3D arm_mmu500_reset, + .reset =3D qcom_smmu500_reset, .write_s2cr =3D qcom_smmu_write_s2cr, .tlb_sync =3D qcom_smmu_tlb_sync, #ifdef CONFIG_ARM_SMMU_QCOM_DEBUG @@ -461,7 +500,7 @@ static const struct arm_smmu_impl qcom_adreno_smmu_v2_i= mpl =3D { static const struct arm_smmu_impl qcom_adreno_smmu_500_impl =3D { .init_context =3D qcom_adreno_smmu_init_context, .def_domain_type =3D qcom_smmu_def_domain_type, - .reset =3D arm_mmu500_reset, + .reset =3D qcom_smmu500_reset, .alloc_context_bank =3D qcom_adreno_smmu_alloc_context_bank, .write_sctlr =3D qcom_adreno_smmu_write_sctlr, .tlb_sync =3D qcom_smmu_tlb_sync, -- 2.34.1