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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9CD.mail.protection.outlook.com (10.167.241.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8048.13 via Frontend Transport; Tue, 8 Oct 2024 10:42:45 +0000 Received: from BLR-L-DHSRIVAS.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 8 Oct 2024 05:42:41 -0500 From: Dheeraj Kumar Srivastava To: , , , , , , Subject: [PATCH 7/8] iommu/amd: Add debugfs support to dump IRT Table Date: Tue, 8 Oct 2024 16:10:34 +0530 Message-ID: <20241008104035.4008-8-dheerajkumar.srivastava@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241008104035.4008-1-dheerajkumar.srivastava@amd.com> References: <20241008104035.4008-1-dheerajkumar.srivastava@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CD:EE_|SJ2PR12MB8846:EE_ X-MS-Office365-Filtering-Correlation-Id: fb458b2e-67a1-4c9b-3075-08dce785f1e4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2024 10:42:45.3135 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fb458b2e-67a1-4c9b-3075-08dce785f1e4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8846 Content-Type: text/plain; charset="utf-8" In cases where we have an issue in the device interrupt path with IOMMU interrupt remapping enabled, dumping valid IRT table entries for the device is very useful and good input for debugging the issue. eg. To dump irte entries for a particular device #echo "c4:00.0" > /sys/kernel/debug/iommu/amd/devid #cat /sys/kernel/debug/iommu/amd/irqtbl | less or #echo "0000:c4:00.0" > /sys/kernel/debug/iommu/amd/devid #cat /sys/kernel/debug/iommu/amd/irqtbl | less Signed-off-by: Dheeraj Kumar Srivastava --- drivers/iommu/amd/debugfs.c | 89 +++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/drivers/iommu/amd/debugfs.c b/drivers/iommu/amd/debugfs.c index 61a541019432..c61daf921441 100644 --- a/drivers/iommu/amd/debugfs.c +++ b/drivers/iommu/amd/debugfs.c @@ -11,6 +11,7 @@ #include =20 #include "amd_iommu.h" +#include "../irq_remapping.h" =20 static struct dentry *amd_iommu_debugfs; =20 @@ -315,6 +316,92 @@ static int iommu_devtbl_show(struct seq_file *m, void = *unused) } DEFINE_SHOW_ATTRIBUTE(iommu_devtbl); =20 +static void dump_128_irte(struct seq_file *m, struct irq_remap_table *tabl= e) +{ + struct irte_ga *ptr, *irte; + int index; + + for (index =3D 0; index < MAX_IRQS_PER_TABLE; index++) { + ptr =3D (struct irte_ga *)table->table; + irte =3D &ptr[index]; + + if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) && + !irte->lo.fields_vapic.valid) + continue; + else if (!irte->lo.fields_remap.valid) + continue; + seq_printf(m, "IRT[%04d] %016llx%016llx\n", index, irte->hi.val, irte->l= o.val); + } +} + +static void dump_32_irte(struct seq_file *m, struct irq_remap_table *table) +{ + union irte *ptr, *irte; + int index; + + for (index =3D 0; index < MAX_IRQS_PER_TABLE; index++) { + ptr =3D (union irte *)table->table; + irte =3D &ptr[index]; + + if (!irte->fields.valid) + continue; + seq_printf(m, "IRT[%04d] %08x\n", index, irte->val); + } +} + +static void dump_irte(struct seq_file *m, u16 devid, struct amd_iommu_pci_= seg *pci_seg) +{ + struct irq_remap_table *table; + unsigned long flags; + + table =3D pci_seg->irq_lookup_table[devid]; + if (!table) { + seq_printf(m, "IRQ lookup table not set for %04x:%02x:%02x:%x\n", + pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid)); + return; + } + + seq_printf(m, "DeviceId %04x:%02x:%02x:%x\n", pci_seg->id, PCI_BUS_NUM(de= vid), + PCI_SLOT(devid), PCI_FUNC(devid)); + + raw_spin_lock_irqsave(&table->lock, flags); + if (AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) + dump_128_irte(m, table); + else + dump_32_irte(m, table); + seq_puts(m, "\n"); + raw_spin_unlock_irqrestore(&table->lock, flags); +} + +static int iommu_irqtbl_show(struct seq_file *m, void *unused) +{ + struct amd_iommu_pci_seg *pci_seg; + u16 devid, seg; + + if (!irq_remapping_enabled) { + seq_puts(m, "Interrupt remapping is disabled\n"); + return 0; + } + + if (sbdf < 0) { + seq_puts(m, "Please provide valid device id input\n"); + return 0; + } + + seg =3D PCI_SBDF_TO_SEGID(sbdf); + devid =3D PCI_SBDF_TO_DEVID(sbdf); + + for_each_pci_segment(pci_seg) { + if (pci_seg->id !=3D seg) + continue; + dump_irte(m, devid, pci_seg); + break; + } + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(iommu_irqtbl); + void amd_iommu_debugfs_setup(void) { struct amd_iommu *iommu; @@ -341,4 +428,6 @@ void amd_iommu_debugfs_setup(void) &devid_fops); debugfs_create_file("devtbl", 0444, amd_iommu_debugfs, NULL, &iommu_devtbl_fops); + debugfs_create_file("irqtbl", 0444, amd_iommu_debugfs, NULL, + &iommu_irqtbl_fops); } --=20 2.25.1