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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2024 10:41:11.1687 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f6c6c7f2-1c73-45f8-3392-08dce785b9c9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9440 Content-Type: text/plain; charset="utf-8" Rearrange initial setup of AMD IOMMU debugfs to segregate per IOMMU setup and setup which is common for all IOMMUs. This ensures that common debugfs paths (introduced in subsequent patches) are created only once instead of being created for each IOMMU. With the change, there is no need to use lock as amd_iommu_debugfs_setup() will be called only once during AMD IOMMU initialization. So remove lock acquisition in amd_iommu_debugfs_setup(). Signed-off-by: Dheeraj Kumar Srivastava Reviewed-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 4 ++-- drivers/iommu/amd/debugfs.c | 16 +++++++--------- drivers/iommu/amd/init.c | 5 ++--- 3 files changed, 11 insertions(+), 14 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 6386fa4556d9..68821b62730c 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -29,9 +29,9 @@ void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu, gfp_t gfp, size_t size); =20 #ifdef CONFIG_AMD_IOMMU_DEBUGFS -void amd_iommu_debugfs_setup(struct amd_iommu *iommu); +void amd_iommu_debugfs_setup(void); #else -static inline void amd_iommu_debugfs_setup(struct amd_iommu *iommu) {} +static inline void amd_iommu_debugfs_setup(void) {} #endif =20 /* Needed for interrupt remapping */ diff --git a/drivers/iommu/amd/debugfs.c b/drivers/iommu/amd/debugfs.c index 545372fcc72f..ff9520e002be 100644 --- a/drivers/iommu/amd/debugfs.c +++ b/drivers/iommu/amd/debugfs.c @@ -13,20 +13,18 @@ #include "amd_iommu.h" =20 static struct dentry *amd_iommu_debugfs; -static DEFINE_MUTEX(amd_iommu_debugfs_lock); =20 #define MAX_NAME_LEN 20 =20 -void amd_iommu_debugfs_setup(struct amd_iommu *iommu) +void amd_iommu_debugfs_setup(void) { + struct amd_iommu *iommu; char name[MAX_NAME_LEN + 1]; =20 - mutex_lock(&amd_iommu_debugfs_lock); - if (!amd_iommu_debugfs) - amd_iommu_debugfs =3D debugfs_create_dir("amd", - iommu_debugfs_dir); - mutex_unlock(&amd_iommu_debugfs_lock); + amd_iommu_debugfs =3D debugfs_create_dir("amd", iommu_debugfs_dir); =20 - snprintf(name, MAX_NAME_LEN, "iommu%02d", iommu->index); - iommu->debugfs =3D debugfs_create_dir(name, amd_iommu_debugfs); + for_each_iommu(iommu) { + snprintf(name, MAX_NAME_LEN, "iommu%02d", iommu->index); + iommu->debugfs =3D debugfs_create_dir(name, amd_iommu_debugfs); + } } diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 43131c3a2172..d78dc96bbec3 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -3377,7 +3377,6 @@ int amd_iommu_enable_faulting(unsigned int cpu) */ static int __init amd_iommu_init(void) { - struct amd_iommu *iommu; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2024 10:41:26.8127 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bbe4b891-da06-4645-b0f8-08dce785c31e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D0.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5761 Content-Type: text/plain; charset="utf-8" Analyzing IOMMU MMIO registers gives a view of what IOMMU is configured with on the system and is helpful to debug issues with IOMMU. eg. 1. To get mmio registers value for iommu # echo "0x18" > /sys/kernel/debug/iommu/amd/iommu00/mmio # cat /sys/kernel/debug/iommu/amd/iommu00/mmio_dump Signed-off-by: Dheeraj Kumar Srivastava --- drivers/iommu/amd/debugfs.c | 75 +++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/drivers/iommu/amd/debugfs.c b/drivers/iommu/amd/debugfs.c index ff9520e002be..30d6819e9a35 100644 --- a/drivers/iommu/amd/debugfs.c +++ b/drivers/iommu/amd/debugfs.c @@ -15,6 +15,76 @@ static struct dentry *amd_iommu_debugfs; =20 #define MAX_NAME_LEN 20 +#define OFS_IN_SZ 8 + +static int mmio_offset =3D -1; + +static ssize_t iommu_mmio_write(struct file *filp, const char __user *ubuf, + size_t cnt, loff_t *ppos) +{ + struct seq_file *m =3D filp->private_data; + struct amd_iommu *iommu =3D m->private; + char *mmio_ptr_ofs; + int ret =3D cnt; + + if (cnt > OFS_IN_SZ) { + ret =3D -EINVAL; + goto err; + } + + mmio_ptr_ofs =3D memdup_user_nul(ubuf, cnt); + if (IS_ERR(mmio_ptr_ofs)) { + ret =3D PTR_ERR(mmio_ptr_ofs); + goto err; + } + + if (kstrtou32(mmio_ptr_ofs, 0, &mmio_offset) < 0) { + ret =3D -EINVAL; + goto free; + } + + if (mmio_offset > iommu->mmio_phys_end - 4) { + ret =3D -EINVAL; + goto free; + } + + kfree(mmio_ptr_ofs); + *ppos +=3D cnt; + return ret; + +free: + kfree(mmio_ptr_ofs); +err: + mmio_offset =3D -1; + return ret; +} + +static int iommu_mmio_show(struct seq_file *m, void *unused) +{ + if (mmio_offset >=3D 0) + seq_printf(m, "0x%x\n", mmio_offset); + else + seq_puts(m, "No or invalid input provided\n"); + return 0; +} +DEFINE_SHOW_STORE_ATTRIBUTE(iommu_mmio); + +static int iommu_mmio_dump_show(struct seq_file *m, void *unused) +{ + struct amd_iommu *iommu =3D m->private; + u32 value; + + if (mmio_offset < 0) { + seq_puts(m, "Please provide mmio register's offset\n"); + return 0; + } + + value =3D readl(iommu->mmio_base + mmio_offset); + seq_printf(m, "0x%08x\n", value); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(iommu_mmio_dump); =20 void amd_iommu_debugfs_setup(void) { @@ -26,5 +96,10 @@ void amd_iommu_debugfs_setup(void) for_each_iommu(iommu) { snprintf(name, MAX_NAME_LEN, "iommu%02d", iommu->index); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2024 10:41:42.5061 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5894b049-956a-497a-4d77-08dce785cc79 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CE.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4461 Content-Type: text/plain; charset="utf-8" IOMMU Capability registers defines capabilities of IOMMU and information needed for initialising MMIO registers and device table. This is useful to dump these registers for debugging IOMMU related issues. e.g.To get capability registers value for iommu # echo "0x10" > /sys/kernel/debug/iommu/amd/iommu00/capability # cat /sys/kernel/debug/iommu/amd/iommu00/capability_dump Signed-off-by: Dheeraj Kumar Srivastava --- drivers/iommu/amd/debugfs.c | 77 +++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/drivers/iommu/amd/debugfs.c b/drivers/iommu/amd/debugfs.c index 30d6819e9a35..c3ef15e7b918 100644 --- a/drivers/iommu/amd/debugfs.c +++ b/drivers/iommu/amd/debugfs.c @@ -18,6 +18,7 @@ static struct dentry *amd_iommu_debugfs; #define OFS_IN_SZ 8 =20 static int mmio_offset =3D -1; +static int cap_offset =3D -1; =20 static ssize_t iommu_mmio_write(struct file *filp, const char __user *ubuf, size_t cnt, loff_t *ppos) @@ -86,6 +87,78 @@ static int iommu_mmio_dump_show(struct seq_file *m, void= *unused) } DEFINE_SHOW_ATTRIBUTE(iommu_mmio_dump); =20 +static ssize_t iommu_capability_write(struct file *filp, const char __user= *ubuf, + size_t cnt, loff_t *ppos) +{ + char *cap_ptr_ofs; + int ret =3D cnt; + + if (cnt > OFS_IN_SZ) { + ret =3D -EINVAL; + goto err; + } + + cap_ptr_ofs =3D memdup_user_nul(ubuf, cnt); + if (IS_ERR(cap_ptr_ofs)) { + ret =3D PTR_ERR(cap_ptr_ofs); + goto err; + } + + if (kstrtou32(cap_ptr_ofs, 0, &cap_offset) < 0) { + ret =3D -EINVAL; + goto free; + } + + /* Capability register at offset 0x14 is the last IOMMU capability regist= er. */ + if (cap_offset > 0x14) { + ret =3D -EINVAL; + goto free; + } + + kfree(cap_ptr_ofs); + *ppos +=3D cnt; + return ret; + +free: + kfree(cap_ptr_ofs); +err: + cap_offset =3D -1; + return ret; +} + +static int iommu_capability_show(struct seq_file *m, void *unused) +{ + if (cap_offset >=3D 0) + seq_printf(m, "0x%x\n", cap_offset); + else + seq_puts(m, "No or invalid input provided\n"); + return 0; +} +DEFINE_SHOW_STORE_ATTRIBUTE(iommu_capability); + +static int iommu_capability_dump_show(struct seq_file *m, void *unused) +{ + struct amd_iommu *iommu =3D m->private; + u32 value; + int err; + + if (cap_offset < 0) { + seq_puts(m, "Please provide capability register's offset\n"); + return 0; + } + + err =3D pci_read_config_dword(iommu->dev, iommu->cap_ptr + cap_offset, &v= alue); + if (err) { + seq_printf(m, "Not able to read capability register at 0x%x\n", cap_offs= et); + return 0; + } + + seq_printf(m, "0x%08x\n", value); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(iommu_capability_dump); + void amd_iommu_debugfs_setup(void) { struct amd_iommu *iommu; @@ -101,5 +174,9 @@ void amd_iommu_debugfs_setup(void) &iommu_mmio_fops); debugfs_create_file("mmio_dump", 0444, iommu->debugfs, iommu, &iommu_mmio_dump_fops); + debugfs_create_file("capability", 0644, iommu->debugfs, iommu, + &iommu_capability_fops); + debugfs_create_file("capability_dump", 0444, iommu->debugfs, + iommu, &iommu_capability_dump_fops); } } --=20 2.25.1 From nobody Wed Nov 27 19:44:18 2024 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2058.outbound.protection.outlook.com [40.107.93.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C11BC179953 for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2024 10:41:59.2698 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4ae8c16b-f579-408b-3ef4-08dce785d677 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D2.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5916 Content-Type: text/plain; charset="utf-8" IOMMU driver sends command to IOMMU hardware via command buffer. In cases where IOMMU hardware fails to process commands in command buffer, dumping it is a valuable input to debug the issue. IOMMU hardware processes command buffer entry at offset equals to the head pointer. Dumping just the entry at the head pointer may not always be useful. The current head may not be pointing to the entry of the command buffer which is causing the issue. IOMMU Hardware may have processed the entry and updated the head pointer. So dumping the entire command buffer gives a broad understanding of what hardware was/is doing. The command buffer dump will have all entries from start to end of the command buffer. Along with that, it will have a head and tail command buffer pointer register dump to facilitate where the IOMMU driver and hardware are in the command buffer for injecting and processing the entries respectively. Command buffer is a per IOMMU data structure. So dumping on per IOMMU basis. eg. To get command buffer dump for iommu #cat /sys/kernel/debug/iommu/amd/iommu/cmdbuf Signed-off-by: Dheeraj Kumar Srivastava --- drivers/iommu/amd/amd_iommu_types.h | 7 +++++++ drivers/iommu/amd/debugfs.c | 27 +++++++++++++++++++++++++++ drivers/iommu/amd/iommu.c | 7 ------- 3 files changed, 34 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 601fb4ee6900..876fa671ef91 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -878,6 +878,13 @@ extern struct list_head amd_iommu_list; */ extern struct amd_iommu *amd_iommus[MAX_IOMMUS]; =20 +/* + * Structure defining one entry in the command buffer + */ +struct iommu_cmd { + u32 data[4]; +}; + /* * Structure defining one entry in the device table */ diff --git a/drivers/iommu/amd/debugfs.c b/drivers/iommu/amd/debugfs.c index c3ef15e7b918..69d2b01bc0e4 100644 --- a/drivers/iommu/amd/debugfs.c +++ b/drivers/iommu/amd/debugfs.c @@ -159,6 +159,31 @@ static int iommu_capability_dump_show(struct seq_file = *m, void *unused) } DEFINE_SHOW_ATTRIBUTE(iommu_capability_dump); =20 +static int iommu_cmdbuf_show(struct seq_file *m, void *unused) +{ + struct amd_iommu *iommu =3D m->private; + struct iommu_cmd *cmd; + unsigned long flag; + u32 head, tail; + int i; + + raw_spin_lock_irqsave(&iommu->lock, flag); + + head =3D readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); + tail =3D readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); + seq_printf(m, "CMD Buffer Head pointer register:0x%08x Tail pointer regis= ter:0x%08x\n", + head, tail); + for (i =3D 0; i < CMD_BUFFER_ENTRIES; i++) { + cmd =3D (struct iommu_cmd *)(iommu->cmd_buf + i * sizeof(*cmd)); + seq_printf(m, "%3d: %08x%08x%08x%08x\n", i, cmd->data[0], + cmd->data[1], cmd->data[2], cmd->data[3]); + } + raw_spin_unlock_irqrestore(&iommu->lock, flag); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(iommu_cmdbuf); + void amd_iommu_debugfs_setup(void) { struct amd_iommu *iommu; @@ -178,5 +203,7 @@ void amd_iommu_debugfs_setup(void) &iommu_capability_fops); debugfs_create_file("capability_dump", 0444, iommu->debugfs, iommu, &iommu_capability_dump_fops); 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Tue, 8 Oct 2024 05:42:10 -0500 From: Dheeraj Kumar Srivastava To: , , , , , , Subject: [PATCH 5/8] iommu/amd: Add support for device id user input Date: Tue, 8 Oct 2024 16:10:32 +0530 Message-ID: <20241008104035.4008-6-dheerajkumar.srivastava@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241008104035.4008-1-dheerajkumar.srivastava@amd.com> References: <20241008104035.4008-1-dheerajkumar.srivastava@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CE:EE_|LV8PR12MB9408:EE_ X-MS-Office365-Filtering-Correlation-Id: 200132de-ae45-48bd-8d7d-08dce785def3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2024 10:42:13.5062 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 200132de-ae45-48bd-8d7d-08dce785def3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CE.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9408 Content-Type: text/plain; charset="utf-8" Device id user input is needed for dumping IOMMU data structures like device table, IRT etc in AMD IOMMU debugfs. eg. 1. # echo 0000:01:00.0 > /sys/kernel/debug/iommu/amd/devid # cat /sys/kernel/debug/iommu/amd/devid Output : 0000:01:00.0 2. # echo 01:00.0 > /sys/kernel/debug/iommu/amd/devid # cat /sys/kernel/debug/iommu/amd/devid Output : 0000:01:00.0 Signed-off-by: Dheeraj Kumar Srivastava --- drivers/iommu/amd/debugfs.c | 86 +++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/drivers/iommu/amd/debugfs.c b/drivers/iommu/amd/debugfs.c index 69d2b01bc0e4..0d11250c1a00 100644 --- a/drivers/iommu/amd/debugfs.c +++ b/drivers/iommu/amd/debugfs.c @@ -16,9 +16,11 @@ static struct dentry *amd_iommu_debugfs; =20 #define MAX_NAME_LEN 20 #define OFS_IN_SZ 8 +#define DEVID_IN_SZ 16 =20 static int mmio_offset =3D -1; static int cap_offset =3D -1; +static int sbdf =3D -1; =20 static ssize_t iommu_mmio_write(struct file *filp, const char __user *ubuf, size_t cnt, loff_t *ppos) @@ -184,6 +186,88 @@ static int iommu_cmdbuf_show(struct seq_file *m, void = *unused) } DEFINE_SHOW_ATTRIBUTE(iommu_cmdbuf); =20 +static ssize_t devid_write(struct file *filp, const char __user *ubuf, + size_t cnt, loff_t *ppos) +{ + struct amd_iommu_pci_seg *pci_seg; + int seg, bus, slot, func; + struct amd_iommu *iommu; + char *srcid_ptr; + int i, ret =3D cnt; + u16 devid; + + if (cnt >=3D DEVID_IN_SZ) { + ret =3D -EINVAL; + goto err; + } + + srcid_ptr =3D memdup_user_nul(ubuf, cnt); + if (IS_ERR(srcid_ptr)) { + ret =3D PTR_ERR(srcid_ptr); + goto err; + } + + i =3D sscanf(srcid_ptr, "%x:%x:%x.%x", &seg, &bus, &slot, &func); + if (i !=3D 4) { + i =3D sscanf(srcid_ptr, "%x:%x.%x", &bus, &slot, &func); + if (i !=3D 3) { + ret =3D -EINVAL; + goto free; + } + seg =3D 0; + } + + devid =3D PCI_DEVID(bus, PCI_DEVFN(slot, func)); + + /* Check if user device id input is a valid input */ + for_each_pci_segment(pci_seg) { + if (pci_seg->id !=3D seg) + continue; + if (devid > pci_seg->last_bdf) { + ret =3D -EINVAL; + goto free; + } + iommu =3D pci_seg->rlookup_table[devid]; + if (!iommu) { + ret =3D -ENODEV; + goto free; + } + break; + } + + if (pci_seg->id !=3D seg) { + ret =3D -EINVAL; + goto free; + } + + sbdf =3D PCI_SEG_DEVID_TO_SBDF(seg, devid); + + kfree(srcid_ptr); + *ppos +=3D cnt; + return ret; + +free: + kfree(srcid_ptr); +err: + sbdf =3D -1; + return ret; +} + +static int devid_show(struct seq_file *m, void *unused) +{ + u16 devid; + + if (sbdf >=3D 0) { + devid =3D PCI_SBDF_TO_DEVID(sbdf); + seq_printf(m, "%04x:%02x:%02x:%x\n", PCI_SBDF_TO_SEGID(sbdf), + PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid)); + } else + seq_puts(m, "No or Invalid input provided\n"); + + return 0; +} +DEFINE_SHOW_STORE_ATTRIBUTE(devid); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2024 10:42:29.5439 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 10b3f7c1-4f62-434b-5319-08dce785e880 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7874 Content-Type: text/plain; charset="utf-8" IOMMU uses device table data structure to get per-device information for DMA remapping, interrupt remapping, and other functionalities. It's a valuable data structure to visualize for debugging issues related to IOMMU. eg. To dump device table entry for a particular device #echo 0000:c4:00.0 > /sys/kernel/debug/iommu/amd/devid #cat /sys/kernel/debug/iommu/amd/devtbl or #echo c4:00.0 > /sys/kernel/debug/iommu/amd/devid #cat /sys/kernel/debug/iommu/amd/devtbl Signed-off-by: Dheeraj Kumar Srivastava --- drivers/iommu/amd/debugfs.c | 49 +++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/iommu/amd/debugfs.c b/drivers/iommu/amd/debugfs.c index 0d11250c1a00..61a541019432 100644 --- a/drivers/iommu/amd/debugfs.c +++ b/drivers/iommu/amd/debugfs.c @@ -268,6 +268,53 @@ static int devid_show(struct seq_file *m, void *unused) } DEFINE_SHOW_STORE_ATTRIBUTE(devid); =20 +static void dump_dte(struct seq_file *m, struct amd_iommu_pci_seg *pci_seg= , u16 devid) +{ + struct dev_table_entry *dev_table; + struct amd_iommu *iommu; + + iommu =3D pci_seg->rlookup_table[devid]; + if (!iommu) + return; + + dev_table =3D get_dev_table(iommu); + if (!dev_table) { + seq_puts(m, "Device table not found"); + return; + } + + seq_printf(m, "%-12s %16s %16s %16s %16s iommu\n", "DeviceId", + "QWORD[3]", "QWORD[2]", "QWORD[1]", "QWORD[0]"); + seq_printf(m, "%04x:%02x:%02x:%x ", pci_seg->id, PCI_BUS_NUM(devid), + PCI_SLOT(devid), PCI_FUNC(devid)); + for (int i =3D 3; i >=3D 0; --i) + seq_printf(m, "%016llx ", dev_table[devid].data[i]); + seq_printf(m, "iommu%d\n", iommu->index); +} + +static int iommu_devtbl_show(struct seq_file *m, void *unused) +{ + struct amd_iommu_pci_seg *pci_seg; + u16 seg, devid; + + if (sbdf < 0) { + seq_puts(m, "Please provide valid device id input\n"); + return 0; + } + seg =3D PCI_SBDF_TO_SEGID(sbdf); + devid =3D PCI_SBDF_TO_DEVID(sbdf); + + for_each_pci_segment(pci_seg) { + if (pci_seg->id !=3D seg) + continue; + dump_dte(m, pci_seg, devid); + break; + } + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(iommu_devtbl); + void amd_iommu_debugfs_setup(void) { struct amd_iommu *iommu; @@ -292,4 +339,6 @@ void amd_iommu_debugfs_setup(void) } debugfs_create_file("devid", 0644, amd_iommu_debugfs, NULL, &devid_fops); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2024 10:42:45.3135 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fb458b2e-67a1-4c9b-3075-08dce785f1e4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8846 Content-Type: text/plain; charset="utf-8" In cases where we have an issue in the device interrupt path with IOMMU interrupt remapping enabled, dumping valid IRT table entries for the device is very useful and good input for debugging the issue. eg. To dump irte entries for a particular device #echo "c4:00.0" > /sys/kernel/debug/iommu/amd/devid #cat /sys/kernel/debug/iommu/amd/irqtbl | less or #echo "0000:c4:00.0" > /sys/kernel/debug/iommu/amd/devid #cat /sys/kernel/debug/iommu/amd/irqtbl | less Signed-off-by: Dheeraj Kumar Srivastava --- drivers/iommu/amd/debugfs.c | 89 +++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/drivers/iommu/amd/debugfs.c b/drivers/iommu/amd/debugfs.c index 61a541019432..c61daf921441 100644 --- a/drivers/iommu/amd/debugfs.c +++ b/drivers/iommu/amd/debugfs.c @@ -11,6 +11,7 @@ #include =20 #include "amd_iommu.h" +#include "../irq_remapping.h" =20 static struct dentry *amd_iommu_debugfs; =20 @@ -315,6 +316,92 @@ static int iommu_devtbl_show(struct seq_file *m, void = *unused) } DEFINE_SHOW_ATTRIBUTE(iommu_devtbl); =20 +static void dump_128_irte(struct seq_file *m, struct irq_remap_table *tabl= e) +{ + struct irte_ga *ptr, *irte; + int index; + + for (index =3D 0; index < MAX_IRQS_PER_TABLE; index++) { + ptr =3D (struct irte_ga *)table->table; + irte =3D &ptr[index]; + + if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) && + !irte->lo.fields_vapic.valid) + continue; + else if (!irte->lo.fields_remap.valid) + continue; + seq_printf(m, "IRT[%04d] %016llx%016llx\n", index, irte->hi.val, irte->l= o.val); + } +} + +static void dump_32_irte(struct seq_file *m, struct irq_remap_table *table) +{ + union irte *ptr, *irte; + int index; + + for (index =3D 0; index < MAX_IRQS_PER_TABLE; index++) { + ptr =3D (union irte *)table->table; + irte =3D &ptr[index]; + + if (!irte->fields.valid) + continue; + seq_printf(m, "IRT[%04d] %08x\n", index, irte->val); + } +} + +static void dump_irte(struct seq_file *m, u16 devid, struct amd_iommu_pci_= seg *pci_seg) +{ + struct irq_remap_table *table; + unsigned long flags; + + table =3D pci_seg->irq_lookup_table[devid]; + if (!table) { + seq_printf(m, "IRQ lookup table not set for %04x:%02x:%02x:%x\n", + pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid)); + return; + } + + seq_printf(m, "DeviceId %04x:%02x:%02x:%x\n", pci_seg->id, PCI_BUS_NUM(de= vid), + PCI_SLOT(devid), PCI_FUNC(devid)); + + raw_spin_lock_irqsave(&table->lock, flags); + if (AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) + dump_128_irte(m, table); + else + dump_32_irte(m, table); + seq_puts(m, "\n"); + raw_spin_unlock_irqrestore(&table->lock, flags); +} + +static int iommu_irqtbl_show(struct seq_file *m, void *unused) +{ + struct amd_iommu_pci_seg *pci_seg; + u16 devid, seg; + + if (!irq_remapping_enabled) { + seq_puts(m, "Interrupt remapping is disabled\n"); + return 0; + } + + if (sbdf < 0) { + seq_puts(m, "Please provide valid device id input\n"); + return 0; + } + + seg =3D PCI_SBDF_TO_SEGID(sbdf); + devid =3D PCI_SBDF_TO_DEVID(sbdf); + + for_each_pci_segment(pci_seg) { + if (pci_seg->id !=3D seg) + continue; + dump_irte(m, devid, pci_seg); + break; + } + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(iommu_irqtbl); + void amd_iommu_debugfs_setup(void) { struct amd_iommu *iommu; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2024 10:43:00.8482 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bcde736c-4a9f-46c5-f996-08dce785fb28 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D2.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6076 Content-Type: text/plain; charset="utf-8" Add documentation describing how to use AMD IOMMU debugfs support to dump IOMMU data structures - IRT table, Device table, Registers (MMIO and Capability) and command buffer. Signed-off-by: Dheeraj Kumar Srivastava --- Documentation/ABI/testing/debugfs-amd-iommu | 140 ++++++++++++++++++++ 1 file changed, 140 insertions(+) create mode 100644 Documentation/ABI/testing/debugfs-amd-iommu diff --git a/Documentation/ABI/testing/debugfs-amd-iommu b/Documentation/AB= I/testing/debugfs-amd-iommu new file mode 100644 index 000000000000..7acdb38bdf7b --- /dev/null +++ b/Documentation/ABI/testing/debugfs-amd-iommu @@ -0,0 +1,140 @@ +What: /sys/kernel/debug/iommu/amd/iommu/mmio +Date: September 2024 +Contact: Dheeraj Kumar Srivastava +Description: + This is an input read/write access file. In this file, the user input + mmio register offset for iommu to print corresponding mmio register + of iommu. + + Example: + $ echo "0x18" > /sys/kernel/debug/iommu/amd/iommu00/mmio + $ cat /sys/kernel/debug/iommu/amd/iommu00/mmio + + Output: + 0x18 + +What: /sys/kernel/debug/iommu/amd/iommu/mmio_dump +Date: September 2024 +Contact: Dheeraj Kumar Srivastava +Description: + This is an output read only file that contains mmio register + value at offset "/sys/kernel/debug/iommu/amd/iommu/mmio". + + Example: + $ cat /sys/kernel/debug/iommu/amd/iommu00/mmio_dump + + Output: + 0x0003f48d + +What: /sys/kernel/debug/iommu/amd/iommu/capability +Date: September 2024 +Contact: Dheeraj Kumar Srivastava +Description: + This is an input read/write access file. In this file, the user input + capability register offset for iommu to print correspon= ding capability + register of iommu. + + Example: + $ echo "0x10" > /sys/kernel/debug/iommu/amd/iommu00/capability + $ cat /sys/kernel/debug/iommu/amd/iommu00/capability + + Output: + 0x10 + +What: /sys/kernel/debug/iommu/amd/iommu/capability_dump +Date: September 2024 +Contact: Dheeraj Kumar Srivastava +Description: + This is an output read only file that contains capability register + value at offset "/sys/kernel/debug/iommu/amd/iommu/capa= bility". + + Example: + $ cat /sys/kernel/debug/iommu/amd/iommu00/capability_dump + + Output: + 0x00203040 + +What: /sys/kernel/debug/iommu/amd/iommu/cmdbuf +Date: September 2024 +Contact: Dheeraj Kumar Srivastava +Description: + This file is an output read only file that contains iommu command + buffer entries. + + Examples: + $ cat /sys/kernel/debug/iommu/amd/iommu/cmdbuf + + Output: + CMD Buffer Head pointer register:0x00000b90 Tail pointer register:0x0000= 0b90 + 0: 008350011000000100003c0000000000 + 1: 0000000030000005fffff0037fffffff + 2: 008350011000000100003c0100000000 + 3: 0000000030000005fffff0037fffffff + 4: 008350011000000100003c0200000000 + 5: 0000000030000005fffff0037fffffff + 6: 008350011000000100003c0300000000 + 7: 0000000030000005fffff0037fffffff + 8: 008350011000000100003c0400000000 + 9: 0000000030000005fffff0037fffffff + 10: 008350011000000100003c0500000000 + 11: 0000000030000005fffff0037fffffff + [...] + +What: /sys/kernel/debug/iommu/amd/devid +Date: September 2024 +Contact: Dheeraj Kumar Srivastava +Description: + This is an input read/write file that takes device id user input. + This input can be used for dumping iommu data structures like + interrupt remapping table, device table etc. + + Example: + 1. + $ echo 0000:01:00.0 > /sys/kernel/debug/iommu/amd/devid + $ cat /sys/kernel/debug/iommu/amd/devid + + Output: + 0000:01:00.0 + + 2. + $ echo 01:00.0 > /sys/kernel/debug/iommu/amd/devid + $ cat /sys/kernel/debug/iommu/amd/devid + + Output: + 0000:01:00.0 + +What: /sys/kernel/debug/iommu/devtbl +Date: September 2024 +Contact: Dheeraj Kumar Srivastava +Description: + This is an output read only file that contains device table entry for + the device id input given in /sys/kernel/debug/iommu/amd/devid. + + Example: + $ cat /sys/kernel/debug/iommu/amd/devtbl + + Output: + DeviceId QWORD[3] QWORD[2] QWORD[1] = QWORD[0] iommu + 0000:01:00.0 0000000000000000 20000001373b8013 0000000000000038 60000001= 14d7b603 iommu3 + +What: /sys/kernel/debug/iommu/devtbl +Date: September 2024 +Contact: Dheeraj Kumar Srivastava +Description: + This is an output read only file that contains IRT table valid entries + for the device id input given in /sys/kernel/debug/iommu/amd/devid. + + Example: + $ cat /sys/kernel/debug/iommu/amd/irqtbl + + Output: + DeviceId 0000:01:00.0 + IRT[0000] 00000000000000200000000000000241 + IRT[0001] 00000000000000200000000000000841 + IRT[0002] 00000000000000200000000000002041 + IRT[0003] 00000000000000200000000000008041 + IRT[0004] 00000000000000200000000000020041 + IRT[0005] 00000000000000200000000000080041 + IRT[0006] 00000000000000200000000000200041 + IRT[0007] 00000000000000200000000000800041 + [...] --=20 2.25.1