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[173.79.56.208]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6cbc78650efsm698396d6.39.2024.10.08.07.00.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 07:00:48 -0700 (PDT) From: Gregory Price To: linux-cxl@vger.kernel.org, x86@kernel.org, linux-mm@kvack.org, linux-acpi@vger.kernel.org Cc: linux-kernel@vger.kernel.org, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, david@redhat.com, osalvador@suse.de, gregkh@linuxfoundation.org, rafael@kernel.org, akpm@linux-foundation.org, dan.j.williams@intel.com, Jonathan.Cameron@Huawei.com, alison.schofield@intel.com, rrichter@amd.com, terry.bowman@amd.com, lenb@kernel.org, dave.jiang@intel.com, ira.weiny@intel.com Subject: [PATCH 1/3] memory: extern memory_block_size_bytes and set_memory_block_size_order Date: Tue, 8 Oct 2024 00:43:53 -0400 Message-ID: <20241008044355.4325-2-gourry@gourry.net> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241008044355.4325-1-gourry@gourry.net> References: <20241008044355.4325-1-gourry@gourry.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On CXL systems, block alignment may be as small as 256MB, which may require a resize of the block size during initialization. This is done in the ACPI driver, so the resize function need to be made available. Presently, only x86 provides the functionality to resize memory block sizes. Wire up a weak stub for set_memory_block_size_order, similar to memory_block_size_bytes, that simply returns -ENODEV. Since set_memory_block_size_order is now extern, we also need to drop the __init macro. Signed-off-by: Gregory Price Suggested-by: Dan Williams --- arch/x86/mm/init_64.c | 2 +- drivers/base/memory.c | 6 ++++++ include/linux/memory.h | 4 ++-- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c index ff253648706f..6086f99449fa 100644 --- a/arch/x86/mm/init_64.c +++ b/arch/x86/mm/init_64.c @@ -1424,7 +1424,7 @@ void mark_rodata_ro(void) =20 /* Adjustable memory block size */ static unsigned long set_memory_block_size; -int __init set_memory_block_size_order(unsigned int order) +int set_memory_block_size_order(unsigned int order) { unsigned long size =3D 1UL << order; =20 diff --git a/drivers/base/memory.c b/drivers/base/memory.c index 67858eeb92ed..f9045642f69e 100644 --- a/drivers/base/memory.c +++ b/drivers/base/memory.c @@ -110,6 +110,12 @@ static void memory_block_release(struct device *dev) kfree(mem); } =20 +int __weak set_memory_block_size_order(unsigned int order) +{ + return -ENODEV; +} +EXPORT_SYMBOL_GPL(set_memory_block_size_order); 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[173.79.56.208]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6cbc78650efsm698396d6.39.2024.10.08.07.00.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 07:00:50 -0700 (PDT) From: Gregory Price To: linux-cxl@vger.kernel.org, x86@kernel.org, linux-mm@kvack.org, linux-acpi@vger.kernel.org Cc: linux-kernel@vger.kernel.org, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, david@redhat.com, osalvador@suse.de, gregkh@linuxfoundation.org, rafael@kernel.org, akpm@linux-foundation.org, dan.j.williams@intel.com, Jonathan.Cameron@Huawei.com, alison.schofield@intel.com, rrichter@amd.com, terry.bowman@amd.com, lenb@kernel.org, dave.jiang@intel.com, ira.weiny@intel.com Subject: [PATCH 2/3] x86/mm: if memblock size is adjusted, update the cached value Date: Tue, 8 Oct 2024 00:43:54 -0400 Message-ID: <20241008044355.4325-3-gourry@gourry.net> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241008044355.4325-1-gourry@gourry.net> References: <20241008044355.4325-1-gourry@gourry.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When parsing CFMWS, we need to know the currently registered memory block size to avoid accidentally adjusting the size upward. Querying the size causes it to be cached in a static global. Update the static global if the value is subsequently updated. Print a warning that this has occurred for debugging purposes if the memory block size is changed at an unexpected time (post-init). Signed-off-by: Gregory Price Suggested-by: Dan Williams --- arch/x86/mm/init_64.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c index 6086f99449fa..733dfa899232 100644 --- a/arch/x86/mm/init_64.c +++ b/arch/x86/mm/init_64.c @@ -1424,6 +1424,7 @@ void mark_rodata_ro(void) =20 /* Adjustable memory block size */ static unsigned long set_memory_block_size; +static unsigned long memory_block_size_probed; int set_memory_block_size_order(unsigned int order) { unsigned long size =3D 1UL << order; @@ -1432,6 +1433,19 @@ int set_memory_block_size_order(unsigned int order) return -EINVAL; =20 set_memory_block_size =3D size; + + /* + * If the block size has already been probed, we need to change it. + * This can happen during ACPI/CFMWS parsing, since it needs to + * probe the system for the existing block size to avoid increasing + * the block size if lower memory happens to be misaligned + */ + if (memory_block_size_probed) { + memory_block_size_probed =3D size; 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[173.79.56.208]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6cbc78650efsm698396d6.39.2024.10.08.07.00.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 07:00:53 -0700 (PDT) From: Gregory Price To: linux-cxl@vger.kernel.org, x86@kernel.org, linux-mm@kvack.org, linux-acpi@vger.kernel.org Cc: linux-kernel@vger.kernel.org, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, david@redhat.com, osalvador@suse.de, gregkh@linuxfoundation.org, rafael@kernel.org, akpm@linux-foundation.org, dan.j.williams@intel.com, Jonathan.Cameron@Huawei.com, alison.schofield@intel.com, rrichter@amd.com, terry.bowman@amd.com, lenb@kernel.org, dave.jiang@intel.com, ira.weiny@intel.com Subject: [PATCH 3/3] acpi,srat: reduce memory block size if CFMWS has a smaller alignment Date: Tue, 8 Oct 2024 00:43:55 -0400 Message-ID: <20241008044355.4325-4-gourry@gourry.net> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241008044355.4325-1-gourry@gourry.net> References: <20241008044355.4325-1-gourry@gourry.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The CXL Fixed Memory Window allows for memory aligned down to the size of 256MB. However, by default on x86, memory blocks increase in size as total System RAM capacity increases. On x86, this caps out at 2G when 64GB of System RAM is reached. When the CFMWS regions are not aligned to memory block size, this results in lost capacity on either side of the alignment. Parse all CFMWS to detect the largest common denomenator among all regions, and reduce the block size accordingly. This can only be done when MEMORY_HOTPLUG and SPARSEMEM configs are enabled, but the surrounding code may not necessarily require these configs, so build accordingly. Suggested-by: Dan Williams Signed-off-by: Gregory Price --- drivers/acpi/numa/srat.c | 48 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/drivers/acpi/numa/srat.c b/drivers/acpi/numa/srat.c index 44f91f2c6c5d..9367d36eba9a 100644 --- a/drivers/acpi/numa/srat.c +++ b/drivers/acpi/numa/srat.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -333,6 +334,37 @@ acpi_parse_memory_affinity(union acpi_subtable_headers= *header, return 0; } =20 +#if defined(CONFIG_MEMORY_HOTPLUG) +/* + * CXL allows CFMW to be aligned along 256MB boundaries, but large memory + * systems default to larger alignments (2GB on x86). Misalignments can + * cause some capacity to become unreachable. Calculate the largest suppor= ted + * alignment for all CFMW to maximize the amount of mappable capacity. + */ +static int __init acpi_align_cfmws(union acpi_subtable_headers *header, + void *arg, const unsigned long table_end) +{ + struct acpi_cedt_cfmws *cfmws =3D (struct acpi_cedt_cfmws *)header; + u64 start =3D cfmws->base_hpa; + u64 size =3D cfmws->window_size; + unsigned long *fin_bz =3D arg; + unsigned long bz; + + for (bz =3D SZ_64T; bz >=3D SZ_256M; bz >>=3D 1) { + if (IS_ALIGNED(start, bz) && IS_ALIGNED(size, bz)) + break; + } + + /* Only adjust downward, we never want to increase block size */ + if (bz < *fin_bz && bz >=3D SZ_256M) + *fin_bz =3D bz; + else if (bz < SZ_256M) + pr_err("CFMWS: [BIOS BUG] base/size alignment violates spec\n"); + + return 0; +} +#endif /* defined(CONFIG_MEMORY_HOTPLUG) */ + static int __init acpi_parse_cfmws(union acpi_subtable_headers *header, void *arg, const unsigned long table_end) { @@ -501,6 +533,10 @@ acpi_table_parse_srat(enum acpi_srat_type id, int __init acpi_numa_init(void) { int i, fake_pxm, cnt =3D 0; +#if defined(CONFIG_MEMORY_HOTPLUG) + unsigned long block_sz =3D memory_block_size_bytes(); + unsigned long cfmw_align =3D block_sz; +#endif /* defined(CONFIG_MEMORY_HOTPLUG) */ =20 if (acpi_disabled) return -EINVAL; @@ -552,6 +588,18 @@ int __init acpi_numa_init(void) } last_real_pxm =3D fake_pxm; fake_pxm++; + +#if defined(CONFIG_MEMORY_HOTPLUG) + /* Calculate and set largest supported memory block size alignment */ + acpi_table_parse_cedt(ACPI_CEDT_TYPE_CFMWS, acpi_align_cfmws, + &cfmw_align); + if (cfmw_align < block_sz && cfmw_align >=3D SZ_256M) { + if (set_memory_block_size_order(ffs(cfmw_align)-1)) + pr_warn("CFMWS: Unable to adjust memory block size\n"); + } +#endif /* defined(CONFIG_MEMORY_HOTPLUG) */ + + /* Then parse and fill the numa nodes with the described memory */ acpi_table_parse_cedt(ACPI_CEDT_TYPE_CFMWS, acpi_parse_cfmws, &fake_pxm); =20 --=20 2.43.0