From nobody Wed Nov 27 23:42:28 2024 Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E0BE34206D; Tue, 8 Oct 2024 02:30:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.190 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728354636; cv=none; b=d9XYyCE88V4sS0d0ypAsazt58uIL764/VBjZMnsX87nYUUvW1vguyHqCzoNkgkEbdayOjRKyzfQrZ+jKNtKBlhb7Sz4qgb+PNU04KmAdw3Kqw+VVqGbf0ZjzEOSY2FY5qYWw1qPSuPmeAk8QVbsMispAW/PaMAorab/peVwa9i0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728354636; c=relaxed/simple; bh=79wlIqZIq5IpMVRuOdgv8TlKhw8yP9i2Zk09NUR6QdA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=UFAOqH+mi2LWN1TjxAxYc8XZCjyYn+YklvgNhXaa6X0ZoFX74KZvcTslduH1wRGHaL91D46l9ITJiLl0XDLX8+lFIpPyCFw69mqx/AUvo2hLvM0pm2AdA/kUXc59fVs3azjgefImWbz9s7bXbqMDmO+0GdSWB178JvKDwde1D8c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.190 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.163.17]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4XN0NL3JZnz20q0X; Tue, 8 Oct 2024 10:29:54 +0800 (CST) Received: from kwepemm000007.china.huawei.com (unknown [7.193.23.189]) by mail.maildlp.com (Postfix) with ESMTPS id 847731A0188; Tue, 8 Oct 2024 10:30:29 +0800 (CST) Received: from localhost.localdomain (10.90.30.45) by kwepemm000007.china.huawei.com (7.193.23.189) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 8 Oct 2024 10:30:28 +0800 From: Jijie Shao To: , , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH V11 net-next 06/10] net: hibmcge: Implement .ndo_start_xmit function Date: Tue, 8 Oct 2024 10:23:54 +0800 Message-ID: <20241008022358.863393-7-shaojijie@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20241008022358.863393-1-shaojijie@huawei.com> References: <20241008022358.863393-1-shaojijie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To kwepemm000007.china.huawei.com (7.193.23.189) Content-Type: text/plain; charset="utf-8" Implement .ndo_start_xmit function to fill the information of the packet to be transmitted into the tx descriptor, and then the hardware will transmit the packet using the information in the tx descriptor. In addition, we also implemented the tx_handler function to enable the tx descriptor to be reused, and .ndo_tx_timeout function to print some information when the hardware is busy. Signed-off-by: Jijie Shao --- ChangeLog: v10 -> v11: - Remove unnecessary declares for struct, suggested by Jakub. - fix budget to 128 in TX napi.poll(), suggested by Jakub. - Not call napi_complete_done() if packet_done >=3D budget in napi.poll(), suggested by Jakub. - Use devm_kmalloc() instead of devm_kzalloc() for tx_ring->tout_log_buf, suggested by Christophe JAILLET. v10: https://lore.kernel.org/all/20240912025127.3912972-1-shaojijie@huawe= i.com/ =20 v8 -> v9: - Remove hbg_nic_is_open() judgment from ndo.xmit() v8: https://lore.kernel.org/all/20240909023141.3234567-1-shaojijie@huawei= .com/ v6 -> v7: - Add check for netif_txq_maybe_stop(), suggested by Paolo. - Use dev_sw_netstats_tx_add() instead of dev->stats, suggested by Paolo. v6: https://lore.kernel.org/all/20240830121604.2250904-7-shaojijie@huawei= .com/ v5 -> v6: - Remove hbg_txrx_init() from probe path, alloc ring buffer in .ndo_open(= ), and release ring buffer in .ndo_stop(), suggested by Jakub and Andrew. v5: https://lore.kernel.org/all/20240827131455.2919051-1-shaojijie@huawei= .com/ v4 -> v5: - Delete unnecessary semicolon, suggested by Jakub. v4: https://lore.kernel.org/all/20240826081258.1881385-1-shaojijie@huawei= .com/ RFC v1 -> RFC v2: - Use napi_complete_done() to simplify the process, suggested by Joe Dama= to. RFC v1: https://lore.kernel.org/all/20240731094245.1967834-1-shaojijie@hu= awei.com/ --- .../ethernet/hisilicon/hibmcge/hbg_common.h | 48 ++++ .../net/ethernet/hisilicon/hibmcge/hbg_hw.c | 18 ++ .../net/ethernet/hisilicon/hibmcge/hbg_hw.h | 2 + .../net/ethernet/hisilicon/hibmcge/hbg_irq.c | 8 +- .../net/ethernet/hisilicon/hibmcge/hbg_main.c | 54 +++- .../net/ethernet/hisilicon/hibmcge/hbg_reg.h | 19 ++ .../net/ethernet/hisilicon/hibmcge/hbg_txrx.c | 267 ++++++++++++++++++ .../net/ethernet/hisilicon/hibmcge/hbg_txrx.h | 37 +++ 8 files changed, 450 insertions(+), 3 deletions(-) create mode 100644 drivers/net/ethernet/hisilicon/hibmcge/hbg_txrx.c create mode 100644 drivers/net/ethernet/hisilicon/hibmcge/hbg_txrx.h diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_common.h b/drivers/= net/ethernet/hisilicon/hibmcge/hbg_common.h index ee4890d91ddd..4aaebb69ddde 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_common.h +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_common.h @@ -13,14 +13,61 @@ #define HBG_RX_SKIP1 0x00 #define HBG_RX_SKIP2 0x01 #define HBG_VECTOR_NUM 4 +#define HBG_PCU_CACHE_LINE_SIZE 32 +#define HBG_TX_TIMEOUT_BUF_LEN 1024 + +enum hbg_dir { + HBG_DIR_TX =3D 1 << 0, + HBG_DIR_RX =3D 1 << 1, + HBG_DIR_TX_RX =3D HBG_DIR_TX | HBG_DIR_RX, +}; + +enum hbg_tx_state { + HBG_TX_STATE_COMPLETE =3D 0, /* clear state, must fix to 0 */ + HBG_TX_STATE_START, +}; =20 enum hbg_nic_state { HBG_NIC_STATE_EVENT_HANDLING =3D 0, }; =20 +struct hbg_buffer { + u32 state; + dma_addr_t state_dma; + + struct sk_buff *skb; + dma_addr_t skb_dma; + u32 skb_len; + + enum hbg_dir dir; + struct hbg_ring *ring; + struct hbg_priv *priv; +}; + +struct hbg_ring { + struct hbg_buffer *queue; + dma_addr_t queue_dma; + + union { + u32 head; + u32 ntc; + }; + union { + u32 tail; + u32 ntu; + }; + u32 len; + + enum hbg_dir dir; + struct hbg_priv *priv; + struct napi_struct napi; + char *tout_log_buf; /* tx timeout log buffer */ +}; + enum hbg_hw_event_type { HBG_HW_EVENT_NONE =3D 0, HBG_HW_EVENT_INIT, /* driver is loading */ + HBG_HW_EVENT_RESET, }; =20 struct hbg_dev_specs { @@ -73,6 +120,7 @@ struct hbg_priv { unsigned long state; struct hbg_mac mac; struct hbg_vector vectors; + struct hbg_ring tx_ring; }; =20 #endif diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.c b/drivers/net/= ethernet/hisilicon/hibmcge/hbg_hw.c index 229324fa659d..457204af824b 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.c +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.c @@ -72,6 +72,7 @@ static int hbg_hw_dev_specs_init(struct hbg_priv *priv) if (!is_valid_ether_addr((u8 *)dev_specs->mac_addr.sa_data)) return -EADDRNOTAVAIL; =20 + dev_specs->max_frame_len =3D HBG_PCU_CACHE_LINE_SIZE + dev_specs->max_mtu; return 0; } =20 @@ -168,6 +169,23 @@ void hbg_hw_mac_enable(struct hbg_priv *priv, u32 enab= le) HBG_REG_PORT_ENABLE_RX_B, enable); } =20 +u32 hbg_hw_get_fifo_used_num(struct hbg_priv *priv, enum hbg_dir dir) +{ + if (dir & HBG_DIR_TX) + return hbg_reg_read_field(priv, HBG_REG_CF_CFF_DATA_NUM_ADDR, + HBG_REG_CF_CFF_DATA_NUM_ADDR_TX_M); + + return 0; +} + +void hbg_hw_set_tx_desc(struct hbg_priv *priv, struct hbg_tx_desc *tx_desc) +{ + hbg_reg_write(priv, HBG_REG_TX_CFF_ADDR_0_ADDR, tx_desc->word0); + hbg_reg_write(priv, HBG_REG_TX_CFF_ADDR_1_ADDR, tx_desc->word1); + hbg_reg_write(priv, HBG_REG_TX_CFF_ADDR_2_ADDR, tx_desc->word2); + hbg_reg_write(priv, HBG_REG_TX_CFF_ADDR_3_ADDR, tx_desc->word3); +} + void hbg_hw_adjust_link(struct hbg_priv *priv, u32 speed, u32 duplex) { hbg_reg_write_field(priv, HBG_REG_PORT_MODE_ADDR, diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.h b/drivers/net/= ethernet/hisilicon/hibmcge/hbg_hw.h index 0ce500e907b3..508e41cce41e 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.h +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_hw.h @@ -52,5 +52,7 @@ void hbg_hw_irq_enable(struct hbg_priv *priv, u32 mask, b= ool enable); void hbg_hw_set_mtu(struct hbg_priv *priv, u16 mtu); void hbg_hw_mac_enable(struct hbg_priv *priv, u32 enable); void hbg_hw_set_uc_addr(struct hbg_priv *priv, u64 mac_addr); +u32 hbg_hw_get_fifo_used_num(struct hbg_priv *priv, enum hbg_dir dir); +void hbg_hw_set_tx_desc(struct hbg_priv *priv, struct hbg_tx_desc *tx_desc= ); =20 #endif diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_irq.c b/drivers/net= /ethernet/hisilicon/hibmcge/hbg_irq.c index 9a8e2ad267a0..9ebaf03f13c8 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_irq.c +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_irq.c @@ -13,6 +13,12 @@ static void hbg_irq_handle_err(struct hbg_priv *priv, "receive error interrupt: %s\n", irq_info->name); } =20 +static void hbg_irq_handle_tx(struct hbg_priv *priv, + struct hbg_irq_info *irq_info) +{ + napi_schedule(&priv->tx_ring.napi); +} + #define HBG_TXRX_IRQ_I(name, handle) \ {#name, HBG_INT_MSK_##name##_B, false, false, 0, handle} #define HBG_ERR_IRQ_I(name, need_print) \ @@ -20,7 +26,7 @@ static void hbg_irq_handle_err(struct hbg_priv *priv, =20 static struct hbg_irq_info hbg_irqs[] =3D { HBG_TXRX_IRQ_I(RX, NULL), - HBG_TXRX_IRQ_I(TX, NULL), + HBG_TXRX_IRQ_I(TX, hbg_irq_handle_tx), HBG_ERR_IRQ_I(MAC_MII_FIFO_ERR, true), HBG_ERR_IRQ_I(MAC_PCS_RX_FIFO_ERR, true), HBG_ERR_IRQ_I(MAC_PCS_TX_FIFO_ERR, true), diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_main.c b/drivers/ne= t/ethernet/hisilicon/hibmcge/hbg_main.c index 3f6f3b381c50..9bea5e21066f 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_main.c +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_main.c @@ -9,6 +9,9 @@ #include "hbg_hw.h" #include "hbg_irq.h" #include "hbg_mdio.h" +#include "hbg_txrx.h" + +static void hbg_change_mtu(struct hbg_priv *priv, int new_mtu); =20 static void hbg_all_irq_enable(struct hbg_priv *priv, bool enabled) { @@ -24,6 +27,11 @@ static void hbg_all_irq_enable(struct hbg_priv *priv, bo= ol enabled) static int hbg_net_open(struct net_device *netdev) { struct hbg_priv *priv =3D netdev_priv(netdev); + int ret; + + ret =3D hbg_txrx_init(priv); + if (ret) + return ret; =20 hbg_all_irq_enable(priv, true); hbg_hw_mac_enable(priv, HBG_STATUS_ENABLE); @@ -33,6 +41,26 @@ static int hbg_net_open(struct net_device *netdev) return 0; } =20 +/* This function only can be called after hbg_txrx_uninit() */ +static int hbg_hw_txrx_clear(struct hbg_priv *priv) +{ + int ret; + + /* After ring buffers have been released, + * do a reset to release hw fifo rx ring buffer + */ + ret =3D hbg_hw_event_notify(priv, HBG_HW_EVENT_RESET); + if (ret) + return ret; + + /* After reset, regs need to be reconfigured */ + hbg_hw_init(priv); + hbg_hw_set_uc_addr(priv, ether_addr_to_u64(priv->netdev->dev_addr)); + hbg_change_mtu(priv, priv->netdev->mtu); + + return 0; +} + static int hbg_net_stop(struct net_device *netdev) { struct hbg_priv *priv =3D netdev_priv(netdev); @@ -41,8 +69,8 @@ static int hbg_net_stop(struct net_device *netdev) netif_stop_queue(netdev); hbg_hw_mac_enable(priv, HBG_STATUS_DISABLE); hbg_all_irq_enable(priv, false); - - return 0; + hbg_txrx_uninit(priv); + return hbg_hw_txrx_clear(priv); } =20 static int hbg_net_set_mac_address(struct net_device *netdev, void *addr) @@ -86,12 +114,33 @@ static int hbg_net_change_mtu(struct net_device *netde= v, int new_mtu) return 0; } =20 +static void hbg_net_tx_timeout(struct net_device *netdev, unsigned int txq= ueue) +{ + struct hbg_priv *priv =3D netdev_priv(netdev); + struct hbg_ring *ring =3D &priv->tx_ring; + char *buf =3D ring->tout_log_buf; + u32 pos =3D 0; + + pos +=3D scnprintf(buf + pos, HBG_TX_TIMEOUT_BUF_LEN - pos, + "ring used num: %u, fifo used num: %u\n", + hbg_get_queue_used_num(ring), + hbg_hw_get_fifo_used_num(priv, HBG_DIR_TX)); + pos +=3D scnprintf(buf + pos, HBG_TX_TIMEOUT_BUF_LEN - pos, + "ntc: %u, ntu: %u, irq enabled: %u\n", + ring->ntc, ring->ntu, + hbg_hw_irq_is_enabled(priv, HBG_INT_MSK_TX_B)); + + netdev_info(netdev, "%s", buf); +} + static const struct net_device_ops hbg_netdev_ops =3D { .ndo_open =3D hbg_net_open, .ndo_stop =3D hbg_net_stop, + .ndo_start_xmit =3D hbg_net_start_xmit, .ndo_validate_addr =3D eth_validate_addr, .ndo_set_mac_address =3D hbg_net_set_mac_address, .ndo_change_mtu =3D hbg_net_change_mtu, + .ndo_tx_timeout =3D hbg_net_tx_timeout, }; =20 static int hbg_init(struct hbg_priv *priv) @@ -170,6 +219,7 @@ static int hbg_probe(struct pci_dev *pdev, const struct= pci_device_id *ent) netdev->max_mtu =3D priv->dev_specs.max_mtu; netdev->min_mtu =3D priv->dev_specs.min_mtu; netdev->netdev_ops =3D &hbg_netdev_ops; + netdev->watchdog_timeo =3D 5 * HZ; =20 hbg_change_mtu(priv, ETH_DATA_LEN); hbg_net_set_mac_address(priv->netdev, &priv->dev_specs.mac_addr); diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h b/drivers/net= /ethernet/hisilicon/hibmcge/hbg_reg.h index fbc17ca5564f..0b7926a2a4fa 100644 --- a/drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_reg.h @@ -80,6 +80,12 @@ #define HBG_REG_CF_INTRPT_CLR_ADDR (HBG_REG_SGMII_BASE + 0x0438) #define HBG_REG_MAX_FRAME_LEN_ADDR (HBG_REG_SGMII_BASE + 0x0444) #define HBG_REG_MAX_FRAME_LEN_M GENMASK(15, 0) +#define HBG_REG_CF_CFF_DATA_NUM_ADDR (HBG_REG_SGMII_BASE + 0x045C) +#define HBG_REG_CF_CFF_DATA_NUM_ADDR_TX_M GENMASK(8, 0) +#define HBG_REG_TX_CFF_ADDR_0_ADDR (HBG_REG_SGMII_BASE + 0x0488) +#define HBG_REG_TX_CFF_ADDR_1_ADDR (HBG_REG_SGMII_BASE + 0x048C) +#define HBG_REG_TX_CFF_ADDR_2_ADDR (HBG_REG_SGMII_BASE + 0x0490) +#define HBG_REG_TX_CFF_ADDR_3_ADDR (HBG_REG_SGMII_BASE + 0x0494) #define HBG_REG_RX_BUF_SIZE_ADDR (HBG_REG_SGMII_BASE + 0x04E4) #define HBG_REG_RX_BUF_SIZE_M GENMASK(15, 0) #define HBG_REG_BUS_CTRL_ADDR (HBG_REG_SGMII_BASE + 0x04E8) @@ -108,4 +114,17 @@ enum hbg_port_mode { HBG_PORT_MODE_SGMII_1000M =3D 0x8, }; =20 +struct hbg_tx_desc { + u32 word0; + u32 word1; + u32 word2; /* pkt_addr */ + u32 word3; /* clear_addr */ +}; + +#define HBG_TX_DESC_W0_IP_OFF_M GENMASK(30, 26) +#define HBG_TX_DESC_W0_l3_CS_B BIT(2) +#define HBG_TX_DESC_W0_WB_B BIT(1) +#define HBG_TX_DESC_W0_l4_CS_B BIT(0) +#define HBG_TX_DESC_W1_SEND_LEN_M GENMASK(19, 4) + #endif diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_txrx.c b/drivers/ne= t/ethernet/hisilicon/hibmcge/hbg_txrx.c new file mode 100644 index 000000000000..4dafcfcfc6b5 --- /dev/null +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_txrx.c @@ -0,0 +1,267 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2024 Hisilicon Limited. + +#include +#include "hbg_common.h" +#include "hbg_irq.h" +#include "hbg_reg.h" +#include "hbg_txrx.h" + +#define netdev_get_tx_ring(netdev) (&(((struct hbg_priv *)netdev_priv(net= dev))->tx_ring)) + +#define buffer_to_dma_dir(buffer) (((buffer)->dir =3D=3D HBG_DIR_RX) ? \ + DMA_FROM_DEVICE : DMA_TO_DEVICE) + +#define hbg_queue_used_num(head, tail, ring) ({ \ + typeof(ring) _ring =3D (ring); \ + ((tail) + _ring->len - (head)) % _ring->len; }) +#define hbg_queue_left_num(head, tail, ring) \ + ((ring)->len - hbg_queue_used_num((head), (tail), (ring)) - 1) +#define hbg_queue_is_empty(head, tail, ring) \ + (hbg_queue_used_num((head), (tail), (ring)) =3D=3D 0) +#define hbg_queue_next_prt(p, ring) (((p) + 1) % (ring)->len) + +#define HBG_TX_STOP_THRS 2 +#define HBG_TX_START_THRS (2 * HBG_TX_STOP_THRS) + +static int hbg_dma_map(struct hbg_buffer *buffer) +{ + struct hbg_priv *priv =3D buffer->priv; + + buffer->skb_dma =3D dma_map_single(&priv->pdev->dev, + buffer->skb->data, buffer->skb_len, + buffer_to_dma_dir(buffer)); + if (unlikely(dma_mapping_error(&priv->pdev->dev, buffer->skb_dma))) + return -ENOMEM; + + return 0; +} + +static void hbg_dma_unmap(struct hbg_buffer *buffer) +{ + struct hbg_priv *priv =3D buffer->priv; + + if (unlikely(!buffer->skb_dma)) + return; + + dma_unmap_single(&priv->pdev->dev, buffer->skb_dma, buffer->skb_len, + buffer_to_dma_dir(buffer)); + buffer->skb_dma =3D 0; +} + +static void hbg_init_tx_desc(struct hbg_buffer *buffer, + struct hbg_tx_desc *tx_desc) +{ + u32 ip_offset =3D buffer->skb->network_header - buffer->skb->mac_header; + u32 word0 =3D 0; + + word0 |=3D FIELD_PREP(HBG_TX_DESC_W0_WB_B, HBG_STATUS_ENABLE); + word0 |=3D FIELD_PREP(HBG_TX_DESC_W0_IP_OFF_M, ip_offset); + if (likely(buffer->skb->ip_summed =3D=3D CHECKSUM_PARTIAL)) { + word0 |=3D FIELD_PREP(HBG_TX_DESC_W0_l3_CS_B, HBG_STATUS_ENABLE); + word0 |=3D FIELD_PREP(HBG_TX_DESC_W0_l4_CS_B, HBG_STATUS_ENABLE); + } + + tx_desc->word0 =3D word0; + tx_desc->word1 =3D FIELD_PREP(HBG_TX_DESC_W1_SEND_LEN_M, buffer->skb->len= ); + tx_desc->word2 =3D buffer->skb_dma; + tx_desc->word3 =3D buffer->state_dma; +} + +netdev_tx_t hbg_net_start_xmit(struct sk_buff *skb, struct net_device *net= dev) +{ + struct hbg_ring *ring =3D netdev_get_tx_ring(netdev); + struct hbg_priv *priv =3D netdev_priv(netdev); + /* This smp_load_acquire() pairs with smp_store_release() in + * hbg_napi_tx_recycle() called in tx interrupt handle process. + */ + u32 ntc =3D smp_load_acquire(&ring->ntc); + struct hbg_buffer *buffer; + struct hbg_tx_desc tx_desc; + u32 ntu =3D ring->ntu; + + if (unlikely(!skb->len || + skb->len > hbg_spec_max_frame_len(priv, HBG_DIR_TX))) { + dev_kfree_skb_any(skb); + netdev->stats.tx_errors++; + return NETDEV_TX_OK; + } + + if (!netif_subqueue_maybe_stop(netdev, 0, + hbg_queue_left_num(ntc, ntu, ring), + HBG_TX_STOP_THRS, HBG_TX_START_THRS)) + return NETDEV_TX_BUSY; + + buffer =3D &ring->queue[ntu]; + buffer->skb =3D skb; + buffer->skb_len =3D skb->len; + if (unlikely(hbg_dma_map(buffer))) { + dev_kfree_skb_any(skb); + return NETDEV_TX_OK; + } + + buffer->state =3D HBG_TX_STATE_START; + hbg_init_tx_desc(buffer, &tx_desc); + hbg_hw_set_tx_desc(priv, &tx_desc); + + /* This smp_store_release() pairs with smp_load_acquire() in + * hbg_napi_tx_recycle() called in tx interrupt handle process. + */ + smp_store_release(&ring->ntu, hbg_queue_next_prt(ntu, ring)); + dev_sw_netstats_tx_add(netdev, 1, skb->len); + return NETDEV_TX_OK; +} + +static void hbg_buffer_free_skb(struct hbg_buffer *buffer) +{ + if (unlikely(!buffer->skb)) + return; + + dev_kfree_skb_any(buffer->skb); + buffer->skb =3D NULL; +} + +static void hbg_buffer_free(struct hbg_buffer *buffer) +{ + hbg_dma_unmap(buffer); + hbg_buffer_free_skb(buffer); +} + +static int hbg_napi_tx_recycle(struct napi_struct *napi, int budget) +{ + struct hbg_ring *ring =3D container_of(napi, struct hbg_ring, napi); + /* This smp_load_acquire() pairs with smp_store_release() in + * hbg_net_start_xmit() called in xmit process. + */ + u32 ntu =3D smp_load_acquire(&ring->ntu); + struct hbg_priv *priv =3D ring->priv; + struct hbg_buffer *buffer; + u32 ntc =3D ring->ntc; + int packet_done =3D 0; + + /* We need do cleanup even if budget is 0. + * Per NAPI documentation budget is for Rx. + * So We hardcode the amount of work Tx NAPI does to 128. + */ + budget =3D 128; + while (packet_done < budget) { + if (unlikely(hbg_queue_is_empty(ntc, ntu, ring))) + break; + + /* make sure HW write desc complete */ + dma_rmb(); + + buffer =3D &ring->queue[ntc]; + if (buffer->state !=3D HBG_TX_STATE_COMPLETE) + break; + + hbg_buffer_free(buffer); + ntc =3D hbg_queue_next_prt(ntc, ring); + packet_done++; + } + + /* This smp_store_release() pairs with smp_load_acquire() in + * hbg_net_start_xmit() called in xmit process. + */ + smp_store_release(&ring->ntc, ntc); + netif_wake_queue(priv->netdev); + + if (likely(packet_done < budget && + napi_complete_done(napi, packet_done))) + hbg_hw_irq_enable(priv, HBG_INT_MSK_TX_B, true); + + return packet_done; +} + +static void hbg_ring_uninit(struct hbg_ring *ring) +{ + struct hbg_buffer *buffer; + u32 i; + + if (!ring->queue) + return; + + napi_disable(&ring->napi); + netif_napi_del(&ring->napi); + + for (i =3D 0; i < ring->len; i++) { + buffer =3D &ring->queue[i]; + hbg_buffer_free(buffer); + buffer->ring =3D NULL; + buffer->priv =3D NULL; + } + + dma_free_coherent(&ring->priv->pdev->dev, + ring->len * sizeof(*ring->queue), + ring->queue, ring->queue_dma); + ring->queue =3D NULL; + ring->queue_dma =3D 0; + ring->len =3D 0; + ring->priv =3D NULL; +} + +static int hbg_ring_init(struct hbg_priv *priv, struct hbg_ring *ring, + int (*napi_poll)(struct napi_struct *, int), + enum hbg_dir dir) +{ + struct hbg_buffer *buffer; + u32 i, len; + + len =3D hbg_get_spec_fifo_max_num(priv, dir) + 1; + ring->queue =3D dma_alloc_coherent(&priv->pdev->dev, + len * sizeof(*ring->queue), + &ring->queue_dma, GFP_KERNEL); + if (!ring->queue) + return -ENOMEM; + + for (i =3D 0; i < len; i++) { + buffer =3D &ring->queue[i]; + buffer->skb_len =3D 0; + buffer->dir =3D dir; + buffer->ring =3D ring; + buffer->priv =3D priv; + buffer->state_dma =3D ring->queue_dma + (i * sizeof(*buffer)); + } + + ring->dir =3D dir; + ring->priv =3D priv; + ring->ntc =3D 0; + ring->ntu =3D 0; + ring->len =3D len; + + netif_napi_add_tx(priv->netdev, &ring->napi, napi_poll); + napi_enable(&ring->napi); + return 0; +} + +static int hbg_tx_ring_init(struct hbg_priv *priv) +{ + struct hbg_ring *tx_ring =3D &priv->tx_ring; + + if (!tx_ring->tout_log_buf) + tx_ring->tout_log_buf =3D devm_kmalloc(&priv->pdev->dev, + HBG_TX_TIMEOUT_BUF_LEN, + GFP_KERNEL); + + if (!tx_ring->tout_log_buf) + return -ENOMEM; + + return hbg_ring_init(priv, tx_ring, hbg_napi_tx_recycle, HBG_DIR_TX); +} + +int hbg_txrx_init(struct hbg_priv *priv) +{ + int ret; + + ret =3D hbg_tx_ring_init(priv); + if (ret) + dev_err(&priv->pdev->dev, + "failed to init tx ring, ret =3D %d\n", ret); + + return ret; +} + +void hbg_txrx_uninit(struct hbg_priv *priv) +{ + hbg_ring_uninit(&priv->tx_ring); +} diff --git a/drivers/net/ethernet/hisilicon/hibmcge/hbg_txrx.h b/drivers/ne= t/ethernet/hisilicon/hibmcge/hbg_txrx.h new file mode 100644 index 000000000000..73aca4b850a8 --- /dev/null +++ b/drivers/net/ethernet/hisilicon/hibmcge/hbg_txrx.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Copyright (c) 2024 Hisilicon Limited. */ + +#ifndef __HBG_TXRX_H +#define __HBG_TXRX_H + +#include +#include "hbg_hw.h" + +static inline u32 hbg_spec_max_frame_len(struct hbg_priv *priv, enum hbg_d= ir dir) +{ + return (dir =3D=3D HBG_DIR_TX) ? priv->dev_specs.max_frame_len : + priv->dev_specs.rx_buf_size; +} + +static inline u32 hbg_get_spec_fifo_max_num(struct hbg_priv *priv, enum hb= g_dir dir) +{ + return (dir =3D=3D HBG_DIR_TX) ? priv->dev_specs.tx_fifo_num : + priv->dev_specs.rx_fifo_num; +} + +static inline bool hbg_fifo_is_full(struct hbg_priv *priv, enum hbg_dir di= r) +{ + return hbg_hw_get_fifo_used_num(priv, dir) >=3D + hbg_get_spec_fifo_max_num(priv, dir); +} + +static inline u32 hbg_get_queue_used_num(struct hbg_ring *ring) +{ + return (ring->ntu + ring->len - ring->ntc) % ring->len; +} + +netdev_tx_t hbg_net_start_xmit(struct sk_buff *skb, struct net_device *net= dev); +int hbg_txrx_init(struct hbg_priv *priv); +void hbg_txrx_uninit(struct hbg_priv *priv); + +#endif --=20 2.33.0