From nobody Wed Nov 27 18:55:59 2024 Received: from mail-pf1-f179.google.com (mail-pf1-f179.google.com [209.85.210.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B71C2204D8 for ; Tue, 8 Oct 2024 22:38:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728427120; cv=none; b=UXL2Gtpwkr2260iRt0iqTVFgOKrxHzW7zMImS8mntTBYCjWwA/QdITg5FjZhoPoCm5ZigQ6wuQAHFnZhZ3hsUbKU4AebgNAjHWJn32uHFySbmb9HKexs2GApCJOUal3CKFVzYi31q4AoiTQ8UIRd514ZhKdjLIzQMBlOUI7so7k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728427120; c=relaxed/simple; bh=/9u0F4hQc74Y4MO2+TwNDZibu87i167PyYHkW9Ck3RQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jV+Q/bhRDokXa0/Mq7JoQ0w75PGs6dYOHci3T9iSje4AGZNmUltwwPyMERYj7dNEZanJ4D1SNfpBOTUHhSzRGGR4stsV9zgq+QXR9kw/VpVlE3M8/VD4TFRYayz78/wFFXLK3I3uFvGshUNcGYu5X+pgwrTBsDp8rzsUofBAcUk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=xnrp4pGv; arc=none smtp.client-ip=209.85.210.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="xnrp4pGv" Received: by mail-pf1-f179.google.com with SMTP id d2e1a72fcca58-71dfc1124cdso223658b3a.1 for ; Tue, 08 Oct 2024 15:38:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1728427118; x=1729031918; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=H2HJsBemoUtn69Y0WdrOXv10G4III+URyauyH8vTu7Q=; b=xnrp4pGv3OpuDtJ+zonv48R/ksb7gbpuOoxw5XKa9zzZ1WPaVL7GsBC/DHzE9nlE5W +NsrntIkwwPgyYA0SdZAefbfRrkW+Wxg7bGvZ+Pb110qdfjA1nk6FHzlKL6ldxdqiIuJ iG0AdEf0w1rwqNKPGPRVJnb1k7yIDZSCfRmf3ZXUk4Bwp75zsyWGVfolL+3u7vR1IBXT wY9z0rZUtCUYUWZPzlWoxWhD9wZZvD9fRuv70rUojf30bji8GEmW+7foWOcE9A0xqYdp JTcGd1Lw+8z6QqRmQg4gozMYUOJNKaG2esMfCBQSRt4CUWrgqlOGJGasgQknzMxh9hRQ 9zQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728427118; x=1729031918; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H2HJsBemoUtn69Y0WdrOXv10G4III+URyauyH8vTu7Q=; b=Hxf6av/QYN7PEUIM+ewAsN+HM08LZQUczX8bQyJESiJTGhjNV1JrIKrhWZNXSgGiyJ 6YLFm54k+d2GXjcrIvD0jPXzUucKg4MTRFdqM58qD+fksuupKnvGi208C9qe5iYdyoKY LH+xhRwzXC2/9fOwW7sFSfECKmQm0iXwATXzocdrTaT8C1fpE+Z2KTLIJXukPJfFBlwI zJEMVFuiInIak1jLJZLL5h9qD6TgmWOLDpcGIFLDBOQ23zwvmQBv9xhfT7+gvAARnBJ3 d6M9RJyYoKoC45SzLCu26ijP9POamyhrCShlYCBBcX0gqo39iDrlgOPU9SwBTT7IOltE 81Fg== X-Gm-Message-State: AOJu0YwV5x28smDPXBPtP4+/6XIERDaUK+To1AWSmBGeyIBR4s4D8F5k lpLQPyvknLTQNljENcieQmu5as/PqW2a4NhLdDOlDNX2fX/DMcUSEylMffjeAX0= X-Google-Smtp-Source: AGHT+IG1wGSlqMBE3PBvpa6FjggvdA8TOV0s8RC2JgpdWWcLYtxJbO7UMJi9+bIzOEiti8s0uhAHTQ== X-Received: by 2002:a05:6a00:2e08:b0:71d:f459:6df3 with SMTP id d2e1a72fcca58-71e1d6a47f2mr972694b3a.10.1728427117956; Tue, 08 Oct 2024 15:38:37 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71df0ccc4b2sm6591270b3a.45.2024.10.08.15.38.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 15:38:37 -0700 (PDT) From: Deepak Gupta Date: Tue, 08 Oct 2024 15:37:00 -0700 Subject: [PATCH v6 18/33] prctl: arch-agnostic prctl for indirect branch tracking Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241008-v5_user_cfi_series-v6-18-60d9fe073f37@rivosinc.com> References: <20241008-v5_user_cfi_series-v6-0-60d9fe073f37@rivosinc.com> In-Reply-To: <20241008-v5_user_cfi_series-v6-0-60d9fe073f37@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, Deepak Gupta X-Mailer: b4 0.14.0 Three architectures (x86, aarch64, riscv) have support for indirect branch tracking feature in a very similar fashion. On a very high level, indirect branch tracking is a CPU feature where CPU tracks branches which uses memory operand to perform control transfer in program. As part of this tracking on indirect branches, CPU goes in a state where it expects a landing pad instr on target and if not found then CPU raises some fault (architecture dependent) x86 landing pad instr - `ENDBRANCH` aarch64 landing pad instr - `BTI` riscv landing instr - `lpad` Given that three major arches have support for indirect branch tracking, This patch makes `prctl` for indirect branch tracking arch agnostic. To allow userspace to enable this feature for itself, following prtcls are defined: - PR_GET_INDIR_BR_LP_STATUS: Gets current configured status for indirect branch tracking. - PR_SET_INDIR_BR_LP_STATUS: Sets a configuration for indirect branch tracking. Following status options are allowed - PR_INDIR_BR_LP_ENABLE: Enables indirect branch tracking on user thread. - PR_INDIR_BR_LP_DISABLE; Disables indirect branch tracking on user thread. - PR_LOCK_INDIR_BR_LP_STATUS: Locks configured status for indirect branch tracking for user thread. Signed-off-by: Deepak Gupta Reviewed-by: Mark Brown --- include/linux/cpu.h | 4 ++++ include/uapi/linux/prctl.h | 27 +++++++++++++++++++++++++++ kernel/sys.c | 30 ++++++++++++++++++++++++++++++ 3 files changed, 61 insertions(+) diff --git a/include/linux/cpu.h b/include/linux/cpu.h index bdcec1732445..eff56aae05d7 100644 --- a/include/linux/cpu.h +++ b/include/linux/cpu.h @@ -203,4 +203,8 @@ static inline bool cpu_mitigations_auto_nosmt(void) } #endif =20 +int arch_get_indir_br_lp_status(struct task_struct *t, unsigned long __use= r *status); +int arch_set_indir_br_lp_status(struct task_struct *t, unsigned long statu= s); +int arch_lock_indir_br_lp_status(struct task_struct *t, unsigned long stat= us); + #endif /* _LINUX_CPU_H_ */ diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h index b8d7b6361754..41ffb53490a4 100644 --- a/include/uapi/linux/prctl.h +++ b/include/uapi/linux/prctl.h @@ -349,4 +349,31 @@ struct prctl_mm_map { */ #define PR_LOCK_SHADOW_STACK_STATUS 76 =20 +/* + * Get the current indirect branch tracking configuration for the current + * thread, this will be the value configured via PR_SET_INDIR_BR_LP_STATUS. + */ +#define PR_GET_INDIR_BR_LP_STATUS 77 + +/* + * Set the indirect branch tracking configuration. PR_INDIR_BR_LP_ENABLE w= ill + * enable cpu feature for user thread, to track all indirect branches and = ensure + * they land on arch defined landing pad instruction. + * x86 - If enabled, an indirect branch must land on `ENDBRANCH` instructi= on. + * arch64 - If enabled, an indirect branch must land on `BTI` instruction. + * riscv - If enabled, an indirect branch must land on `lpad` instruction. + * PR_INDIR_BR_LP_DISABLE will disable feature for user thread and indirect + * branches will no more be tracked by cpu to land on arch defined landing= pad + * instruction. + */ +#define PR_SET_INDIR_BR_LP_STATUS 78 +# define PR_INDIR_BR_LP_ENABLE (1UL << 0) + +/* + * Prevent further changes to the specified indirect branch tracking + * configuration. All bits may be locked via this call, including + * undefined bits. + */ +#define PR_LOCK_INDIR_BR_LP_STATUS 79 + #endif /* _LINUX_PRCTL_H */ diff --git a/kernel/sys.c b/kernel/sys.c index 3d38a9c7c5c9..dafa31485584 100644 --- a/kernel/sys.c +++ b/kernel/sys.c @@ -2339,6 +2339,21 @@ int __weak arch_lock_shadow_stack_status(struct task= _struct *t, unsigned long st return -EINVAL; } =20 +int __weak arch_get_indir_br_lp_status(struct task_struct *t, unsigned lon= g __user *status) +{ + return -EINVAL; +} + +int __weak arch_set_indir_br_lp_status(struct task_struct *t, unsigned lon= g status) +{ + return -EINVAL; +} + +int __weak arch_lock_indir_br_lp_status(struct task_struct *t, unsigned lo= ng status) +{ + return -EINVAL; +} + #define PR_IO_FLUSHER (PF_MEMALLOC_NOIO | PF_LOCAL_THROTTLE) =20 #ifdef CONFIG_ANON_VMA_NAME @@ -2814,6 +2829,21 @@ SYSCALL_DEFINE5(prctl, int, option, unsigned long, a= rg2, unsigned long, arg3, return -EINVAL; error =3D arch_lock_shadow_stack_status(me, arg2); break; + case PR_GET_INDIR_BR_LP_STATUS: + if (arg3 || arg4 || arg5) + return -EINVAL; + error =3D arch_get_indir_br_lp_status(me, (unsigned long __user *) arg2); + break; + case PR_SET_INDIR_BR_LP_STATUS: + if (arg3 || arg4 || arg5) + return -EINVAL; + error =3D arch_set_indir_br_lp_status(me, arg2); + break; + case PR_LOCK_INDIR_BR_LP_STATUS: + if (arg3 || arg4 || arg5) + return -EINVAL; + error =3D arch_lock_indir_br_lp_status(me, arg2); + break; default: error =3D -EINVAL; break; --=20 2.45.0