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[83.233.6.197]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2faf9ab1564sm10972441fa.7.2024.10.08.00.03.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Oct 2024 00:03:15 -0700 (PDT) From: Marcus Folkesson Date: Tue, 08 Oct 2024 09:02:44 +0200 Subject: [PATCH v5 1/2] mtd: nand: davinci: add support for on-die ECC engine type Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241008-ondie-v5-1-041ca4ccc5ee@gmail.com> References: <20241008-ondie-v5-0-041ca4ccc5ee@gmail.com> In-Reply-To: <20241008-ondie-v5-0-041ca4ccc5ee@gmail.com> To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Marcus Folkesson X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1761; i=marcus.folkesson@gmail.com; h=from:subject:message-id; bh=PDm1f5NEBuhwxeXGvwzqxiOMHTZXe7TWbR431qOgkS4=; b=owEBbQKS/ZANAwAIAYiATm9ZXVIyAcsmYgBnBNkebjGmYRrtlhenm+K3h8wiuFZxvVSZrNvwD ArtFpwR3SGJAjMEAAEIAB0WIQQFUaLotmy1TWTBLGWIgE5vWV1SMgUCZwTZHgAKCRCIgE5vWV1S MruBEADehX3XFOMU22oAj4rCjhuoOpjY1i8KZ7VJFHpHztpYdurG8OpZNw2ZPWw3LN1gCGZiUqa pytKoyHppOK/HFoTv48/GQ64kAUWoyYFpYEKu0gyxBXy65U0zllfn9ER51Ed4BTCbPGn15V0ylo OUhYxCU5HIin7sEu7QyaO61mO27Kx08i+f27qS35/ROp3vge4MP15olSsF5JaJMjAHTf7w1nTAR JRAxQ+dJ3ldSSB2gDEeAQ13Tvq03ZWF3hq4g88vAhUZnH04hgdhtyN+0CuIKIy+lp3fg0YqR2Cr LB3YkbVRh77cjXJppZEZdQEUsvEyz3Z9vqrNsIvJJNXgPTPnQAXBQ8m+WyES/7LNWbo2NI5+lNR 6sGBUfAe9xnJkameaw81NOlIAptgje6on4YAm9vDURoGWyphM6oKvQlrQuDVkkr7BUmR8IKWv9Y PqSpv6tvRjEuVuzHlS/PAsyazqm1OEP6gx6hM61Kbx3oXz9dLwpfa4S0ZTVxUK2VHO220IyxQZN W/Nci58Ixja/SEbtZaBAicrKouGf6rn7gR7rk6NLXQrOBaFbFICkebMYPngaj+ZeGEGOD7yhxe1 tZ141OsiJOrrEMOwqgGhUtMsLWFN+g4r6WuzcJ12YY1dX2HABJLO7MUHvzCB6ea9yZQTgzKw0nD YouXThlSAhTsRvw== X-Developer-Key: i=marcus.folkesson@gmail.com; a=openpgp; fpr=AB91D46C7E0F6E6FB2AB640EC0FE25D598F6C127 Some chips, e.g. Micron MT29F1G08ABBFAH4, has a mandatory on-die ECC. Add "on-die" as ECC engine type in order to be compatible with those. Signed-off-by: Marcus Folkesson --- drivers/mtd/nand/raw/davinci_nand.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/dav= inci_nand.c index 392678143a36b20b42c1827eee8203dc2e41889a..79e768d337ae12f6e8d7f21f1ac= d4e259f4f3020 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -66,6 +66,7 @@ struct davinci_nand_pdata { =20 /* none =3D=3D NAND_ECC_ENGINE_TYPE_NONE (strongly *not* advised!!) * soft =3D=3D NAND_ECC_ENGINE_TYPE_SOFT + * on-die =3D=3D NAND_ECC_ENGINE_TYPE_ON_DIE * else =3D=3D NAND_ECC_ENGINE_TYPE_ON_HOST, according to ecc_bits * * All DaVinci-family chips support 1-bit hardware ECC. @@ -524,6 +525,8 @@ static struct davinci_nand_pdata pdata->engine_type =3D NAND_ECC_ENGINE_TYPE_SOFT; if (!strncmp("hw", mode, 2)) pdata->engine_type =3D NAND_ECC_ENGINE_TYPE_ON_HOST; + if (!strncmp("on-die", mode, 6)) + pdata->engine_type =3D NAND_ECC_ENGINE_TYPE_ON_DIE; } if (!of_property_read_u32(pdev->dev.of_node, "ti,davinci-ecc-bits", &prop)) @@ -580,6 +583,7 @@ static int davinci_nand_attach_chip(struct nand_chip *c= hip) =20 switch (chip->ecc.engine_type) { case NAND_ECC_ENGINE_TYPE_NONE: + case NAND_ECC_ENGINE_TYPE_ON_DIE: pdata->ecc_bits =3D 0; break; case NAND_ECC_ENGINE_TYPE_SOFT: @@ -914,4 +918,3 @@ module_platform_driver(nand_davinci_driver); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Texas Instruments"); MODULE_DESCRIPTION("Davinci NAND flash driver"); - --=20 2.46.0 From nobody Wed Nov 27 18:41:25 2024 Received: from mail-lj1-f178.google.com (mail-lj1-f178.google.com [209.85.208.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0947F1F8EF3; Tue, 8 Oct 2024 07:03:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Signed-off-by: Marcus Folkesson --- .../devicetree/bindings/mtd/davinci-nand.txt | 94 ----------------- .../devicetree/bindings/mtd/ti,davinci-nand.yaml | 115 +++++++++++++++++= ++++ 2 files changed, 115 insertions(+), 94 deletions(-) diff --git a/Documentation/devicetree/bindings/mtd/davinci-nand.txt b/Docum= entation/devicetree/bindings/mtd/davinci-nand.txt deleted file mode 100644 index eb8e2ff4dbd2901b3c396f2e66c1f590a32dcf67..000000000000000000000000000= 0000000000000 --- a/Documentation/devicetree/bindings/mtd/davinci-nand.txt +++ /dev/null @@ -1,94 +0,0 @@ -Device tree bindings for Texas instruments Davinci/Keystone NAND controller - -This file provides information, what the device node for the davinci/keyst= one -NAND interface contains. - -Documentation: -Davinci DM646x - https://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf -Kestone - https://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf - -Required properties: - -- compatible: "ti,davinci-nand" - "ti,keystone-nand" - -- reg: Contains 2 offset/length values: - - offset and length for the access window. - - offset and length for accessing the AEMIF - control registers. - -- ti,davinci-chipselect: number of chipselect. Indicates on the - davinci_nand driver which chipselect is used - for accessing the nand. - Can be in the range [0-3]. - -Recommended properties : - -- ti,davinci-mask-ale: mask for ALE. Needed for executing address - phase. These offset will be added to the base - address for the chip select space the NAND Flash - device is connected to. - If not set equal to 0x08. - -- ti,davinci-mask-cle: mask for CLE. Needed for executing command - phase. These offset will be added to the base - address for the chip select space the NAND Flash - device is connected to. - If not set equal to 0x10. - -- ti,davinci-mask-chipsel: mask for chipselect address. Needed to mask - addresses for given chipselect. - -- nand-ecc-mode: operation mode of the NAND ecc mode. ECC mode - valid values for davinci driver: - - "none" - - "soft" - - "hw" - -- ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4. - -- nand-bus-width: buswidth 8 or 16. If not present 8. - -- nand-on-flash-bbt: use flash based bad block table support. OOB - identifier is saved in OOB area. If not present - false. - -Deprecated properties: - -- ti,davinci-ecc-mode: operation mode of the NAND ecc mode. ECC mode - valid values for davinci driver: - - "none" - - "soft" - - "hw" - -- ti,davinci-nand-buswidth: buswidth 8 or 16. If not present 8. - -- ti,davinci-nand-use-bbt: use flash based bad block table support. OOB - identifier is saved in OOB area. If not present - false. - -Nand device bindings may contain additional sub-nodes describing partition= s of -the address space. See mtd.yaml for more detail. The NAND Flash timing -values must be programmed in the chip select=E2=80=99s node of AEMIF -memory-controller (see Documentation/devicetree/bindings/memory-controller= s/ -davinci-aemif.txt). - -Example(da850 EVM ): - -nand_cs3@62000000 { - compatible =3D "ti,davinci-nand"; - reg =3D <0x62000000 0x807ff - 0x68000000 0x8000>; - ti,davinci-chipselect =3D <1>; - ti,davinci-mask-ale =3D <0>; - ti,davinci-mask-cle =3D <0>; - ti,davinci-mask-chipsel =3D <0>; - nand-ecc-mode =3D "hw"; - ti,davinci-ecc-bits =3D <4>; - nand-on-flash-bbt; - - partition@180000 { - label =3D "ubifs"; - reg =3D <0x180000 0x7e80000>; - }; -}; diff --git a/Documentation/devicetree/bindings/mtd/ti,davinci-nand.yaml b/D= ocumentation/devicetree/bindings/mtd/ti,davinci-nand.yaml new file mode 100644 index 0000000000000000000000000000000000000000..1263616593532e8483d556b4242= b004a16620ddf --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/ti,davinci-nand.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/ti,davinci-nand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI DaVinci NAND controller + +maintainers: + - Marcus Folkesson + +allOf: + - $ref: nand-controller.yaml# + +properties: + compatible: + enum: + - ti,davinci-nand + - ti,keystone-nand + + reg: + maxItems: 1 + + partitions: + $ref: /schemas/mtd/partitions/partitions.yaml + + ti,davinci-chipselect: + description: + Number of chipselect. Indicate on the davinci_nand driver which + chipselect is used for accessing the nand. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + ti,davinci-mask-ale: + description: + Mask for ALE. Needed for executing address phase. These offset will = be + added to the base address for the chip select space the NAND Flash + device is connected to. + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0x08 + + ti,davinci-mask-cle: + description: + Mask for CLE. Needed for executing command phase. These offset will = be + added to the base address for the chip select space the NAND Flash d= evice + is connected to. + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0x10 + + ti,davinci-mask-chipsel: + description: + Mask for chipselect address. Needed to mask addresses for given + chipselect. + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + + ti,davinci-ecc-bits: + description: Used ECC bits. + enum: [1, 4] + + ti,davinci-ecc-mode: + description: Operation mode of the NAND ECC mode. + $ref: /schemas/types.yaml#/definitions/string + enum: [none, soft, hw, on-die] + deprecated: true + + ti,davinci-nand-buswidth: + description: Bus width to the NAND chip + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [8, 16] + default: 8 + deprecated: true + + ti,davinci-nand-use-bbt: + type: boolean + description: + Use flash based bad block table support. OOB identifier is saved in = OOB + area. + deprecated: true + +required: + - compatible + - reg + - ti,davinci-chipselect + +unevaluatedProperties: false + +examples: + - | + nand-controller@2000000 { + compatible =3D "ti,davinci-nand"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + reg =3D <0 0x02000000>; + ti,davinci-chipselect =3D <1>; + ti,davinci-mask-ale =3D <0>; + ti,davinci-mask-cle =3D <0>; + ti,davinci-mask-chipsel =3D <0>; + ti,davinci-nand-buswidth =3D <16>; + ti,davinci-ecc-mode =3D "hw"; + ti,davinci-ecc-bits =3D <4>; + ti,davinci-nand-use-bbt; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "u-boot env"; + reg =3D <0 0x020000>; + }; + }; + }; --=20 2.46.0