From nobody Wed Nov 27 23:45:56 2024 Received: from mail11.truemail.it (mail11.truemail.it [217.194.8.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 902DF18DF6C; Mon, 7 Oct 2024 09:32:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.194.8.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728293545; cv=none; b=RUyDk3xle8GZSv8gIySbutheHwnVYN/cf4GzKcgK26rymoNLBoCDMtCXiSzCmU0dOnbRbu15+N9Ptj4GqYVK9x6fiqnPU3HjRd1macDq6zyTgHiQLpL9yoc32EeoVwGDrbDiki6b741Mm8gphvypvCfya4BafOK444H1WqeOAr4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728293545; c=relaxed/simple; bh=Q6ow7GUqAzWy9Gsj22wYbT3r7EnlqIllFyUxMnG3duM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=p0nfYmuvx3W98RXy5g0TNQcFsP0R8YvKZKatkijfjcecbxkueAvu6v/YsAOqCNbkBbzJXKJv0ElUldmmMGWXMqtBBfDLjHaJLnJjuHBQ48xkKhBjhJ/44CQX8R/IWm0X7CFs5QnL8vQukpq88nb1xKf5rncGsuMAZ6zptnMz66Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=dolcini.it; spf=pass smtp.mailfrom=dolcini.it; dkim=pass (2048-bit key) header.d=dolcini.it header.i=@dolcini.it header.b=k0cXll59; arc=none smtp.client-ip=217.194.8.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=dolcini.it Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=dolcini.it Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=dolcini.it header.i=@dolcini.it header.b="k0cXll59" Received: from francesco-nb.pivistrello.it (93-49-2-63.ip317.fastwebnet.it [93.49.2.63]) by mail11.truemail.it (Postfix) with ESMTPA id 746EA207B5; Mon, 7 Oct 2024 11:32:19 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dolcini.it; s=default; t=1728293539; bh=8CrAR/TdXELsDDoNgcW8TShChrJK9EkSXn/tY38DJaE=; h=From:To:Subject; b=k0cXll59hbdc0Pa2ajq57jg6Z7wYjeith+qFEhYDpr4DrLenItQ5UjP7NApBcn3/Q /XliHTik6PUDKCZavpAVEoUnFdkYkU8Y9wt0xYlYNvdfXnXu32TOq0M5Xeh57wKd5m wBSeeAjXP84MCkm90RJwGfsFWmzCTEOo3J6j5ZJWCtc3BCdrwHWWGs+lsmL7l9kKHV PNjLTIRvBiqfc8xZ8kCf9psHsSI5wgF6b/m8EkuavZU1EVt+rR8ZcjcRDm6VPjxDSx B95CGBVdDtV4NeCWUo42GpbjHGxMo9W/g7s7Mt9BVW3kLO8iXAISZ193qTDS98nzRe HQO9qbQQGbQHQ== From: Francesco Dolcini To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathias Nyman , Francesco Dolcini Cc: Parth Pancholi , linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/2] dt-bindings: usb: add TUSB73x0 PCIe Date: Mon, 7 Oct 2024 11:32:04 +0200 Message-Id: <20241007093205.27130-2-francesco@dolcini.it> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241007093205.27130-1-francesco@dolcini.it> References: <20241007093205.27130-1-francesco@dolcini.it> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Parth Pancholi Add device tree bindings for TI's TUSB73x0 PCIe-to-USB 3.0 xHCI host controller. The controller supports software configuration through PCIe registers, such as controlling the PWRONx polarity via the USB control register (E0h). Similar generic PCIe-based bindings can be found as qcom,ath11k-pci.yaml as an example. Datasheet: https://www.ti.com/lit/ds/symlink/tusb7320.pdf Signed-off-by: Parth Pancholi Signed-off-by: Francesco Dolcini --- v2: rename property to ti,tusb7320-pwron-active-high and change type to flag --- .../bindings/usb/ti,tusb73x0-pci.yaml | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.y= aml diff --git a/Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml b/D= ocumentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml new file mode 100644 index 000000000000..67a691dc03de --- /dev/null +++ b/Documentation/devicetree/bindings/usb/ti,tusb73x0-pci.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/ti,tusb73x0-pci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TUSB73x0 USB 3.0 xHCI Host Controller (PCIe) + +maintainers: + - Francesco Dolcini + +description: + TUSB73x0 USB 3.0 xHCI Host Controller via PCIe x1 Gen2 interface. + The TUSB7320 supports up to two downstream ports, the TUSB7340 supports = up + to four downstream ports. + +properties: + compatible: + const: pci104C,8241 + + reg: + maxItems: 1 + + ti,tusb7320-pwron-active-high: + $ref: /schemas/types.yaml#/definitions/flag + description: + Configure the polarity of the PWRONx# signals. When this is present,= the PWRONx# + pins are active high and their internal pull-down resistors are disa= bled. + When this is absent, the PWRONx# pins are active low (default) and t= heir internal + pull-down resistors are enabled. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pcie { + #address-cells =3D <3>; + #size-cells =3D <2>; + + pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + + usb@0 { + compatible =3D "pci104C,8241"; + reg =3D <0x10000 0x0 0x0 0x0 0x0>; + + ti,tusb7320-pwron-active-high; + }; + }; + }; --=20 2.39.5 From nobody Wed Nov 27 23:45:56 2024 Received: from mail11.truemail.it (mail11.truemail.it [217.194.8.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5AD9618BC2D; Mon, 7 Oct 2024 09:32:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.194.8.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728293544; cv=none; b=t+PyaEa9iQguhC435t2QuyQ8DN4E9W1q8oSQx201RDi9e8I6PZP+4M/pZckyJXiksxQL1WUsKTZfmCLRTyr37SnzmCwmnOSkioK0AuaE9IFfyrYT6Ssdg9PJf1JslLcBLQTVNHSx1xeszz4929a7A1lb/KOqjch080nyiPdBHG4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728293544; c=relaxed/simple; bh=6u07R4RIZtY2VJTqZEFqHhxEjSJmD31RTu+iKtt9lPw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=cwHKfhV9lBW6wDc5EexSoxILrDbRRtbcOA0t/S6K0Y2RKFNCOSS7Jp0bhNxcCNOE1saO2DUv6IobYqQf8c2rG3DJUaudnMcz8keUYBgzVodH0ye0a6xSBBz8yLKy7CmB/0VBh9ejuaWaR2UOvViNyjMHAbjLZFFfk4vShEYQen4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=dolcini.it; spf=pass smtp.mailfrom=dolcini.it; dkim=pass (2048-bit key) header.d=dolcini.it header.i=@dolcini.it header.b=gudthhh5; arc=none smtp.client-ip=217.194.8.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=dolcini.it Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=dolcini.it Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=dolcini.it header.i=@dolcini.it header.b="gudthhh5" Received: from francesco-nb.pivistrello.it (93-49-2-63.ip317.fastwebnet.it [93.49.2.63]) by mail11.truemail.it (Postfix) with ESMTPA id F3F2E20B33; Mon, 7 Oct 2024 11:32:19 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dolcini.it; s=default; t=1728293540; bh=RrIkTi/ymDfvWUGLsl95l01h7JrOaCRIN8ELPQBuWlk=; h=From:To:Subject; b=gudthhh5D4g0eZlVDnzqAeGJ+hIwQyhrOBt+/q5SEtpzcoAvcfYV6n4wM9yiIdVM0 DARMZKtQSl0shN+eEeSkTG742xASL3maQ90KunG//USDrrgj0+ssEnckMvOfrqU7F5 EcWQUBhwFD7bFrnbYushg5HF9fXZoIgxBDM8yRPBDyyoMytx3ZpkJSjeqDlT28gO2M EEKFIoBW2rJoX3s3ElvbVWq7q4gHhnl2r0VW5nG7h5aIDpv5qBOWVuOfrQiWR5PmTX dbVj4CAy17Esugy31oWO4dpwhjtbzDUBfZYyMhkb6R9BMOFEf6cuZBCIvt31cn7nxg 1/u1C8H0DpT1w== From: Francesco Dolcini To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathias Nyman , Francesco Dolcini Cc: Parth Pancholi , linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/2] USB: xhci: add support for PWRON active high Date: Mon, 7 Oct 2024 11:32:05 +0200 Message-Id: <20241007093205.27130-3-francesco@dolcini.it> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241007093205.27130-1-francesco@dolcini.it> References: <20241007093205.27130-1-francesco@dolcini.it> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Parth Pancholi Some PCIe-to-USB controllers such as TI's TUSB73x0 3.0 xHCI host controller supports controlling the PWRONx polarity via the USB control register (E0h). Add support for device tree property ti,tusb7320-pwron-active-high which indicates PWRONx to be active high and configure the E0h register accordingly. This enables the software control for the TUSB73x0's PWRONx outputs with an inverted polarity from the default configuration which could be used as USB EN signals for the other hubs or devices. Signed-off-by: Parth Pancholi Signed-off-by: Francesco Dolcini --- v2: s/polarity-invert/active-high --- drivers/usb/host/xhci-pci.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c index 91dccd25a551..4bdef01735eb 100644 --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c @@ -641,6 +641,9 @@ int xhci_pci_common_probe(struct pci_dev *dev, const st= ruct pci_device_id *id) =20 dma_set_max_seg_size(&dev->dev, UINT_MAX); =20 + if (device_property_read_bool(&dev->dev, "ti,tusb7320-pwron-active-high")) + pci_clear_and_set_config_dword(dev, 0xE0, 0, 1 << 22); + return 0; =20 put_usb3_hcd: --=20 2.39.5