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Mon, 07 Oct 2024 09:14:14 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 4979EAEQ028317; Mon, 7 Oct 2024 09:14:10 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 422xhksqup-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Mon, 07 Oct 2024 09:14:10 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 4979E94Y028303; Mon, 7 Oct 2024 09:14:09 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-vdadhani-hyd.qualcomm.com [10.213.106.28]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 4979E9l4028291; Mon, 07 Oct 2024 09:14:09 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 4047106) id D86C5500C56; Mon, 7 Oct 2024 14:44:08 +0530 (+0530) From: Viken Dadhaniya To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Cc: quic_msavaliy@quicinc.com, quic_anupkulk@quicinc.com, Viken Dadhaniya Subject: [PATCH v3] arm64: dts: qcom: sa8775p: Populate additional UART DT nodes Date: Mon, 7 Oct 2024 14:44:07 +0530 Message-Id: <20241007091407.13798-1-quic_vdadhani@quicinc.com> X-Mailer: git-send-email 2.17.1 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 6tRD8x6tiQ0Hp24SUtg4-TesQmUxGdjA X-Proofpoint-GUID: 6tRD8x6tiQ0Hp24SUtg4-TesQmUxGdjA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 clxscore=1015 phishscore=0 mlxscore=0 mlxlogscore=999 adultscore=0 lowpriorityscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410070064 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Currently, UART configuration is populated for only a few SEs (Serial Engines) in the sa8775p DTSI file. Since every SE can support the UART protocol, usecase or client should have the flexibility to enable required SE for UART depending on the specific board version. Hence, populate UART configurations for the remaining SEs in the sa8775p SoC. Co-developed-by: Mukesh Kumar Savaliya Signed-off-by: Mukesh Kumar Savaliya Signed-off-by: Viken Dadhaniya --- v2 -> v3: - Modifed commit log as requested by Dmitry. v2 Link: https://lore.kernel.org/lkml/20240911151447.27544-1-quic_vdadhani@= quicinc.com/ v1 -> v2: - Modifed commit log as requested by Krzysztof. - Added co-developed-by tag. v1 Link: https://lore.kernel.org/linux-arm-msm/98e7dc28-4413-4247-bad1-98b5= 29f6d62d@kernel.org/T/ --- --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 231 ++++++++++++++++++++++++++ 1 file changed, 231 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/sa8775p.dtsi index e8dbc8d820a6..0c95a23aecec 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2023, Linaro Limited + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ =20 #include @@ -905,6 +906,21 @@ status =3D "disabled"; }; =20 + uart14: serial@880000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00880000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd SA8775P_CX>; + status =3D "disabled"; + }; + i2c15: i2c@884000 { compatible =3D "qcom,geni-i2c"; reg =3D <0x0 0x884000 0x0 0x4000>; @@ -947,6 +963,21 @@ status =3D "disabled"; }; =20 + uart15: serial@884000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00884000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd SA8775P_CX>; + status =3D "disabled"; + }; + i2c16: i2c@888000 { compatible =3D "qcom,geni-i2c"; reg =3D <0x0 0x888000 0x0 0x4000>; @@ -989,6 +1020,21 @@ status =3D "disabled"; }; =20 + uart16: serial@888000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00888000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd SA8775P_CX>; + status =3D "disabled"; + }; + i2c17: i2c@88c000 { compatible =3D "qcom,geni-i2c"; reg =3D <0x0 0x88c000 0x0 0x4000>; @@ -1088,6 +1134,21 @@ status =3D "disabled"; }; =20 + uart18: serial@890000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00890000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd SA8775P_CX>; + status =3D "disabled"; + }; + i2c19: i2c@894000 { compatible =3D "qcom,geni-i2c"; reg =3D <0x0 0x894000 0x0 0x4000>; @@ -1130,6 +1191,21 @@ status =3D "disabled"; }; =20 + uart19: serial@894000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00894000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd SA8775P_CX>; + status =3D "disabled"; + }; + i2c20: i2c@898000 { compatible =3D "qcom,geni-i2c"; reg =3D <0x0 0x898000 0x0 0x4000>; @@ -1171,6 +1247,22 @@ power-domains =3D <&rpmhpd SA8775P_CX>; status =3D "disabled"; }; + + uart20: serial@898000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00898000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd SA8775P_CX>; + status =3D "disabled"; + }; + }; =20 qupv3_id_0: geniqup@9c0000 { @@ -1227,6 +1319,21 @@ status =3D "disabled"; }; =20 + uart0: serial@980000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x980000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd SA8775P_CX>; + status =3D "disabled"; + }; + i2c1: i2c@984000 { compatible =3D "qcom,geni-i2c"; reg =3D <0x0 0x984000 0x0 0x4000>; @@ -1269,6 +1376,21 @@ status =3D "disabled"; }; =20 + uart1: serial@984000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x984000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd SA8775P_CX>; + status =3D "disabled"; + }; + i2c2: i2c@988000 { compatible =3D "qcom,geni-i2c"; reg =3D <0x0 0x988000 0x0 0x4000>; @@ -1311,6 +1433,21 @@ status =3D "disabled"; }; =20 + uart2: serial@988000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x988000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd SA8775P_CX>; + status =3D "disabled"; + }; + i2c3: i2c@98c000 { compatible =3D "qcom,geni-i2c"; reg =3D <0x0 0x98c000 0x0 0x4000>; @@ -1353,6 +1490,21 @@ status =3D "disabled"; }; =20 + uart3: serial@98c000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x98c000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd SA8775P_CX>; + status =3D "disabled"; + }; + i2c4: i2c@990000 { compatible =3D "qcom,geni-i2c"; reg =3D <0x0 0x990000 0x0 0x4000>; @@ -1395,6 +1547,21 @@ status =3D "disabled"; }; =20 + uart4: serial@990000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x990000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names =3D "se"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", "qup-config"; + power-domains =3D <&rpmhpd SA8775P_CX>; + status =3D "disabled"; + }; + i2c5: i2c@994000 { compatible =3D "qcom,geni-i2c"; reg =3D <0x0 0x994000 0x0 0x4000>; @@ -1507,6 +1674,22 @@ status =3D "disabled"; }; =20 + uart7: serial@a80000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00a80000 0x0 0x4000>; + interrupts =3D ; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interconnect-names =3D "qup-core", "qup-config"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + power-domains =3D <&rpmhpd SA8775P_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + status =3D "disabled"; + }; + i2c8: i2c@a84000 { compatible =3D "qcom,geni-i2c"; reg =3D <0x0 0xa84000 0x0 0x4000>; @@ -1549,6 +1732,22 @@ status =3D "disabled"; }; =20 + uart8: serial@a84000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00a84000 0x0 0x4000>; + interrupts =3D ; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interconnect-names =3D "qup-core", "qup-config"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + power-domains =3D <&rpmhpd SA8775P_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + status =3D "disabled"; + }; + i2c9: i2c@a88000 { compatible =3D "qcom,geni-i2c"; reg =3D <0x0 0xa88000 0x0 0x4000>; @@ -1706,6 +1905,22 @@ status =3D "disabled"; }; =20 + uart11: serial@a90000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00a90000 0x0 0x4000>; + interrupts =3D ; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interconnect-names =3D "qup-core", "qup-config"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + power-domains =3D <&rpmhpd SA8775P_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + status =3D "disabled"; + }; + i2c12: i2c@a94000 { compatible =3D "qcom,geni-i2c"; reg =3D <0x0 0xa94000 0x0 0x4000>; @@ -1838,6 +2053,22 @@ power-domains =3D <&rpmhpd SA8775P_CX>; status =3D "disabled"; }; + + uart21: serial@b80000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00b80000 0x0 0x4000>; + interrupts =3D ; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP3_S0_CLK>; + interconnect-names =3D "qup-core", "qup-config"; + interconnects =3D <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; + power-domains =3D <&rpmhpd SA8775P_CX>; + operating-points-v2 =3D <&qup_opp_table_100mhz>; + status =3D "disabled"; + }; }; =20 rng: rng@10d2000 { --=20 2.17.1