From nobody Thu Nov 28 00:49:32 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95F2E165EE6 for ; Mon, 7 Oct 2024 07:01:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728284475; cv=none; b=t7ljk+LpK+M7smtioUIo6vf9aApBIcpRZCDoW590Nd+xdlVXcISDa7L3AC1v3y1yAcOatAs38xbiSmOnU1GkxeXfVmGGfBboGidJNvHOuhMlgRExH5s5JpRxVVXw+rZOVkcReK/y17x9qsERQ6us15ZaQ9yS0WFAheWJO5ECKF4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728284475; c=relaxed/simple; bh=Xu/5YC0tIp1c5BtObP7maIw5nkcPK3kDQKeOmmP2AXU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=bTS+PgI86/SaNI27kI2LA7fueBTqYveyaWZBvlRq2jW3TPD7LbbsTYwJY//3QRjUba+I33FG/1b6Q3nZRWiT8SpsakjjULNGJGD/X6Fuug7g+FPCzEj6L2A/+o5JvW/kIXx3fly19NxJ7dWWPUA3jqM+Wem2VmJ22e0kmsjF5vA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=l9Rb0/97; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="l9Rb0/97" X-UUID: eb9e370e847911efb66947d174671e26-20241007 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=foPbD0apNGD991d0AC2YtB9IbbEd440LT5kWdpFQixQ=; b=l9Rb0/97cB6ETImZeMt8Hjk32F2oeEDVnSyf2VaJaYgKIC6lN2rtQPyFv7Vysfxc7U7vM4XvZhkxmFtclrCtT6bRu6DalnQGBEoY8Yt/lTYCQyS/PWwDA0oZjgkIMEn0T2v9NhSoG95v6UjnRdgiZHxXMJxpJzvg4AjansPUYtc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.41,REQID:161d319c-7254-4e0b-baf2-6fd5810258a2,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:6dc6a47,CLOUDID:4a1fda64-444a-4b47-a99a-591ade3b04b2,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: eb9e370e847911efb66947d174671e26-20241007 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1295298432; Mon, 07 Oct 2024 15:01:05 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 7 Oct 2024 15:01:03 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 7 Oct 2024 15:01:03 +0800 From: Jason-JH.Lin To: Adam Thiede , Yassine Oudjana , Chun-Kuang Hu , AngeloGioacchino Del Regno CC: Shawn Sung , Alper Nebi Yasak , , , , , "Jason-JH . Lin" , Singo Chang , "Nancy Lin" , Subject: [PATCH v9 1/5] drm/mediatek: ovl: Fix XRGB format breakage for blend_modes unsupported SoCs Date: Mon, 7 Oct 2024 15:00:57 +0800 Message-ID: <20241007070101.23263-2-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20241007070101.23263-1-jason-jh.lin@mediatek.com> References: <20241007070101.23263-1-jason-jh.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--4.144300-8.000000 X-TMASE-MatchedRID: auvC3QTXpfnPl7LciQedTsDORqgKKiYqUAjrAJWsTe+CsBeCv8CM/dS/ hfkVqvWdD2EF2wJcjhei2CV2woUvEFm72EsAF82QA9lly13c/gEK3n1SHen81eO53bHtM9W3QVh QktC6mCo6Av71VIw5dIAy6p60ZV62fJ5/bZ6npdiujVRFkkVsm0KRNS3nURDdYX20ZXgGme8uSE 1WVaGxAVzM8RLhWMtt1IGf4vNKEEL3ugAbtT6cRkv95ivUjpgUh8kI3MxsG5XZAuBXdw+XWo6H7 DI0GsVcMmI24qiENwrMpIbcl3IoA+q1XYAYw09q9Z1yWryVTWo= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--4.144300-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 692070F7659E55B9377DB75BF4DEBA22298D9C1AB68C9BAD0ADB1DCB47CD31722000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If the constant alpha always enable, the SoCs that is not supported the ignore pixel alpha bit will still use constant alpha. That will break the original constant alpha setting of XRGB foramt for blend_modes unsupported SoCs, such as MT8173. Note that ignore pixel alpha bit is suppored if the SoC support the blend_modes. Make the constatnt alpha only enable when having a vliad blend_mode or setting the has_alpha to fix the downgrade issue. Fixes: bc46eb5d5d77 ("drm/mediatek: Support DRM plane alpha in OVL") Signed-off-by: Jason-JH.Lin Reviewed-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 89b439dcf3a6..8453a72f9e59 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -473,8 +473,14 @@ void mtk_ovl_layer_config(struct device *dev, unsigned= int idx, =20 con =3D ovl_fmt_convert(ovl, fmt, blend_mode); if (state->base.fb) { - con |=3D OVL_CON_AEN; con |=3D state->base.alpha & OVL_CON_ALPHA; + + /* + * For blend_modes supported SoCs, always enable constant alpha. + * For blend_modes unsupported SoCs, enable constant alpha when has_alph= a is set. + */ + if (blend_mode || state->base.fb->format->has_alpha) + con |=3D OVL_CON_AEN; } =20 /* CONST_BLD must be enabled for XRGB formats although the alpha channel --=20 2.43.0 From nobody Thu Nov 28 00:49:32 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87FAE17085A for ; Mon, 7 Oct 2024 07:01:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728284476; cv=none; b=jUtS/KWDJkDB2iZWdi0hgKaaON1iBoq58by07hy3y792xV9rzM1FHbhGkEfZrQs6lFTlDMppD0mpCn4jQaPq6JO9+l7otGdkJiO3vbQ7q1IAqhPEHkhWYNgUeLpQwOjrTAjLPD6Ut+B+maJRbKWkIBVwrnzScvKPxz2eI92OUhQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728284476; c=relaxed/simple; bh=LZQFc3zVyeXc6PdfCkTaSTT7F+52DMTiGIfqbP/zrvo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dXdGqrWCwN8oYycmpMImvtndrMVaYBSICbOPatSshW+JXRoFUhWFlZoh8GN+5i17lDWFH3f//9GErO3HXuYzRnrHiFIHZd3z518Mpv6gKGD7y3R2Ol4Ho+TevB/xOi3nsPjXbBQC/8UFJqE1JFNGDpIY5do4WNCq97BhucnzyoY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=kOpMlkOf; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="kOpMlkOf" X-UUID: eb4711fe847911efb66947d174671e26-20241007 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=mikTk70CrNGupwfA96mysETqIWVDq8bAGh/Y0KQDRqk=; b=kOpMlkOfjRZ52uzLNF3HmAAaqGiEAO1ytcGaDLYix69DaTaa5BPM0j66LSIa/touncT1qCVa0zhjeD14u1cFIyonOa6wDNRk9YeeulpccXrY8WDkC6fld/UxVsM11W7+ZmmgRXg9QYcVmBzl2qk11HFExQBh14fjOLTd1rpPDFQ=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.41,REQID:3af594bf-a24c-4d57-a21d-bab65e585614,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:6dc6a47,CLOUDID:4c1fda64-444a-4b47-a99a-591ade3b04b2,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: eb4711fe847911efb66947d174671e26-20241007 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 480990772; Mon, 07 Oct 2024 15:01:04 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by MTKMBS09N1.mediatek.inc (172.21.101.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 7 Oct 2024 15:01:03 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 7 Oct 2024 15:01:03 +0800 From: Jason-JH.Lin To: Adam Thiede , Yassine Oudjana , Chun-Kuang Hu , AngeloGioacchino Del Regno CC: Shawn Sung , Alper Nebi Yasak , , , , , "Jason-JH . Lin" , Singo Chang , Nancy Lin , Subject: [PATCH v9 2/5] drm/mediatek: ovl: Refine ignore_pixel_alpha comment and placement Date: Mon, 7 Oct 2024 15:00:58 +0800 Message-ID: <20241007070101.23263-3-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20241007070101.23263-1-jason-jh.lin@mediatek.com> References: <20241007070101.23263-1-jason-jh.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Refine the comment for ignore_pixel_alpha flag and move it to if (state->fb) statement to make it less conditional. Signed-off-by: Jason-JH.Lin Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu Tested-by: Chen-Yu Tsai --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 8453a72f9e59..ddc826c42653 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -481,16 +481,16 @@ void mtk_ovl_layer_config(struct device *dev, unsigne= d int idx, */ if (blend_mode || state->base.fb->format->has_alpha) con |=3D OVL_CON_AEN; - } =20 - /* CONST_BLD must be enabled for XRGB formats although the alpha channel - * can be ignored, or OVL will still read the value from memory. - * For RGB888 related formats, whether CONST_BLD is enabled or not won't - * affect the result. Therefore we use !has_alpha as the condition. - */ - if ((state->base.fb && !state->base.fb->format->has_alpha) || - blend_mode =3D=3D DRM_MODE_BLEND_PIXEL_NONE) - ignore_pixel_alpha =3D OVL_CONST_BLEND; + /* + * Although the alpha channel can be ignored, CONST_BLD must be enabled + * for XRGB format, otherwise OVL will still read the value from memory. + * For RGB888 related formats, whether CONST_BLD is enabled or not won't + * affect the result. Therefore we use !has_alpha as the condition. + */ + if (blend_mode =3D=3D DRM_MODE_BLEND_PIXEL_NONE || !state->base.fb->form= at->has_alpha) + ignore_pixel_alpha =3D OVL_CONST_BLEND; + } =20 if (pending->rotation & DRM_MODE_REFLECT_Y) { con |=3D OVL_CON_VIRT_FLIP; --=20 2.43.0 From nobody Thu Nov 28 00:49:32 2024 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E9AC8248D for ; Mon, 7 Oct 2024 07:01:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728284473; cv=none; b=nhpZ17bEQXNOT3+rWQS2P6jLMvyAfttxmMfJEB815XGzAH5upV6MX7vPlPc7UPVtQjEpHF8HKF4nvNWgLTtv+jiazi6rRGHHDmA8fgO0E3PzzsQJtLkqLjt2OqXo5dUxeZiPNn9kG9LWcWV6xO/lsAAPfD1v0mEekxWEsmkGy7M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728284473; c=relaxed/simple; bh=8UiXKxrz3mIBTIEBuV8LG0HYfDFBmYBRSXirlftXym0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=jorotbvrpzpbvzKexZ09sibmN+MwwN8P6b54YzsYQ1RpyzafeDVq4m4gx0uRjUwteJ/DdFOwc8BHbY+7Ibg2wQubp5gAagAxg+Ppzn35RHar70HQ+kNE6XjidCphBI616JlskhBupSSUsQSMDrUU6YpRK4YWq0mKpfrgQGw4kzk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=mab49E4Y; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="mab49E4Y" X-UUID: ebc68a10847911efb66947d174671e26-20241007 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=hFEgSzsR19g/gZoKiElaar5KRFRdu2C3mWi6oy3D+PE=; b=mab49E4YGOzqQw4vGf8hHfLHEE3LyPoRwE7ol3zcZXPNL4/i9x3WkN4Q2jly21062CtyfPjkwpnOYgq64C2VBYde3FSIpv/Tq9FtxopN8rs4Sgv7p74a0o7NgatVzg2FEhquIuQMG7gfaGdEfWd8s2XkVOzNB962Dpi3AA7C10c=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.41,REQID:ea173f58-e331-49c5-939d-c11c5d95bd6d,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:6dc6a47,CLOUDID:da5adc40-8751-41b2-98dd-475503d45150,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES :1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_ULN,TF_CID_SPAM_SNR X-UUID: ebc68a10847911efb66947d174671e26-20241007 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1422908548; Mon, 07 Oct 2024 15:01:05 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 7 Oct 2024 15:01:03 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 7 Oct 2024 15:01:03 +0800 From: Jason-JH.Lin To: Adam Thiede , Yassine Oudjana , Chun-Kuang Hu , AngeloGioacchino Del Regno CC: Shawn Sung , Alper Nebi Yasak , , , , , "Jason-JH . Lin" , Singo Chang , "Nancy Lin" , Subject: [PATCH v9 3/5] drm/mediatek: ovl: Remove the color format comment for ovl_fmt_convert() Date: Mon, 7 Oct 2024 15:00:59 +0800 Message-ID: <20241007070101.23263-4-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20241007070101.23263-1-jason-jh.lin@mediatek.com> References: <20241007070101.23263-1-jason-jh.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--3.679400-8.000000 X-TMASE-MatchedRID: JqvUv0YB5EcxgGuH6sDPS8u00lnG8+PW4+ZcrqvCDkFcKZwALwMGsyc/ xZYu98DINdSJDUY9JRESqo3ZUfrHh25/NyTKlG694pdq9sdj8LVaNaxZBRbNWi8zQZ2rR/Opl12 4J4jWEmtRY9f7h2Xyki1nQIsbRW6GSJvHZYIIxMieAiCmPx4NwBnUJ0Ek6yhjxEHRux+uk8ifEz J5hPndGba+xTwXsc5qqeC1Zf5kfSTM53A5+Z0f0qNJf0+RLn+96jfpBdJfd4N749KQ5eyZEpQEQ Sv/NPqP4gzb/+CBJ6+IyRJlDbkVyXmVKZusLp922v9OjYWA2uMMswg45VMfPadst5iAforfVlxr 1FJij9s= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--3.679400-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 0254FD193E5AEA77617F13376B729042DCEDD557A5F76DE370D29A73D78063B52000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since we changed MACROs to be consistent with DRM input color format naming, the comment for ovl_fmt_conver() is no longer needed. Fixes: 9f428b95ac89 ("drm/mediatek: Add new color format MACROs in OVL") Signed-off-by: Jason-JH.Lin Reviewed-by: CK Hu Tested-by: Chen-Yu Tsai --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index ddc826c42653..22f17ebfd8b3 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -389,11 +389,6 @@ void mtk_ovl_layer_off(struct device *dev, unsigned in= t idx, static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int= fmt, unsigned int blend_mode) { - /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX" - * is defined in mediatek HW data sheet. - * The alphabet order in XXX is no relation to data - * arrangement in memory. - */ switch (fmt) { default: case DRM_FORMAT_RGB565: --=20 2.43.0 From nobody Thu Nov 28 00:49:32 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D423C13792B for ; Mon, 7 Oct 2024 07:01:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728284472; cv=none; b=PwBvAKMC74+igMSyGY7uEjdd78a+ag+FrRPHHZWXKHR4ZJZKDZk/8EmeEZX2lXfQuVObL7whS2D6oJ6h9ud7n2AXXBcF3dkdQN7zJoTN/Eb2HM3lzHn4EZN//hiqtvgRc+vXXh7+VNdbL5C6XdzEvFn1baQW1uetu9m0Co50NbY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728284472; c=relaxed/simple; bh=pXk0xFUkubDkvmgAt9lcDuiHXKyUdg+0hoxO0XYfAaQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=to9aqKvk3QDyGwi4+vGlMoDSpd2KS/zfZ8wsxgucFadcEepLZMpTblcEEj5Nl5oeCXtRAO2blrXi+xGbvVrbrV5nb0p9MVlYFid32SHmSGg+vwKOCAym5lx43mYmpXg3bwdxZhTb15mJvRY8kR7Tv4jsAYML9ME/P0Jzd9hxMIs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=JNUcQqyG; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="JNUcQqyG" X-UUID: eb4b8b76847911ef8b96093e013ec31c-20241007 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=lqUh6reBenVOo2PK0q3FWwTZxg0Z7SkzFkPrsnQOk9Q=; b=JNUcQqyGoiwHp8DP3peDT0wQmJ4N4CPVHW5GrnKmz/AS2UImKsUM3MYUw/2hDL8aGXaU5tm/AuVDCJDU/fOJqO8GH3eJSDButxz/f0ITN3/kVxtxmHdeNJEDb2xSPpLiRE54w77gcLHcvuRGd9KTb6AgcCXSfK3sQtX5m6y//Hw=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.41,REQID:bd3b73c1-0c1c-43ec-b4c3-006b2d804561,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:6dc6a47,CLOUDID:351fda64-444a-4b47-a99a-591ade3b04b2,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: eb4b8b76847911ef8b96093e013ec31c-20241007 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 2132492788; Mon, 07 Oct 2024 15:01:04 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 7 Oct 2024 15:01:03 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 7 Oct 2024 15:01:03 +0800 From: Jason-JH.Lin To: Adam Thiede , Yassine Oudjana , Chun-Kuang Hu , AngeloGioacchino Del Regno CC: Shawn Sung , Alper Nebi Yasak , , , , , "Jason-JH . Lin" , Singo Chang , "Nancy Lin" , Subject: [PATCH v9 4/5] drm/mediatek: ovl: Add blend_modes to driver data Date: Mon, 7 Oct 2024 15:01:00 +0800 Message-ID: <20241007070101.23263-5-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20241007070101.23263-1-jason-jh.lin@mediatek.com> References: <20241007070101.23263-1-jason-jh.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--11.742200-8.000000 X-TMASE-MatchedRID: PIIqySEg3TIzP1+hKLmUcMu00lnG8+PWIaLR+2xKRDLb6Y+fnTZULz94 HX24gqtC170RpEE9+Ch41slfouzT+EIjaJSsaV6q9Jn/ZrGuc8HSL+EVfOJR07FRmrhHzmfvR+m RDHa7QqxsMMavja2AExKqjdlR+seHLVayL7k7olyQOktEo73GFArefVId6fzVCqIJhrrDy28j7P LDbldk2nqqxcrRKidevws8hDIFFaPGWQHDiYaPQNF8NCC76P7lS8T7akvAZuebKItl61J/yZ+in TK0bC9eKrauXd3MZDVrKcxhGNhTPi2fcpKjyjtXPRyw9iLsE0+tmysOooI43i70ukIx9ljm X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--11.742200-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 099BE6B5E68196C26FAC094FDF435403E79DD7BE1F77CD0C0344D5621E5954722000:8 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" OVL_CON_CLRFMT_MAN is a configuration for extending color format settings of DISP_REG_OVL_CON(n). It will change some of the original color format settings. Take the settings of (3 << 12) for example. - If OVL_CON_CLRFMT_MAN =3D 0 means OVL_CON_CLRFMT_RGBA8888. - If OVL_CON_CLRFMT_MAN =3D 1 means OVL_CON_CLRFMT_PARGB8888. Since previous SoCs did not support OVL_CON_CLRFMT_MAN, this means that the SoC does not support the premultiplied color format. It will break the original color format setting of MT8173. Therefore, the blend_modes is added to the driver data and then mtk_ovl_fmt_convert() will check the blend_modes to see if premultiplied supported in current platform. If it is not supported, use coverage mode to set it to the supported color formats to solve the degradation problem. Fixes: a3f7f7ef4bfe ("drm/mediatek: Support "Pre-multiplied" blending in OV= L") Signed-off-by: Jason-JH.Lin Reviewed-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 34 ++++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 22f17ebfd8b3..41874dc9d933 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -146,6 +146,7 @@ struct mtk_disp_ovl_data { bool fmt_rgb565_is_0; bool smi_id_en; bool supports_afbc; + const u32 blend_modes; const u32 *formats; size_t num_formats; bool supports_clrfmt_ext; @@ -386,9 +387,27 @@ void mtk_ovl_layer_off(struct device *dev, unsigned in= t idx, DISP_REG_OVL_RDMA_CTRL(idx)); } =20 -static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int= fmt, - unsigned int blend_mode) +static unsigned int mtk_ovl_fmt_convert(struct mtk_disp_ovl *ovl, + struct mtk_plane_state *state) { + unsigned int fmt =3D state->pending.format; + unsigned int blend_mode =3D DRM_MODE_BLEND_COVERAGE; + + /* + * For the platforms where OVL_CON_CLRFMT_MAN is defined in the hardware = data sheet + * and supports premultiplied color formats, such as OVL_CON_CLRFMT_PARGB= 8888. + * + * Check blend_modes in the driver data to see if premultiplied mode is s= upported. + * If not, use coverage mode instead to set it to the supported color for= mats. + * + * Current DRM assumption is that alpha is default premultiplied, so the = bitmask of + * blend_modes must include BIT(DRM_MODE_BLEND_PREMULTI). Otherwise, mtk_= plane_init() + * will get an error return from drm_plane_create_blend_mode_property() a= nd + * state->base.pixel_blend_mode should not be used. + */ + if (ovl->data->blend_modes & BIT(DRM_MODE_BLEND_PREMULTI)) + blend_mode =3D state->base.pixel_blend_mode; + switch (fmt) { default: case DRM_FORMAT_RGB565: @@ -466,7 +485,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned = int idx, return; } =20 - con =3D ovl_fmt_convert(ovl, fmt, blend_mode); + con =3D mtk_ovl_fmt_convert(ovl, state); if (state->base.fb) { con |=3D state->base.alpha & OVL_CON_ALPHA; =20 @@ -664,6 +683,9 @@ static const struct mtk_disp_ovl_data mt8192_ovl_driver= _data =3D { .layer_nr =3D 4, .fmt_rgb565_is_0 =3D true, .smi_id_en =3D true, + .blend_modes =3D BIT(DRM_MODE_BLEND_PREMULTI) | + BIT(DRM_MODE_BLEND_COVERAGE) | + BIT(DRM_MODE_BLEND_PIXEL_NONE), .formats =3D mt8173_formats, .num_formats =3D ARRAY_SIZE(mt8173_formats), }; @@ -674,6 +696,9 @@ static const struct mtk_disp_ovl_data mt8192_ovl_2l_dri= ver_data =3D { .layer_nr =3D 2, .fmt_rgb565_is_0 =3D true, .smi_id_en =3D true, + .blend_modes =3D BIT(DRM_MODE_BLEND_PREMULTI) | + BIT(DRM_MODE_BLEND_COVERAGE) | + BIT(DRM_MODE_BLEND_PIXEL_NONE), .formats =3D mt8173_formats, .num_formats =3D ARRAY_SIZE(mt8173_formats), }; @@ -685,6 +710,9 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver= _data =3D { .fmt_rgb565_is_0 =3D true, .smi_id_en =3D true, .supports_afbc =3D true, + .blend_modes =3D BIT(DRM_MODE_BLEND_PREMULTI) | + BIT(DRM_MODE_BLEND_COVERAGE) | + BIT(DRM_MODE_BLEND_PIXEL_NONE), .formats =3D mt8195_formats, .num_formats =3D ARRAY_SIZE(mt8195_formats), .supports_clrfmt_ext =3D true, --=20 2.43.0 From nobody Thu Nov 28 00:49:32 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BBC94139CF2 for ; Mon, 7 Oct 2024 07:01:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728284473; cv=none; b=c6kQJhnHP+aoFXLVUmZtSYJX0RJ7mBwe1KVuXunmBFfZNCtGnZIj7TDJdhELGVFT669MIA/H8XemvU89tD4jrNxwNzG8rz3vuNurVYbhnGEKI2P89vbBST4oJtVa5bmLmAkmRQJzCQxuQqBNzU1VAOvBukAVd7JuIwqE6pdIcTg= ARC-Message-Signature: i=1; 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Mon, 07 Oct 2024 15:01:05 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 7 Oct 2024 15:01:03 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 7 Oct 2024 15:01:03 +0800 From: Jason-JH.Lin To: Adam Thiede , Yassine Oudjana , Chun-Kuang Hu , AngeloGioacchino Del Regno CC: Shawn Sung , Alper Nebi Yasak , , , , , "Jason-JH . Lin" , Singo Chang , Nancy Lin , Subject: [PATCH v9 5/5] drm/mediatek: Add blend_modes to mtk_plane_init() for different SoCs Date: Mon, 7 Oct 2024 15:01:01 +0800 Message-ID: <20241007070101.23263-6-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20241007070101.23263-1-jason-jh.lin@mediatek.com> References: <20241007070101.23263-1-jason-jh.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since some SoCs support premultiplied pixel formats but some do not, the blend_modes parameter is added to mtk_plane_init(), which is obtained from the mtk_ddp_comp_get_blend_modes function implemented in different blending supported components. The blending supported components can use driver data to set the blend mode capabilities for different SoCs. Signed-off-by: Jason-JH.Lin Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu Tested-by: Chen-Yu Tsai --- drivers/gpu/drm/mediatek/mtk_crtc.c | 1 + drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 2 ++ drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 10 ++++++++++ drivers/gpu/drm/mediatek/mtk_disp_drv.h | 2 ++ drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 7 +++++++ drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 7 +++++++ drivers/gpu/drm/mediatek/mtk_ethdr.c | 7 +++++++ drivers/gpu/drm/mediatek/mtk_ethdr.h | 1 + drivers/gpu/drm/mediatek/mtk_plane.c | 15 +++++++-------- drivers/gpu/drm/mediatek/mtk_plane.h | 4 ++-- 10 files changed, 46 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek= /mtk_crtc.c index 175b00e5a253..b65f196f2015 100644 --- a/drivers/gpu/drm/mediatek/mtk_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_crtc.c @@ -913,6 +913,7 @@ static int mtk_crtc_init_comp_planes(struct drm_device = *drm_dev, BIT(pipe), mtk_crtc_plane_type(mtk_crtc->layer_nr, num_planes), mtk_ddp_comp_supported_rotations(comp), + mtk_ddp_comp_get_blend_modes(comp), mtk_ddp_comp_get_formats(comp), mtk_ddp_comp_get_num_formats(comp), i); if (ret) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.c index be66d94be361..edc6417639e6 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -363,6 +363,7 @@ static const struct mtk_ddp_comp_funcs ddp_ovl =3D { .layer_config =3D mtk_ovl_layer_config, .bgclr_in_on =3D mtk_ovl_bgclr_in_on, .bgclr_in_off =3D mtk_ovl_bgclr_in_off, + .get_blend_modes =3D mtk_ovl_get_blend_modes, .get_formats =3D mtk_ovl_get_formats, .get_num_formats =3D mtk_ovl_get_num_formats, }; @@ -416,6 +417,7 @@ static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = =3D { .disconnect =3D mtk_ovl_adaptor_disconnect, .add =3D mtk_ovl_adaptor_add_comp, .remove =3D mtk_ovl_adaptor_remove_comp, + .get_blend_modes =3D mtk_ovl_adaptor_get_blend_modes, .get_formats =3D mtk_ovl_adaptor_get_formats, .get_num_formats =3D mtk_ovl_adaptor_get_num_formats, .mode_valid =3D mtk_ovl_adaptor_mode_valid, diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.h index ecf6dc283cd7..39720b27f4e9 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h @@ -80,6 +80,7 @@ struct mtk_ddp_comp_funcs { void (*ctm_set)(struct device *dev, struct drm_crtc_state *state); struct device * (*dma_dev_get)(struct device *dev); + u32 (*get_blend_modes)(struct device *dev); const u32 *(*get_formats)(struct device *dev); size_t (*get_num_formats)(struct device *dev); void (*connect)(struct device *dev, struct device *mmsys_dev, unsigned in= t next); @@ -266,6 +267,15 @@ static inline struct device *mtk_ddp_comp_dma_dev_get(= struct mtk_ddp_comp *comp) return comp->dev; } =20 +static inline +u32 mtk_ddp_comp_get_blend_modes(struct mtk_ddp_comp *comp) +{ + if (comp->funcs && comp->funcs->get_blend_modes) + return comp->funcs->get_blend_modes(comp->dev); + + return 0; +} + static inline const u32 *mtk_ddp_comp_get_formats(struct mtk_ddp_comp *comp) { diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/medi= atek/mtk_disp_drv.h index 082ac18fe04a..04154db9085c 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -103,6 +103,7 @@ void mtk_ovl_register_vblank_cb(struct device *dev, void mtk_ovl_unregister_vblank_cb(struct device *dev); void mtk_ovl_enable_vblank(struct device *dev); void mtk_ovl_disable_vblank(struct device *dev); +u32 mtk_ovl_get_blend_modes(struct device *dev); const u32 *mtk_ovl_get_formats(struct device *dev); size_t mtk_ovl_get_num_formats(struct device *dev); =20 @@ -131,6 +132,7 @@ void mtk_ovl_adaptor_start(struct device *dev); void mtk_ovl_adaptor_stop(struct device *dev); unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev); struct device *mtk_ovl_adaptor_dma_dev_get(struct device *dev); +u32 mtk_ovl_adaptor_get_blend_modes(struct device *dev); const u32 *mtk_ovl_adaptor_get_formats(struct device *dev); size_t mtk_ovl_adaptor_get_num_formats(struct device *dev); enum drm_mode_status mtk_ovl_adaptor_mode_valid(struct device *dev, diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 41874dc9d933..f747b91e586f 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -215,6 +215,13 @@ void mtk_ovl_disable_vblank(struct device *dev) writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN); } =20 +u32 mtk_ovl_get_blend_modes(struct device *dev) +{ + struct mtk_disp_ovl *ovl =3D dev_get_drvdata(dev); + + return ovl->data->blend_modes; +} + const u32 *mtk_ovl_get_formats(struct device *dev) { struct mtk_disp_ovl *ovl =3D dev_get_drvdata(dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index c6768210b08b..bf2546c4681a 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -400,6 +400,13 @@ void mtk_ovl_adaptor_disable_vblank(struct device *dev) mtk_ethdr_disable_vblank(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0= ]); } =20 +u32 mtk_ovl_adaptor_get_blend_modes(struct device *dev) +{ + struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); + + return mtk_ethdr_get_blend_modes(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTO= R_ETHDR0]); +} + const u32 *mtk_ovl_adaptor_get_formats(struct device *dev) { struct mtk_disp_ovl_adaptor *ovl_adaptor =3D dev_get_drvdata(dev); diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediate= k/mtk_ethdr.c index d1d9cf8b10e1..0f22e7d337cb 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -145,6 +145,13 @@ static irqreturn_t mtk_ethdr_irq_handler(int irq, void= *dev_id) return IRQ_HANDLED; } =20 +u32 mtk_ethdr_get_blend_modes(struct device *dev) +{ + return BIT(DRM_MODE_BLEND_PREMULTI) | + BIT(DRM_MODE_BLEND_COVERAGE) | + BIT(DRM_MODE_BLEND_PIXEL_NONE); +} + void mtk_ethdr_layer_config(struct device *dev, unsigned int idx, struct mtk_plane_state *state, struct cmdq_pkt *cmdq_pkt) diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.h b/drivers/gpu/drm/mediate= k/mtk_ethdr.h index 81af9edea3f7..a72aeee46829 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.h +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.h @@ -13,6 +13,7 @@ void mtk_ethdr_clk_disable(struct device *dev); void mtk_ethdr_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); +u32 mtk_ethdr_get_blend_modes(struct device *dev); void mtk_ethdr_layer_config(struct device *dev, unsigned int idx, struct mtk_plane_state *state, struct cmdq_pkt *cmdq_pkt); diff --git a/drivers/gpu/drm/mediatek/mtk_plane.c b/drivers/gpu/drm/mediate= k/mtk_plane.c index 7d2cb4e0fafa..8a48b3b0a956 100644 --- a/drivers/gpu/drm/mediatek/mtk_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_plane.c @@ -320,8 +320,8 @@ static const struct drm_plane_helper_funcs mtk_plane_he= lper_funcs =3D { =20 int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane, unsigned long possible_crtcs, enum drm_plane_type type, - unsigned int supported_rotations, const u32 *formats, - size_t num_formats, unsigned int plane_idx) + unsigned int supported_rotations, const u32 blend_modes, + const u32 *formats, size_t num_formats, unsigned int plane_idx) { int err; =20 @@ -366,12 +366,11 @@ int mtk_plane_init(struct drm_device *dev, struct drm= _plane *plane, if (err) DRM_ERROR("failed to create property: alpha\n"); =20 - err =3D drm_plane_create_blend_mode_property(plane, - BIT(DRM_MODE_BLEND_PREMULTI) | - BIT(DRM_MODE_BLEND_COVERAGE) | - BIT(DRM_MODE_BLEND_PIXEL_NONE)); - if (err) - DRM_ERROR("failed to create property: blend_mode\n"); + if (blend_modes) { + err =3D drm_plane_create_blend_mode_property(plane, blend_modes); + if (err) + DRM_ERROR("failed to create property: blend_mode\n"); + } =20 drm_plane_helper_add(plane, &mtk_plane_helper_funcs); =20 diff --git a/drivers/gpu/drm/mediatek/mtk_plane.h b/drivers/gpu/drm/mediate= k/mtk_plane.h index 5b177eac67b7..3b13b89989c7 100644 --- a/drivers/gpu/drm/mediatek/mtk_plane.h +++ b/drivers/gpu/drm/mediatek/mtk_plane.h @@ -48,6 +48,6 @@ to_mtk_plane_state(struct drm_plane_state *state) =20 int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane, unsigned long possible_crtcs, enum drm_plane_type type, - unsigned int supported_rotations, const u32 *formats, - size_t num_formats, unsigned int plane_idx); + unsigned int supported_rotations, const u32 blend_modes, + const u32 *formats, size_t num_formats, unsigned int plane_idx); #endif --=20 2.43.0