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Signed-off-by: Sibi Sankar --- v3: * Restructure the bindings to mimic IMX [Christian] .../bindings/firmware/arm,scmi.yaml | 1 + .../bindings/firmware/qcom,scmi-memlat.yaml | 246 ++++++++++++++++++ .../dt-bindings/firmware/qcom,scmi-memlat.h | 22 ++ 3 files changed, 269 insertions(+) create mode 100644 Documentation/devicetree/bindings/firmware/qcom,scmi-me= mlat.yaml create mode 100644 include/dt-bindings/firmware/qcom,scmi-memlat.h diff --git a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml b/Doc= umentation/devicetree/bindings/firmware/arm,scmi.yaml index 54d7d11bfed4..1d405f429168 100644 --- a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml +++ b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml @@ -24,6 +24,7 @@ description: | =20 anyOf: - $ref: /schemas/firmware/nxp,imx95-scmi.yaml + - $ref: /schemas/firmware/qcom,scmi-memlat.yaml =20 properties: $nodename: diff --git a/Documentation/devicetree/bindings/firmware/qcom,scmi-memlat.ya= ml b/Documentation/devicetree/bindings/firmware/qcom,scmi-memlat.yaml new file mode 100644 index 000000000000..0e8ea6dacd6a --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/qcom,scmi-memlat.yaml @@ -0,0 +1,246 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/qcom,scmi-memlat.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SCMI Memory Bus nodes + +maintainers: + - Sibi Sankar + +description: + This binding describes the various memory buses that can be monitored an= d scaled + by memory latency governor running on the CPU Control Processor (SCMI co= ntroller). + +properties: + protocol@80: + $ref: '/schemas/firmware/arm,scmi.yaml#/$defs/protocol-node' + unevaluatedProperties: false + + properties: + reg: + const: 0x80 + + patternProperties: + '^memory-[0-9]$': + type: object + unevaluatedProperties: false + description: + The list of all memory buses that can be monitored and scaled by= the + memory latency governor running on the SCMI controller. + + properties: + qcom,memory-type: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + description: | + Memory Bus Identifier + 0 =3D QCOM_MEM_TYPE_DDR + 1 =3D QCOM_MEM_TYPE_LLCC + 2 =3D QCOM_MEM_TYPE_DDR_QOS + + freq-table-hz: + items: + items: + - description: Minimum frequency of the memory bus in Hz + - description: Maximum frequency of the memory bus in Hz + + patternProperties: + '^monitor-[0-9]$': + type: object + unevaluatedProperties: false + description: + The list of all monitors detecting the memory latency bound = workloads using + various counters. + + properties: + qcom,compute-type: + description: + Monitors of type compute perform bus dvfs based on a rud= imentary CPU + frequency to memory frequency map. + type: boolean + + qcom,ipm-ceil: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Monitors having this property perform bus dvfs based on = the same + rudimentary table but the scaling is performed only if t= he calculated + IPM (Instruction Per Misses) exceeds the given ceiling. + + cpus: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Should be a list of phandles to CPU nodes (as described = in + Documentation/devicetree/bindings/arm/cpus.yaml). + + operating-points-v2: true + opp-table: + type: object + + required: + - cpus + - operating-points-v2 + + oneOf: + - required: [ 'qcom,compute-type' ] + - required: [ 'qcom,ipm-ceil' ] + + required: + - qcom,memory-type + - freq-table-hz + +additionalProperties: true + +examples: + - | + #include + + firmware { + scmi { + compatible =3D "arm,scmi"; + mboxes =3D <&cpucp_mbox 0>, <&cpucp_mbox 2>; + mbox-names =3D "tx", "rx"; + shmem =3D <&cpu_scp_lpri0>, <&cpu_scp_lpri1>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + protocol@80 { + reg =3D <0x80>; + + memory-0 { + qcom,memory-type =3D ; + freq-table-hz =3D /bits/ 64 <200000000 4224000000>; + + monitor-0 { + qcom,ipm-ceil =3D <20000000>; + cpus =3D <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5 &CPU= 6 &CPU7 + &CPU8 &CPU9 &CPU10 &CPU11>; + operating-points-v2 =3D <&memory0_monitor0_opp_tab= le>; + + memory0_monitor0_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-999000000 { + opp-hz =3D /bits/ 64 <999000000 547000000>; + }; + + opp-1440000000 { + opp-hz =3D /bits/ 64 <1440000000 768000000= >; + }; + + opp-1671000000 { + opp-hz =3D /bits/ 64 <1671000000 155500000= 0>; + }; + + opp-2189000000 { + opp-hz =3D /bits/ 64 <2189000000 209200000= 0>; + }; + + opp-2516000000 { + opp-hz =3D /bits/ 64 <2516000000 318700000= 0>; + }; + + opp-3860000000 { + opp-hz =3D /bits/ 64 <3860000000 422400000= 0>; + }; + }; + }; + + monitor-1 { + qcom,compute-type; + cpus =3D <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5 &CPU= 6 &CPU7 + &CPU8 &CPU9 &CPU10 &CPU11>; + operating-points-v2 =3D <&memory0_monitor1_opp_tab= le>; + + memory0_monitor1_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-1440000000 { + opp-hz =3D /bits/ 64 <1440000000 20000= 0000>; + }; + + opp-2189000000 { + opp-hz =3D /bits/ 64 <2189000000 76800= 0000>; + }; + + opp-2516000000 { + opp-hz =3D /bits/ 64 <2516000000 15550= 00000>; + }; + + opp-3860000000 { + opp-hz =3D /bits/ 64 <3860000000 42240= 00000>; + }; + }; + }; + }; + + memory-1 { + qcom,memory-type =3D ; + freq-table-hz =3D /bits/ 64 <300000000 1067000000>; + + monitor-0 { + qcom,ipm-ceil =3D <20000000>; + cpus =3D <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5 &CPU= 6 &CPU7 + &CPU8 &CPU9 &CPU10 &CPU11>; + operating-points-v2 =3D <&memory1_monitor0_opp_tab= le>; + + memory1_monitor0_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-999000000 { + opp-hz =3D /bits/ 64 <999000000 300000000>; + }; + + opp-1440000000 { + opp-hz =3D /bits/ 64 <1440000000 466000000= >; + }; + + opp-1671000000 { + opp-hz =3D /bits/ 64 <1671000000 600000000= >; + }; + + opp-2189000000 { + opp-hz =3D /bits/ 64 <2189000000 806000000= >; + }; + + opp-2516000000 { + opp-hz =3D /bits/ 64 <2516000000 933000000= >; + }; + + opp-3860000000 { + opp-hz =3D /bits/ 64 <3860000000 106600000= 0>; + }; + }; + }; + }; + + memory-2 { + qcom,memory-type =3D ; + freq-table-hz =3D /bits/ 64 ; + + monitor-0 { + qcom,ipm-ceil =3D <20000000>; + cpus =3D <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5 &CPU= 6 &CPU7 + &CPU8 &CPU9 &CPU10 &CPU11>; + operating-points-v2 =3D <&memory2_monitor0_opp_tab= le>; + + memory2_monitor0_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-2189000000 { + opp-hz =3D /bits/ 64 <2189000000>; + opp-level =3D ; + }; + + opp-3860000000 { + opp-hz =3D /bits/ 64 <3860000000>; + opp-level =3D ; + }; + }; + }; + }; + }; + }; + }; diff --git a/include/dt-bindings/firmware/qcom,scmi-memlat.h b/include/dt-b= indings/firmware/qcom,scmi-memlat.h new file mode 100644 index 000000000000..7ae8d8d5623b --- /dev/null +++ b/include/dt-bindings/firmware/qcom,scmi-memlat.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. 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charset="utf-8" Add QCOM System Control Management Interface (SCMI) Generic Vendor Extensions Protocol documentation. Signed-off-by: Sibi Sankar --- .../arm_scmi/vendors/qcom/qcom_generic.rst | 210 ++++++++++++++++++ 1 file changed, 210 insertions(+) create mode 100644 drivers/firmware/arm_scmi/vendors/qcom/qcom_generic.rst diff --git a/drivers/firmware/arm_scmi/vendors/qcom/qcom_generic.rst b/driv= ers/firmware/arm_scmi/vendors/qcom/qcom_generic.rst new file mode 100644 index 000000000000..1ee6dabaac23 --- /dev/null +++ b/drivers/firmware/arm_scmi/vendors/qcom/qcom_generic.rst @@ -0,0 +1,210 @@ +.. SPDX-License-Identifier: GPL-2.0 +.. include:: + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D +QCOM System Control and Management Interface(SCMI) Vendor Protocols Extens= ion +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D + +:Copyright: |copy| 2024, Qualcomm Innovation Center, Inc. All rights reser= ved. + +:Author: Sibi Sankar + +SCMI_GENERIC: System Control and Management Interface QCOM Generic Vendor = Protocol +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D + +This protocol is intended as a generic way of exposing a number of Qualcomm +SoC specific features through a mixture of pre-determined algorithm string= and +param_id pairs hosted on the SCMI controller. It implements an interface c= ompliant +with the Arm SCMI Specification with additional vendor specific commands as +detailed below. + +Commands: +_________ + +PROTOCOL_VERSION +~~~~~~~~~~~~~~~~ + +message_id: 0x0 +protocol_id: 0x80 + ++---------------+---------------------------------------------------------= -----+ +|Return values = | ++---------------+---------------------------------------------------------= -----+ +|Name |Description = | ++---------------+---------------------------------------------------------= -----+ +|int32 status |See ARM SCMI Specification for status code definitions. = | ++---------------+---------------------------------------------------------= -----+ +|uint32 version |For this revision of the specification, this value must b= e | +| |0x10000. = | ++---------------+---------------------------------------------------------= -----+ + +PROTOCOL_ATTRIBUTES +~~~~~~~~~~~~~~~~~~~ + +message_id: 0x1 +protocol_id: 0x80 + ++---------------+---------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|int32 status |See ARM SCMI Specification for status code definitions= . | ++------------------+------------------------------------------------------= -----+ +|uint32 attributes |Bits[8] Set to 1. = | +| |Bits[0] Set to 1. = | ++------------------+------------------------------------------------------= -----+ + +PROTOCOL_MESSAGE_ATTRIBUTES +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +message_id: 0x2 +protocol_id: 0x80 + ++---------------+---------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|int32 status |See ARM SCMI Specification for status code definitions= . | ++------------------+------------------------------------------------------= -----+ +|uint32 attributes |For all message id's the parameter has a value of 0. = | ++------------------+------------------------------------------------------= -----+ + +QCOM_SCMI_SET_PARAM +~~~~~~~~~~~~~~~~~~~ + +message_id: 0x10 +protocol_id: 0x80 + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 ext_id |Reserved, must be zero. = | ++------------------+------------------------------------------------------= -----+ +|uint32 algo_low |Lower 32-bit value of the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 algo_high |Upper 32-bit value of the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 param_id |Serves as the token message id for the algorithm strin= g | +| |and is used to set various parameters supported by it.= | ++------------------+------------------------------------------------------= -----+ +|uint32 buf[] |Serves as the payload for the specified param_id and = | +| |algorithm string pair. = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS: if the param_id and buf[] is parsed successfu= lly | +| |by the chosen algorithm string. = | +| |NOT_SUPPORTED: if the algorithm string does not have a= ny | +| |matches. = | +| |INVALID_PARAMETERS: if the param_id and the buf[] pass= ed | +| |is rejected by the algorithm string. = | ++------------------+------------------------------------------------------= -----+ + +QCOM_SCMI_GET_PARAM +~~~~~~~~~~~~~~~~~~~ + +message_id: 0x11 +protocol_id: 0x80 + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 ext_id |Reserved, must be zero. = | ++------------------+------------------------------------------------------= -----+ +|uint32 algo_low |Lower 32-bit value of the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 algo_high |Upper 32-bit value of the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 param_id |Serves as the token message id for the algorithm strin= g. | ++------------------+------------------------------------------------------= -----+ +|uint32 buf[] |Serves as the payload and store of value for the speci= fied | +| |param_id and algorithm string pair. = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS: if the param_id and buf[] is parsed successfu= lly | +| |by the chosen algorithm string and the result is copie= d | +| |into buf[]. = | +| |NOT_SUPPORTED: if the algorithm string does not have a= ny | +| |matches. = | +| |INVALID_PARAMETERS: if the param_id and the buf[] pass= ed | +| |is rejected by the algorithm string. = | ++------------------+------------------------------------------------------= -----+ + +QCOM_SCMI_START_ACTIVITY +~~~~~~~~~~~~~~~~~~~~~~~~ + +message_id: 0x12 +protocol_id: 0x80 + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 ext_id |Reserved, must be zero. = | ++------------------+------------------------------------------------------= -----+ +|uint32 algo_low |Lower 32-bit value of the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 algo_high |Upper 32-bit value of the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 param_id |Serves as the token message id for the algorithm strin= g | +| |and is generally used to start the activity performed = by | +| |the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 buf[] |Serves as the payload for the specified param_id and = | +| |algorithm string pair. = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS: if the activity performed by the algorithm st= ring | +| |starts successfully. = | +| |NOT_SUPPORTED: if the algorithm string does not have a= ny. | +| |matches or if the activity is already running. = | ++------------------+------------------------------------------------------= -----+ + +QCOM_SCMI_STOP_ACTIVITY +~~~~~~~~~~~~~~~~~~~~~~~ + +message_id: 0x13 +protocol_id: 0x80 + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 ext_id |Reserved, must be zero. = | ++------------------+------------------------------------------------------= -----+ +|uint32 algo_low |Lower 32-bit value of the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 algo_high |Upper 32-bit value of the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 param_id |Serves as the token message id for the algorithm strin= g | +| |and is generally used to stop the activity performed b= y | +| |the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 buf[] |Serves as the payload for the specified param_id and = | +| |algorithm string pair. = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS: if the activity performed by the algorithm st= ring | +| |stops successfully. = | +| |NOT_SUPPORTED: if the algorithm string does not have a= ny | +| |matches or if the activity isn't running. = | ++------------------+------------------------------------------------------= -----+ --=20 2.34.1 From nobody Thu Nov 28 00:49:27 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFA3917622F; Mon, 7 Oct 2024 06:11:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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firmware: arm_scmi: vendors: Add QCOM SCMI Generic Extensions Date: Mon, 7 Oct 2024 11:40:21 +0530 Message-ID: <20241007061023.1978380-4-quic_sibis@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241007061023.1978380-1-quic_sibis@quicinc.com> References: <20241007061023.1978380-1-quic_sibis@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 4O-uGFOFMeoiMkXRwSJTgkEmUvTfhjgC X-Proofpoint-GUID: 4O-uGFOFMeoiMkXRwSJTgkEmUvTfhjgC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 adultscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 mlxlogscore=999 clxscore=1015 malwarescore=0 spamscore=0 lowpriorityscore=0 phishscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410070042 Content-Type: text/plain; charset="utf-8" The QCOM SCMI Generic Extensions Protocol provides a generic way of exposing a number of Qualcomm SoC specific features (like memory bus scaling) through a mixture of pre-determined algorithm strings and param_id pairs hosted on the SCMI controller. Co-developed-by: Shivnandan Kumar Signed-off-by: Shivnandan Kumar Co-developed-by: Ramakrishna Gottimukkula Signed-off-by: Ramakrishna Gottimukkula Co-developed-by: Amir Vajid Signed-off-by: Amir Vajid Signed-off-by: Sibi Sankar Reviewed-by: Cristian Marussi --- v3: * Pick up Rb tag and fixup/re-order elements of the vendor ops [Christian] * Follow naming convention and folder structure used by IMX * Add missing enum in the vendor protocol and fix documentation [Konrad] drivers/firmware/arm_scmi/Kconfig | 1 + drivers/firmware/arm_scmi/Makefile | 1 + .../firmware/arm_scmi/vendors/qcom/Kconfig | 15 ++ .../firmware/arm_scmi/vendors/qcom/Makefile | 2 + .../arm_scmi/vendors/qcom/qcom-generic-ext.c | 184 ++++++++++++++++++ include/linux/scmi_qcom_protocol.h | 39 ++++ 6 files changed, 242 insertions(+) create mode 100644 drivers/firmware/arm_scmi/vendors/qcom/Kconfig create mode 100644 drivers/firmware/arm_scmi/vendors/qcom/Makefile create mode 100644 drivers/firmware/arm_scmi/vendors/qcom/qcom-generic-ext= .c create mode 100644 include/linux/scmi_qcom_protocol.h diff --git a/drivers/firmware/arm_scmi/Kconfig b/drivers/firmware/arm_scmi/= Kconfig index dabd874641d0..73128442d97b 100644 --- a/drivers/firmware/arm_scmi/Kconfig +++ b/drivers/firmware/arm_scmi/Kconfig @@ -71,6 +71,7 @@ config ARM_SCMI_DEBUG_COUNTERS =20 source "drivers/firmware/arm_scmi/transports/Kconfig" source "drivers/firmware/arm_scmi/vendors/imx/Kconfig" +source "drivers/firmware/arm_scmi/vendors/qcom/Kconfig" =20 endif #ARM_SCMI_PROTOCOL =20 diff --git a/drivers/firmware/arm_scmi/Makefile b/drivers/firmware/arm_scmi= /Makefile index 9ac81adff567..58cf4d656cbb 100644 --- a/drivers/firmware/arm_scmi/Makefile +++ b/drivers/firmware/arm_scmi/Makefile @@ -12,6 +12,7 @@ scmi-module-objs :=3D $(scmi-driver-y) $(scmi-protocols-y= ) $(scmi-transport-y) =20 obj-$(CONFIG_ARM_SCMI_PROTOCOL) +=3D transports/ obj-$(CONFIG_ARM_SCMI_PROTOCOL) +=3D vendors/imx/ +obj-$(CONFIG_ARM_SCMI_PROTOCOL) +=3D vendors/qcom/ =20 obj-$(CONFIG_ARM_SCMI_PROTOCOL) +=3D scmi-core.o obj-$(CONFIG_ARM_SCMI_PROTOCOL) +=3D scmi-module.o diff --git a/drivers/firmware/arm_scmi/vendors/qcom/Kconfig b/drivers/firmw= are/arm_scmi/vendors/qcom/Kconfig new file mode 100644 index 000000000000..5dd9e8a6b75f --- /dev/null +++ b/drivers/firmware/arm_scmi/vendors/qcom/Kconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only +menu "ARM SCMI QCOM Vendor Protocols" + +config QCOM_SCMI_GENERIC_EXT + tristate "Qualcomm Technologies, Inc. Qcom SCMI vendor Protocol" + depends on ARM_SCMI_PROTOCOL || COMPILE_TEST + help + The QCOM SCMI vendor protocol provides a generic way of exposing + a number of Qualcomm SoC specific features (like memory bus scaling) + through a mixture of pre-determined algorithm strings and param_id + pairs hosted on the SCMI controller. + + This driver defines/documents the message ID's used for this + communication and also exposes the operations used by the clients. +endmenu diff --git a/drivers/firmware/arm_scmi/vendors/qcom/Makefile b/drivers/firm= ware/arm_scmi/vendors/qcom/Makefile new file mode 100644 index 000000000000..6b98fabbebb8 --- /dev/null +++ b/drivers/firmware/arm_scmi/vendors/qcom/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_QCOM_SCMI_GENERIC_EXT) +=3D qcom-generic-ext.o diff --git a/drivers/firmware/arm_scmi/vendors/qcom/qcom-generic-ext.c b/dr= ivers/firmware/arm_scmi/vendors/qcom/qcom-generic-ext.c new file mode 100644 index 000000000000..f7cd949161df --- /dev/null +++ b/drivers/firmware/arm_scmi/vendors/qcom/qcom-generic-ext.c @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#include + +#include "../../common.h" + +/** + * enum qcom_generic_ext_protocol_cmd - vendor specific commands supported= by SCMI Qualcomm + * generic vendor protocol. + * + * This protocol is intended as a generic way of exposing a number of Qual= comm SoC + * specific features through a mixture of pre-determined algorithm string = and param_id + * pairs hosted on the SCMI controller. + * + * The QCOM SCMI Vendor Protocol has the protocol id as 0x80 and vendor id= set to + * Qualcomm and the implementation version set to 0x20000. The PROTOCOL_VE= RSION command + * returns version 1.0. + * + * @QCOM_SCMI_SET_PARAM: message_id: 0x10 is used to set the parameter of = a specific algo_str + * hosted on QCOM SCMI Vendor Protocol. The tx len d= epends on the + * algo_str used. + * @QCOM_SCMI_GET_PARAM: message_id: 0x11 is used to get parameter informa= tion of a specific + * algo_str hosted on QCOM SCMI Vendor Protocol. The= tx and rx len + * depends on the algo_str used. + * @QCOM_SCMI_START_ACTIVITY: message_id: 0x12 is used to start the activi= ty performed by + * the algo_str. + * @QCOM_SCMI_STOP_ACTIVITY: message_id: 0x13 is used to stop a pre-existi= ng activity + * performed by the algo_str. + */ +enum qcom_generic_ext_protocol_cmd { + QCOM_SCMI_SET_PARAM =3D 0x10, + QCOM_SCMI_GET_PARAM =3D 0x11, + QCOM_SCMI_START_ACTIVITY =3D 0x12, + QCOM_SCMI_STOP_ACTIVITY =3D 0x13, +}; + +/** + * struct qcom_scmi_msg - represents the various parameters to be populated + * for using the QCOM SCMI Vendor Protocol + * + * @ext_id: reserved, must be zero + * @algo_low: lower 32 bits of the algo_str + * @algo_high: upper 32 bits of the algo_str + * @param_id: serves as token message id to the specific algo_str + * @buf: serves as the payload to the specified param_id and algo_str pair + */ +struct qcom_scmi_msg { + __le32 ext_id; + __le32 algo_low; + __le32 algo_high; + __le32 param_id; + __le32 buf[]; +}; + +static int qcom_scmi_set_param(const struct scmi_protocol_handle *ph, void= *buf, size_t buf_len, + u64 algo_str, u32 param_id) +{ + struct scmi_xfer *t; + struct qcom_scmi_msg *msg; + int ret; + + ret =3D ph->xops->xfer_get_init(ph, QCOM_SCMI_SET_PARAM, buf_len + sizeof= (*msg), 0, &t); + if (ret) + return ret; + + msg =3D t->tx.buf; + msg->algo_low =3D cpu_to_le32(lower_32_bits(algo_str)); + msg->algo_high =3D cpu_to_le32(upper_32_bits(algo_str)); + msg->param_id =3D cpu_to_le32(param_id); + + memcpy(msg->buf, buf, t->tx.len - sizeof(*msg)); + + ret =3D ph->xops->do_xfer(ph, t); + ph->xops->xfer_put(ph, t); + + return ret; +} + +static int qcom_scmi_get_param(const struct scmi_protocol_handle *ph, void= *buf, size_t buf_len, + u64 algo_str, u32 param_id, size_t rx_size) +{ + struct scmi_xfer *t; + struct qcom_scmi_msg *msg; + int ret; + + ret =3D ph->xops->xfer_get_init(ph, QCOM_SCMI_GET_PARAM, buf_len + sizeof= (*msg), rx_size, &t); + if (ret) + return ret; + + msg =3D t->tx.buf; + msg->algo_low =3D cpu_to_le32(lower_32_bits(algo_str)); + msg->algo_high =3D cpu_to_le32(upper_32_bits(algo_str)); + msg->param_id =3D cpu_to_le32(param_id); + memcpy(msg->buf, buf, t->tx.len - sizeof(*msg)); + + ret =3D ph->xops->do_xfer(ph, t); + memcpy(buf, t->rx.buf, t->rx.len); + ph->xops->xfer_put(ph, t); + + return ret; +} + +static int qcom_scmi_start_activity(const struct scmi_protocol_handle *ph,= void *buf, + size_t buf_len, u64 algo_str, u32 param_id) +{ + struct scmi_xfer *t; + struct qcom_scmi_msg *msg; + int ret; + + ret =3D ph->xops->xfer_get_init(ph, QCOM_SCMI_START_ACTIVITY, buf_len + s= izeof(*msg), 0, &t); + if (ret) + return ret; + + msg =3D t->tx.buf; + msg->algo_low =3D cpu_to_le32(lower_32_bits(algo_str)); + msg->algo_high =3D cpu_to_le32(upper_32_bits(algo_str)); + msg->param_id =3D cpu_to_le32(param_id); + + memcpy(msg->buf, buf, t->tx.len - sizeof(*msg)); + + ret =3D ph->xops->do_xfer(ph, t); + ph->xops->xfer_put(ph, t); + + return ret; +} + +static int qcom_scmi_stop_activity(const struct scmi_protocol_handle *ph, = void *buf, + size_t buf_len, u64 algo_str, u32 param_id) +{ + struct scmi_xfer *t; + struct qcom_scmi_msg *msg; + int ret; + + ret =3D ph->xops->xfer_get_init(ph, QCOM_SCMI_STOP_ACTIVITY, buf_len + si= zeof(*msg), 0, &t); + if (ret) + return ret; + + msg =3D t->tx.buf; + msg->algo_low =3D cpu_to_le32(lower_32_bits(algo_str)); + msg->algo_high =3D cpu_to_le32(upper_32_bits(algo_str)); + msg->param_id =3D cpu_to_le32(param_id); + + memcpy(msg->buf, buf, t->tx.len - sizeof(*msg)); + + ret =3D ph->xops->do_xfer(ph, t); + ph->xops->xfer_put(ph, t); + + return ret; +} + +static struct qcom_generic_ext_ops qcom_proto_ops =3D { + .set_param =3D qcom_scmi_set_param, + .get_param =3D qcom_scmi_get_param, + .start_activity =3D qcom_scmi_start_activity, + .stop_activity =3D qcom_scmi_stop_activity, +}; + +static int qcom_generic_ext_protocol_init(const struct scmi_protocol_handl= e *ph) +{ + u32 version; + + ph->xops->version_get(ph, &version); + + dev_info(ph->dev, "QCOM Generic Vendor Version %d.%d\n", + PROTOCOL_REV_MAJOR(version), PROTOCOL_REV_MINOR(version)); + + return 0; +} + +static const struct scmi_protocol qcom_generic_ext =3D { + .id =3D SCMI_PROTOCOL_QCOM_GENERIC, + .owner =3D THIS_MODULE, + .instance_init =3D &qcom_generic_ext_protocol_init, + .ops =3D &qcom_proto_ops, + .vendor_id =3D "Qualcomm", + .impl_ver =3D 0x20000, +}; +module_scmi_protocol(qcom_generic_ext); + +MODULE_DESCRIPTION("QCOM SCMI Generic Vendor protocol"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/scmi_qcom_protocol.h b/include/linux/scmi_qcom_p= rotocol.h new file mode 100644 index 000000000000..8f82c42e566d --- /dev/null +++ b/include/linux/scmi_qcom_protocol.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * SCMI Message Protocol driver QCOM extension header + * + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#ifndef _LINUX_SCMI_QCOM_PROTOCOL_H +#define _LINUX_SCMI_QCOM_PROTOCOL_H + +#include +#include +#include + +#define SCMI_PROTOCOL_QCOM_GENERIC 0x80 + +struct scmi_protocol_handle; + +/** + * struct qcom_generic_ext_ops - represents the various operations provided + * by QCOM Generic Vendor Protocol + * + * @set_param: set parameter specified by param_id and algo_str pair. + * @get_param: retrieve parameter specified by param_id and algo_str pair. + * @start_activity: initiate a specific activity defined by algo_str. + * @stop_activity: halt previously initiated activity defined by algo_str. + */ +struct qcom_generic_ext_ops { + int (*set_param)(const struct scmi_protocol_handle *ph, void *buf, size_t= buf_len, + u64 algo_str, u32 param_id); + int (*get_param)(const struct scmi_protocol_handle *ph, void *buf, size_t= buf_len, + u64 algo_str, u32 param_id, size_t rx_size); + int (*start_activity)(const struct scmi_protocol_handle *ph, void *buf, s= ize_t buf_len, + u64 algo_str, u32 param_id); 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Mon, 7 Oct 2024 06:11:03 GMT Received: from hu-sibis-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sun, 6 Oct 2024 23:10:57 -0700 From: Sibi Sankar To: , , , , , CC: , , , , , , , , , Amir Vajid Subject: [PATCH V4 4/5] soc: qcom: Introduce SCMI based Memlat (Memory Latency) governor Date: Mon, 7 Oct 2024 11:40:22 +0530 Message-ID: <20241007061023.1978380-5-quic_sibis@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241007061023.1978380-1-quic_sibis@quicinc.com> References: <20241007061023.1978380-1-quic_sibis@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: tEZuKciGy8f_1KUch_IWYK0XWbKLK89t X-Proofpoint-ORIG-GUID: tEZuKciGy8f_1KUch_IWYK0XWbKLK89t X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 spamscore=0 mlxscore=0 malwarescore=0 suspectscore=0 mlxlogscore=999 impostorscore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410070041 Content-Type: text/plain; charset="utf-8" Introduce a client driver that uses the memlat algorithm string hosted on QCOM SCMI Generic Extension Protocol to detect memory latency workloads and control frequency/level of the various memory buses (DDR/LLCC/DDR_QOS). Co-developed-by: Shivnandan Kumar Signed-off-by: Shivnandan Kumar Co-developed-by: Ramakrishna Gottimukkula Signed-off-by: Ramakrishna Gottimukkula Co-developed-by: Amir Vajid Signed-off-by: Amir Vajid Signed-off-by: Sibi Sankar --- v3: * Add missing enum in the scmi memlat driver and fix documentation [Konrad] * Add checks for max memory and monitor [Shivnandan] * Fix typo from START_TIMER -> STOP_TIMER [Shivnandan] * Make populate_physical_mask func to void [Shivnandan] * Remove unecessary zero set [Shivnandan] * Use __free(device node) in init_cpufreq-memfreqmap [Christian/Konrad] * Use sdev->dev.of_node directly [Christian] * use return dev_err_probe in multiple places [Christian] drivers/soc/qcom/Kconfig | 12 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/qcom_scmi_memlat_client.c | 569 +++++++++++++++++++++ 3 files changed, 582 insertions(+) create mode 100644 drivers/soc/qcom/qcom_scmi_memlat_client.c diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index 74b9121240f8..1b6dd40d69ea 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -295,4 +295,16 @@ config QCOM_PBS This module provides the APIs to the client drivers that wants to send = the PBS trigger event to the PBS RAM. =20 +config QCOM_SCMI_MEMLAT_CLIENT + tristate "Qualcomm Technologies Inc. SCMI client driver" + depends on QCOM_SCMI_GENERIC_EXT || COMPILE_TEST + help + This driver uses the MEMLAT (memory latency) algorithm string + hosted on QCOM SCMI Vendor Protocol to detect memory latency + workloads and control frequency/level of the various memory + buses (DDR/LLCC/DDR_QOS). + + This driver defines/documents the parameter IDs used while configuring + the memory buses. + endmenu diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index acbca2ab5cc2..28549bb141bc 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_QCOM_APR) +=3D apr.o obj-$(CONFIG_QCOM_LLCC) +=3D llcc-qcom.o obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) +=3D kryo-l2-accessors.o obj-$(CONFIG_QCOM_ICC_BWMON) +=3D icc-bwmon.o +obj-$(CONFIG_QCOM_SCMI_MEMLAT_CLIENT) +=3D qcom_scmi_memlat_client.o qcom_ice-objs +=3D ice.o obj-$(CONFIG_QCOM_INLINE_CRYPTO_ENGINE) +=3D qcom_ice.o obj-$(CONFIG_QCOM_PBS) +=3D qcom-pbs.o diff --git a/drivers/soc/qcom/qcom_scmi_memlat_client.c b/drivers/soc/qcom/= qcom_scmi_memlat_client.c new file mode 100644 index 000000000000..05198bf1f7ec --- /dev/null +++ b/drivers/soc/qcom/qcom_scmi_memlat_client.c @@ -0,0 +1,569 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MEMLAT_ALGO_STR 0x4D454D4C4154 /* MEMLAT */ +#define INVALID_IDX 0xff +#define MAX_MEMORY_TYPES 3 +#define MAX_MONITOR_CNT 4 +#define MAX_NAME_LEN 20 +#define MAX_MAP_ENTRIES 7 +#define CPUCP_DEFAULT_SAMPLING_PERIOD_MS 4 +#define CPUCP_DEFAULT_FREQ_METHOD 1 + +/** + * enum scmi_memlat_protocol_cmd - parameter_ids supported by the "MEMLAT"= algo_str hosted + * by the Qualcomm Generic Vendor Protocol= on the SCMI controller. + * + * MEMLAT (Memory Latency) monitors the counters to detect memory latency = bound workloads + * and scales the frequency/levels of the memory buses accordingly. + * + * @MEMLAT_SET_MEM_GROUP: initializes the frequency/level scaling function= s for the memory bus. + * @MEMLAT_SET_MONITOR: configures the monitor to work on a specific memor= y bus. + * @MEMLAT_SET_COMMON_EV_MAP: set up common counters used to monitor the c= pu frequency. + * @MEMLAT_SET_GRP_EV_MAP: set up any specific counters used to monitor th= e memory bus. + * @MEMLAT_IPM_CEIL: set the IPM (Instruction Per Misses) ceiling per moni= tor. + * @MEMLAT_SAMPLE_MS: set the sampling period for all the monitors. + * @MEMLAT_MON_FREQ_MAP: setup the cpufreq to memfreq map. + * @MEMLAT_SET_MIN_FREQ: set the max frequency of the memory bus. + * @MEMLAT_SET_MAX_FREQ: set the min frequency of the memory bus. + * @MEMLAT_START_TIMER: start all the monitors with the requested sampling= period. + * @MEMLAT_STOP_TIMER: stop all the running monitors. + * @MEMLAT_SET_EFFECTIVE_FREQ_METHOD: set the method used to determine cpu= frequency. + */ +enum scmi_memlat_protocol_cmd { + MEMLAT_SET_MEM_GROUP =3D 16, + MEMLAT_SET_MONITOR, + MEMLAT_SET_COMMON_EV_MAP, + MEMLAT_SET_GRP_EV_MAP, + MEMLAT_IPM_CEIL =3D 23, + MEMLAT_SAMPLE_MS =3D 31, + MEMLAT_MON_FREQ_MAP, + MEMLAT_SET_MIN_FREQ, + MEMLAT_SET_MAX_FREQ, + MEMLAT_START_TIMER =3D 36, + MEMLAT_STOP_TIMER, + MEMLAT_SET_EFFECTIVE_FREQ_METHOD =3D 39, +}; + +struct map_table { + u16 v1; + u16 v2; +}; + +struct map_param_msg { + u32 hw_type; + u32 mon_idx; + u32 nr_rows; + struct map_table tbl[MAX_MAP_ENTRIES]; +} __packed; + +struct node_msg { + u32 cpumask; + u32 hw_type; + u32 mon_type; + u32 mon_idx; + char mon_name[MAX_NAME_LEN]; +}; + +struct scalar_param_msg { + u32 hw_type; + u32 mon_idx; + u32 val; +}; + +enum common_ev_idx { + INST_IDX, + CYC_IDX, + CONST_CYC_IDX, + FE_STALL_IDX, + BE_STALL_IDX, + NUM_COMMON_EVS +}; + +enum grp_ev_idx { + MISS_IDX, + WB_IDX, + ACC_IDX, + NUM_GRP_EVS +}; + +#define EV_CPU_CYCLES 0 +#define EV_INST_RETIRED 2 +#define EV_L2_D_RFILL 5 + +struct ev_map_msg { + u32 num_evs; + u32 hw_type; + u32 cid[NUM_COMMON_EVS]; +}; + +struct cpufreq_memfreq_map { + unsigned int cpufreq_mhz; + unsigned int memfreq_khz; +}; + +struct scmi_monitor_info { + struct cpufreq_memfreq_map *freq_map; + char mon_name[MAX_NAME_LEN]; + u32 mon_idx; + u32 mon_type; + u32 ipm_ceil; + u32 mask; + u32 freq_map_len; +}; + +struct scmi_memory_info { + struct scmi_monitor_info *monitor[MAX_MONITOR_CNT]; + u32 hw_type; + int monitor_cnt; + u32 min_freq; + u32 max_freq; +}; + +struct scmi_memlat_info { + struct scmi_protocol_handle *ph; + const struct qcom_generic_ext_ops *ops; + struct scmi_memory_info *memory[MAX_MEMORY_TYPES]; + u32 cluster_info[NR_CPUS]; + int memory_cnt; +}; + +static int populate_cluster_info(u32 *cluster_info) +{ + char name[MAX_NAME_LEN]; + int i =3D 0; + + struct device_node *cn __free(device_node) =3D of_find_node_by_path("/cpu= s"); + if (!cn) + return -ENODEV; + + struct device_node *map __free(device_node) =3D of_get_child_by_name(cn, = "cpu-map"); + if (!map) + return -ENODEV; + + do { + snprintf(name, sizeof(name), "cluster%d", i); + struct device_node *c __free(device_node) =3D of_get_child_by_name(map, = name); + if (!c) + break; + + *(cluster_info + i) =3D of_get_child_count(c); + i++; + } while (1); + + return 0; +} + +static void populate_physical_mask(struct device_node *np, u32 *mask, u32 = *cluster_info) +{ + struct device_node *dev_phandle __free(device_node); + int cpu, i =3D 0, physical_id; + + do { + dev_phandle =3D of_parse_phandle(np, "cpus", i++); + cpu =3D of_cpu_node_to_id(dev_phandle); + if (cpu !=3D -ENODEV) { + physical_id =3D topology_core_id(cpu); + for (int j =3D 0; j < topology_cluster_id(cpu); j++) + physical_id +=3D *(cluster_info + j); + *mask |=3D BIT(physical_id); + } + } while (dev_phandle); +} + +static struct cpufreq_memfreq_map *init_cpufreq_memfreq_map(struct device = *dev, + struct scmi_memory_info *memory, + struct device_node *of_node, + u32 *cnt) +{ + struct device_node *tbl_np __free(device_node), *opp_np __free(device_nod= e); + struct cpufreq_memfreq_map *tbl; + int ret, i =3D 0; + u32 level, len; + u64 rate; + + tbl_np =3D of_parse_phandle(of_node, "operating-points-v2", 0); + if (!tbl_np) + return ERR_PTR(-ENODEV); + + len =3D min(of_get_available_child_count(tbl_np), MAX_MAP_ENTRIES); + if (len =3D=3D 0) + return ERR_PTR(-ENODEV); + + tbl =3D devm_kzalloc(dev, (len + 1) * sizeof(struct cpufreq_memfreq_map), + GFP_KERNEL); + if (!tbl) + return ERR_PTR(-ENOMEM); + + for_each_available_child_of_node(tbl_np, opp_np) { + ret =3D of_property_read_u64_index(opp_np, "opp-hz", 0, &rate); + if (ret < 0) + return ERR_PTR(ret); + + tbl[i].cpufreq_mhz =3D rate / HZ_PER_MHZ; + + if (memory->hw_type !=3D QCOM_MEM_TYPE_DDR_QOS) { + ret =3D of_property_read_u64_index(opp_np, "opp-hz", 1, &rate); + if (ret < 0) + return ERR_PTR(ret); + + tbl[i].memfreq_khz =3D rate / HZ_PER_KHZ; + } else { + ret =3D of_property_read_u32(opp_np, "opp-level", &level); + if (ret < 0) + return ERR_PTR(ret); + + tbl[i].memfreq_khz =3D level; + } + + dev_dbg(dev, "Entry%d CPU:%u, Mem:%u\n", i, tbl[i].cpufreq_mhz, tbl[i].m= emfreq_khz); + i++; + } + *cnt =3D len; + + return tbl; +} + +static int process_scmi_memlat_of_node(struct scmi_device *sdev, struct sc= mi_memlat_info *info) +{ + struct scmi_monitor_info *monitor; + struct scmi_memory_info *memory; + char name[MAX_NAME_LEN]; + u64 memfreq[2]; + int ret; + + ret =3D populate_cluster_info(info->cluster_info); + if (ret < 0) { + dev_err_probe(&sdev->dev, ret, "failed to populate cluster info\n"); + goto err; + } + + of_node_get(sdev->dev.of_node); + do { + snprintf(name, sizeof(name), "memory-%d", info->memory_cnt); + struct device_node *memory_np __free(device_node) =3D + of_find_node_by_name(sdev->dev.of_node, name); + + if (!memory_np) + break; + + if (info->memory_cnt >=3D MAX_MEMORY_TYPES) + return dev_err_probe(&sdev->dev, -EINVAL, + "failed to parse unsupported memory type\n"); + + memory =3D devm_kzalloc(&sdev->dev, sizeof(*memory), GFP_KERNEL); + if (!memory) { + ret =3D -ENOMEM; + goto err; + } + + ret =3D of_property_read_u32(memory_np, "qcom,memory-type", &memory->hw_= type); + if (ret) { + dev_err_probe(&sdev->dev, ret, "failed to read memory type\n"); + goto err; + } + + ret =3D of_property_read_u64_array(memory_np, "freq-table-hz", memfreq, = 2); + if (ret && (ret !=3D -EINVAL)) { + dev_err_probe(&sdev->dev, ret, "failed to read min/max freq\n"); + goto err; + } + + if (memory->hw_type !=3D QCOM_MEM_TYPE_DDR_QOS) { + memory->min_freq =3D memfreq[0] / HZ_PER_KHZ; + memory->max_freq =3D memfreq[1] / HZ_PER_KHZ; + } else { + memory->min_freq =3D memfreq[0]; + memory->max_freq =3D memfreq[1]; + } + info->memory[info->memory_cnt++] =3D memory; + + do { + snprintf(name, sizeof(name), "monitor-%d", memory->monitor_cnt); + struct device_node *monitor_np __free(device_node) =3D + of_get_child_by_name(memory_np, name); + + if (!monitor_np) + break; + + if (memory->monitor_cnt >=3D MAX_MONITOR_CNT) + return dev_err_probe(&sdev->dev, -EINVAL, + "failed to parse unsupported monitor\n"); + + monitor =3D devm_kzalloc(&sdev->dev, sizeof(*monitor), GFP_KERNEL); + if (!monitor) { + ret =3D -ENOMEM; + goto err; + } + + monitor->mon_type =3D of_property_read_bool(monitor_np, "qcom,compute-t= ype"); + if (!monitor->mon_type) { + ret =3D of_property_read_u32(monitor_np, "qcom,ipm-ceil", + &monitor->ipm_ceil); + if (ret) { + dev_err_probe(&sdev->dev, ret, + "failed to read IPM ceiling\n"); + goto err; + } + } + + /* + * Variants of the SoC having reduced number of cpus operate + * with the same number of logical cpus but the physical + * cpu disabled will differ between parts. Calculate the + * physical cpu number using cluster information instead. + */ + populate_physical_mask(monitor_np, &monitor->mask, info->cluster_info); + + monitor->freq_map =3D init_cpufreq_memfreq_map(&sdev->dev, memory, moni= tor_np, + &monitor->freq_map_len); + if (IS_ERR(monitor->freq_map)) { + dev_err_probe(&sdev->dev, PTR_ERR(monitor->freq_map), + "failed to populate cpufreq-memfreq map\n"); + goto err; + } + + strscpy(monitor->mon_name, name, sizeof(monitor->mon_name)); + monitor->mon_idx =3D memory->monitor_cnt; + + memory->monitor[memory->monitor_cnt++] =3D monitor; + } while (1); + + if (!memory->monitor_cnt) { + ret =3D -EINVAL; + dev_err_probe(&sdev->dev, ret, "failed to find monitor nodes\n"); + goto err; + } + } while (1); + + if (!info->memory_cnt) { + ret =3D -EINVAL; + dev_err_probe(&sdev->dev, ret, "failed to find memory nodes\n"); + } + +err: + of_node_put(sdev->dev.of_node); + + return ret; +} + +static int configure_cpucp_common_events(struct scmi_memlat_info *info) +{ + const struct qcom_generic_ext_ops *ops =3D info->ops; + u8 ev_map[NUM_COMMON_EVS]; + struct ev_map_msg msg; + + memset(ev_map, 0xFF, NUM_COMMON_EVS); + + msg.num_evs =3D NUM_COMMON_EVS; + msg.hw_type =3D INVALID_IDX; + msg.cid[INST_IDX] =3D EV_INST_RETIRED; + msg.cid[CYC_IDX] =3D EV_CPU_CYCLES; + msg.cid[CONST_CYC_IDX] =3D INVALID_IDX; + msg.cid[FE_STALL_IDX] =3D INVALID_IDX; + msg.cid[BE_STALL_IDX] =3D INVALID_IDX; + + return ops->set_param(info->ph, &msg, sizeof(msg), MEMLAT_ALGO_STR, + MEMLAT_SET_COMMON_EV_MAP); +} + +static int configure_cpucp_grp(struct device *dev, struct scmi_memlat_info= *info, int memory_index) +{ + const struct qcom_generic_ext_ops *ops =3D info->ops; + struct scmi_memory_info *memory =3D info->memory[memory_index]; + struct ev_map_msg ev_msg; + u8 ev_map[NUM_GRP_EVS]; + struct node_msg msg; + int ret; + + msg.cpumask =3D 0; + msg.hw_type =3D memory->hw_type; + msg.mon_type =3D 0; + msg.mon_idx =3D 0; + ret =3D ops->set_param(info->ph, &msg, sizeof(msg), MEMLAT_ALGO_STR, MEML= AT_SET_MEM_GROUP); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to configure mem type %d\n", + memory->hw_type); + + memset(ev_map, 0xFF, NUM_GRP_EVS); + ev_msg.num_evs =3D NUM_GRP_EVS; + ev_msg.hw_type =3D memory->hw_type; + ev_msg.cid[MISS_IDX] =3D EV_L2_D_RFILL; + ev_msg.cid[WB_IDX] =3D INVALID_IDX; + ev_msg.cid[ACC_IDX] =3D INVALID_IDX; + ret =3D ops->set_param(info->ph, &ev_msg, sizeof(ev_msg), MEMLAT_ALGO_STR, + MEMLAT_SET_GRP_EV_MAP); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to configure event map for mem ty= pe %d\n", + memory->hw_type); + + return ret; +} + +static int configure_cpucp_mon(struct device *dev, struct scmi_memlat_info= *info, + int memory_index, int monitor_index) +{ + const struct qcom_generic_ext_ops *ops =3D info->ops; + struct scmi_memory_info *memory =3D info->memory[memory_index]; + struct scmi_monitor_info *monitor =3D memory->monitor[monitor_index]; + struct scalar_param_msg scalar_msg; + struct map_param_msg map_msg; + struct node_msg msg; + int ret; + int i; + + msg.cpumask =3D monitor->mask; + msg.hw_type =3D memory->hw_type; + msg.mon_type =3D monitor->mon_type; + msg.mon_idx =3D monitor->mon_idx; + strscpy(msg.mon_name, monitor->mon_name, sizeof(msg.mon_name)); + ret =3D ops->set_param(info->ph, &msg, sizeof(msg), MEMLAT_ALGO_STR, MEML= AT_SET_MONITOR); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to configure monitor %s\n", + monitor->mon_name); + + scalar_msg.hw_type =3D memory->hw_type; + scalar_msg.mon_idx =3D monitor->mon_idx; + scalar_msg.val =3D monitor->ipm_ceil; + ret =3D ops->set_param(info->ph, &scalar_msg, sizeof(scalar_msg), MEMLAT_= ALGO_STR, + MEMLAT_IPM_CEIL); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to set ipm ceil for %s\n", + monitor->mon_name); + + map_msg.hw_type =3D memory->hw_type; + map_msg.mon_idx =3D monitor->mon_idx; + map_msg.nr_rows =3D monitor->freq_map_len; + for (i =3D 0; i < monitor->freq_map_len; i++) { + map_msg.tbl[i].v1 =3D monitor->freq_map[i].cpufreq_mhz; + map_msg.tbl[i].v2 =3D monitor->freq_map[i].memfreq_khz; + } + ret =3D ops->set_param(info->ph, &map_msg, sizeof(map_msg), MEMLAT_ALGO_S= TR, + MEMLAT_MON_FREQ_MAP); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to configure freq_map for %s\n", + monitor->mon_name); + + scalar_msg.hw_type =3D memory->hw_type; + scalar_msg.mon_idx =3D monitor->mon_idx; + scalar_msg.val =3D memory->min_freq; + ret =3D ops->set_param(info->ph, &scalar_msg, sizeof(scalar_msg), MEMLAT_= ALGO_STR, + MEMLAT_SET_MIN_FREQ); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to set min_freq for %s\n", + monitor->mon_name); + + scalar_msg.hw_type =3D memory->hw_type; + scalar_msg.mon_idx =3D monitor->mon_idx; + scalar_msg.val =3D memory->max_freq; + ret =3D ops->set_param(info->ph, &scalar_msg, sizeof(scalar_msg), MEMLAT_= ALGO_STR, + MEMLAT_SET_MAX_FREQ); + if (ret < 0) + dev_err_probe(dev, ret, "failed to set max_freq for %s\n", monitor->mon_= name); + + return ret; +} + +static int cpucp_memlat_init(struct scmi_device *sdev) +{ + const struct scmi_handle *handle =3D sdev->handle; + const struct qcom_generic_ext_ops *ops; + struct scmi_protocol_handle *ph; + struct scmi_memlat_info *info; + u32 cpucp_freq_method =3D CPUCP_DEFAULT_FREQ_METHOD; + u32 cpucp_sample_ms =3D CPUCP_DEFAULT_SAMPLING_PERIOD_MS; + int ret, i, j; + + if (!handle) + return -ENODEV; + + ops =3D handle->devm_protocol_get(sdev, SCMI_PROTOCOL_QCOM_GENERIC, &ph); + if (IS_ERR(ops)) + return PTR_ERR(ops); + + info =3D devm_kzalloc(&sdev->dev, sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + ret =3D process_scmi_memlat_of_node(sdev, info); + if (ret) + return ret; + + info->ph =3D ph; + info->ops =3D ops; + + /* Configure common events ids */ + ret =3D configure_cpucp_common_events(info); + if (ret < 0) + return dev_err_probe(&sdev->dev, ret, "failed to configure common events= \n"); + + for (i =3D 0; i < info->memory_cnt; i++) { + /* Configure per group parameters */ + ret =3D configure_cpucp_grp(&sdev->dev, info, i); + if (ret < 0) + return ret; + + for (j =3D 0; j < info->memory[i]->monitor_cnt; j++) { + /* Configure per monitor parameters */ + ret =3D configure_cpucp_mon(&sdev->dev, info, i, j); + if (ret < 0) + return ret; + } + } + + /* Set loop sampling time */ + ret =3D ops->set_param(ph, &cpucp_sample_ms, sizeof(cpucp_sample_ms), MEM= LAT_ALGO_STR, + MEMLAT_SAMPLE_MS); + if (ret < 0) + return dev_err_probe(&sdev->dev, ret, "failed to set sample_ms\n"); + + /* Set the effective cpu frequency calculation method */ + ret =3D ops->set_param(ph, &cpucp_freq_method, sizeof(cpucp_freq_method),= MEMLAT_ALGO_STR, + MEMLAT_SET_EFFECTIVE_FREQ_METHOD); + if (ret < 0) + return dev_err_probe(&sdev->dev, ret, + "failed to set effective frequency calc method\n"); + + /* Start sampling and voting timer */ + ret =3D ops->start_activity(ph, NULL, 0, MEMLAT_ALGO_STR, MEMLAT_START_TI= MER); + if (ret < 0) + dev_err_probe(&sdev->dev, ret, "failed to start memory group timer\n"); + + return ret; +} + +static int scmi_client_probe(struct scmi_device *sdev) +{ + return cpucp_memlat_init(sdev); +} + +static const struct scmi_device_id scmi_id_table[] =3D { + { SCMI_PROTOCOL_QCOM_GENERIC, "qcom-generic-ext" }, + { }, +}; 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Mon, 7 Oct 2024 06:11:08 GMT Received: from hu-sibis-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sun, 6 Oct 2024 23:11:03 -0700 From: Sibi Sankar To: , , , , , CC: , , , , , , , , Subject: [PATCH V4 5/5] arm64: dts: qcom: x1e80100: Enable LLCC/DDR/DDR_QOS dvfs Date: Mon, 7 Oct 2024 11:40:23 +0530 Message-ID: <20241007061023.1978380-6-quic_sibis@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241007061023.1978380-1-quic_sibis@quicinc.com> References: <20241007061023.1978380-1-quic_sibis@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: WI3ajMQnc0E_pXSm-x2RF5CtWFpd5PyA X-Proofpoint-GUID: WI3ajMQnc0E_pXSm-x2RF5CtWFpd5PyA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 suspectscore=0 malwarescore=0 adultscore=0 mlxlogscore=920 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410070042 Content-Type: text/plain; charset="utf-8" Enable LLCC/DDR/DDR_QOS bus scaling through the QCOM SCMI Generic Extension protocol. Signed-off-by: Sibi Sankar --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 138 +++++++++++++++++++++++++ 1 file changed, 138 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index aec3ceb502f6..24ebccd8c124 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -325,6 +326,143 @@ scmi_dvfs: protocol@13 { reg =3D <0x13>; #power-domain-cells =3D <1>; }; + + scmi_vendor: protocol@80 { + reg =3D <0x80>; + + memory-0 { + qcom,memory-type =3D ; + freq-table-hz =3D /bits/ 64 <200000000 4224000000>; + + monitor-0 { + cpus =3D <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5 &CPU6 + &CPU7 &CPU8 &CPU9 &CPU10 &CPU11>; + qcom,ipm-ceil =3D <20000000>; + operating-points-v2 =3D <&memory0_monitor0_opp_table>; + + memory0_monitor0_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-999000000 { + opp-hz =3D /bits/ 64 <999000000 547000000>; + }; + + opp-1440000000 { + opp-hz =3D /bits/ 64 <1440000000 768000000>; + }; + + opp-1671000000 { + opp-hz =3D /bits/ 64 <1671000000 1555000000>; + }; + + opp-2189000000 { + opp-hz =3D /bits/ 64 <2189000000 2092000000>; + }; + + opp-2516000000 { + opp-hz =3D /bits/ 64 <2516000000 3187000000>; + }; + + opp-3860000000 { + opp-hz =3D /bits/ 64 <3860000000 4224000000>; + }; + }; + }; + + monitor-1 { + cpus =3D <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5 &CPU6 + &CPU7 &CPU8 &CPU9 &CPU10 &CPU11>; + operating-points-v2 =3D <&memory0_monitor1_opp_table>; + qcom,compute-type; + + memory0_monitor1_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-1440000000 { + opp-hz =3D /bits/ 64 <1440000000 200000000>; + }; + + opp-2189000000 { + opp-hz =3D /bits/ 64 <2189000000 768000000>; + }; + + opp-2516000000 { + opp-hz =3D /bits/ 64 <2516000000 1555000000>; + }; + + opp-3860000000 { + opp-hz =3D /bits/ 64 <3860000000 4224000000>; + }; + }; + }; + }; + + memory-1 { + qcom,memory-type =3D ; + freq-table-hz =3D /bits/ 64 <300000000 1067000000>; + + monitor-0 { + cpus =3D <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5 &CPU6 + &CPU7 &CPU8 &CPU9 &CPU10 &CPU11>; + qcom,ipm-ceil =3D <20000000>; + operating-points-v2 =3D <&memory1_monitor0_opp_table>; + + memory1_monitor0_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-999000000 { + opp-hz =3D /bits/ 64 <999000000 300000000>; + }; + + opp-1440000000 { + opp-hz =3D /bits/ 64 <1440000000 466000000>; + }; + + opp-1671000000 { + opp-hz =3D /bits/ 64 <1671000000 600000000>; + }; + + opp-2189000000 { + opp-hz =3D /bits/ 64 <2189000000 806000000>; + }; + + opp-2516000000 { + opp-hz =3D /bits/ 64 <2516000000 933000000>; + }; + + opp-3860000000 { + opp-hz =3D /bits/ 64 <3860000000 1066000000>; + }; + }; + }; + }; + + memory-2 { + qcom,memory-type =3D ; + freq-table-hz =3D /bits/ 64 ; + + monitor-0 { + qcom,ipm-ceil =3D <20000000>; + cpus =3D <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5 &CPU6 + &CPU7 &CPU8 &CPU9 &CPU10 &CPU11>; + operating-points-v2 =3D <&memory2_monitor0_opp_table>; + + memory2_monitor0_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-2189000000 { + opp-hz =3D /bits/ 64 <2189000000>; + opp-level =3D ; + }; + + opp-3860000000 { + opp-hz =3D /bits/ 64 <3860000000>; + opp-level =3D ; + }; + }; + }; + }; + }; }; }; =20 --=20 2.34.1