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This also handle scenario, when -EDEFER is returned and useless error is printed. Signed-off-by: Anand Moon --- v2: None v1: None --- drivers/phy/rockchip/phy-rockchip-pcie.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchi= p/phy-rockchip-pcie.c index 51cc5ece0e63..51e636a1ce33 100644 --- a/drivers/phy/rockchip/phy-rockchip-pcie.c +++ b/drivers/phy/rockchip/phy-rockchip-pcie.c @@ -371,12 +371,9 @@ static int rockchip_pcie_phy_probe(struct platform_dev= ice *pdev) mutex_init(&rk_phy->pcie_mutex); =20 rk_phy->phy_rst =3D devm_reset_control_get(dev, "phy"); - if (IS_ERR(rk_phy->phy_rst)) { - if (PTR_ERR(rk_phy->phy_rst) !=3D -EPROBE_DEFER) - dev_err(dev, - "missing phy property for reset controller\n"); - return PTR_ERR(rk_phy->phy_rst); - } + if (IS_ERR(rk_phy->phy_rst)) + return dev_err_probe(&pdev->dev, PTR_ERR(rk_phy->phy_rst), + "missing phy property for reset controller\n"); =20 rk_phy->clk_pciephy_ref =3D devm_clk_get(dev, "refclk"); if (IS_ERR(rk_phy->clk_pciephy_ref)) { --=20 2.44.0 From nobody Thu Nov 28 01:49:32 2024 Received: from mail-yb1-f169.google.com (mail-yb1-f169.google.com [209.85.219.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 986E938F97 for ; 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Sun, 06 Oct 2024 20:56:41 -0700 (PDT) Received: from localhost.localdomain ([113.30.217.221]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71df0cbbac6sm3451322b3a.39.2024.10.06.20.56.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Oct 2024 20:56:41 -0700 (PDT) From: Anand Moon To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , linux-phy@lists.infradead.org (open list:GENERIC PHY FRAMEWORK), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon Subject: [PATCH v2 2/3] phy: rockchip-pcie: Use devm_clk_get_enabled() helper Date: Mon, 7 Oct 2024 09:26:10 +0530 Message-ID: <20241007035616.2701-3-linux.amoon@gmail.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241007035616.2701-1-linux.amoon@gmail.com> References: <20241007035616.2701-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use devm_clk_get_enabled() instead of devm_clk_get() to make the code cleaner and avoid calling clk_disable_unprepare(), as this is exactly what this function does. Use the dev_err_probe() helper to simplify error handling during probe. Signed-off-by: Anand Moon --- v2: Change the subject drop: Change to use/Use v1: New patch in this series --- drivers/phy/rockchip/phy-rockchip-pcie.c | 25 ++++++------------------ 1 file changed, 6 insertions(+), 19 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchi= p/phy-rockchip-pcie.c index 51e636a1ce33..a1b4b0323e9d 100644 --- a/drivers/phy/rockchip/phy-rockchip-pcie.c +++ b/drivers/phy/rockchip/phy-rockchip-pcie.c @@ -277,26 +277,16 @@ static int rockchip_pcie_phy_init(struct phy *phy) if (rk_phy->init_cnt++) goto err_out; =20 - err =3D clk_prepare_enable(rk_phy->clk_pciephy_ref); - if (err) { - dev_err(&phy->dev, "Fail to enable pcie ref clock.\n"); - goto err_refclk; - } - err =3D reset_control_assert(rk_phy->phy_rst); if (err) { dev_err(&phy->dev, "assert phy_rst err %d\n", err); - goto err_reset; + goto err_out; } =20 -err_out: mutex_unlock(&rk_phy->pcie_mutex); return 0; =20 -err_reset: - - clk_disable_unprepare(rk_phy->clk_pciephy_ref); -err_refclk: +err_out: rk_phy->init_cnt--; mutex_unlock(&rk_phy->pcie_mutex); return err; @@ -312,8 +302,6 @@ static int rockchip_pcie_phy_exit(struct phy *phy) if (--rk_phy->init_cnt) goto err_init_cnt; =20 - clk_disable_unprepare(rk_phy->clk_pciephy_ref); - err_init_cnt: mutex_unlock(&rk_phy->pcie_mutex); return 0; @@ -375,11 +363,10 @@ static int rockchip_pcie_phy_probe(struct platform_de= vice *pdev) return dev_err_probe(&pdev->dev, PTR_ERR(rk_phy->phy_rst), "missing phy property for reset controller\n"); =20 - rk_phy->clk_pciephy_ref =3D devm_clk_get(dev, "refclk"); - if (IS_ERR(rk_phy->clk_pciephy_ref)) { - dev_err(dev, "refclk not found.\n"); - return PTR_ERR(rk_phy->clk_pciephy_ref); - } + rk_phy->clk_pciephy_ref =3D devm_clk_get_enabled(dev, "refclk"); + if (IS_ERR(rk_phy->clk_pciephy_ref)) + return dev_err_probe(&pdev->dev, PTR_ERR(rk_phy->clk_pciephy_ref), + "failed to get phyclk\n"); =20 /* parse #phy-cells to see if it's legacy PHY model */ if (of_property_read_u32(dev->of_node, "#phy-cells", &phy_num)) --=20 2.44.0 From nobody Thu Nov 28 01:49:32 2024 Received: from mail-pf1-f181.google.com (mail-pf1-f181.google.com [209.85.210.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2ADD71304BA for ; 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Sun, 06 Oct 2024 20:56:46 -0700 (PDT) Received: from localhost.localdomain ([113.30.217.221]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71df0cbbac6sm3451322b3a.39.2024.10.06.20.56.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Oct 2024 20:56:46 -0700 (PDT) From: Anand Moon To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , linux-phy@lists.infradead.org (open list:GENERIC PHY FRAMEWORK), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon Subject: [PATCH v2 3/3] phy: rockchip-pcie: Use regmap_read_poll_timeout() for PCIe reference clk PLL status Date: Mon, 7 Oct 2024 09:26:11 +0530 Message-ID: <20241007035616.2701-4-linux.amoon@gmail.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241007035616.2701-1-linux.amoon@gmail.com> References: <20241007035616.2701-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace open-coded phy PCIe reference clk PLL status polling with regmap_read_poll_timeout API. This change simplifies the code without altering functionality. Signed-off-by: Anand Moon --- v2: Fix the subject, add the missing () in the function name, Fix the typo reference v1: None. --- drivers/phy/rockchip/phy-rockchip-pcie.c | 56 +++++++----------------- 1 file changed, 15 insertions(+), 41 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchi= p/phy-rockchip-pcie.c index a1b4b0323e9d..2c4d6f68f02a 100644 --- a/drivers/phy/rockchip/phy-rockchip-pcie.c +++ b/drivers/phy/rockchip/phy-rockchip-pcie.c @@ -162,7 +162,6 @@ static int rockchip_pcie_phy_power_on(struct phy *phy) struct rockchip_pcie_phy *rk_phy =3D to_pcie_phy(inst); int err =3D 0; u32 status; - unsigned long timeout; =20 mutex_lock(&rk_phy->pcie_mutex); =20 @@ -191,21 +190,11 @@ static int rockchip_pcie_phy_power_on(struct phy *phy) * so we make it large enough here. And we use loop-break * method which should not be harmful. */ - timeout =3D jiffies + msecs_to_jiffies(1000); - - err =3D -EINVAL; - while (time_before(jiffies, timeout)) { - regmap_read(rk_phy->reg_base, - rk_phy->phy_data->pcie_status, - &status); - if (status & PHY_PLL_LOCKED) { - dev_dbg(&phy->dev, "pll locked!\n"); - err =3D 0; - break; - } - msleep(20); - } - + err =3D regmap_read_poll_timeout(rk_phy->reg_base, + rk_phy->phy_data->pcie_status, + status, + status & PHY_PLL_LOCKED, + 200, 100000); if (err) { dev_err(&phy->dev, "pll lock timeout!\n"); goto err_pll_lock; @@ -214,19 +203,11 @@ static int rockchip_pcie_phy_power_on(struct phy *phy) phy_wr_cfg(rk_phy, PHY_CFG_CLK_TEST, PHY_CFG_SEPE_RATE); phy_wr_cfg(rk_phy, PHY_CFG_CLK_SCC, PHY_CFG_PLL_100M); =20 - err =3D -ETIMEDOUT; - while (time_before(jiffies, timeout)) { - regmap_read(rk_phy->reg_base, - rk_phy->phy_data->pcie_status, - &status); - if (!(status & PHY_PLL_OUTPUT)) { - dev_dbg(&phy->dev, "pll output enable done!\n"); - err =3D 0; - break; - } - msleep(20); - } - + err =3D regmap_read_poll_timeout(rk_phy->reg_base, + rk_phy->phy_data->pcie_status, + status, + !(status & PHY_PLL_OUTPUT), + 200, 100000); if (err) { dev_err(&phy->dev, "pll output enable timeout!\n"); goto err_pll_lock; @@ -236,19 +217,12 @@ static int rockchip_pcie_phy_power_on(struct phy *phy) HIWORD_UPDATE(PHY_CFG_PLL_LOCK, PHY_CFG_ADDR_MASK, PHY_CFG_ADDR_SHIFT)); - err =3D -EINVAL; - while (time_before(jiffies, timeout)) { - regmap_read(rk_phy->reg_base, - rk_phy->phy_data->pcie_status, - &status); - if (status & PHY_PLL_LOCKED) { - dev_dbg(&phy->dev, "pll relocked!\n"); - err =3D 0; - break; - } - msleep(20); - } =20 + err =3D regmap_read_poll_timeout(rk_phy->reg_base, + rk_phy->phy_data->pcie_status, + status, + status & PHY_PLL_LOCKED, + 200, 100000); if (err) { dev_err(&phy->dev, "pll relock timeout!\n"); goto err_pll_lock; --=20 2.44.0